blob: f2cedbb1568a8eaf5dd7c8a3c6ef4acc085286a1 [file] [log] [blame]
Ian Campbellcba69ee2014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Some init for sunxi platform.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
Hans de Goede66203772014-06-13 22:55:49 +020014#include <i2c.h>
Ian Campbell58358232014-05-05 11:52:28 +010015#include <netdev.h>
16#include <miiphy.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010017#include <serial.h>
18#ifdef CONFIG_SPL_BUILD
19#include <spl.h>
20#endif
21#include <asm/gpio.h>
22#include <asm/io.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/arch/timer.h>
27
Ian Campbell799aff32014-07-06 20:03:20 +010028#include <linux/compiler.h>
29
Ian Campbellcba69ee2014-05-05 11:52:26 +010030#ifdef CONFIG_SPL_BUILD
31/* Pointer to the global data structure for SPL */
32DECLARE_GLOBAL_DATA_PTR;
33
34/* The sunxi internal brom will try to loader external bootloader
35 * from mmc0, nand flash, mmc2.
36 * Unfortunately we can't check how SPL was loaded so assume
37 * it's always the first SD/MMC controller
38 */
39u32 spl_boot_device(void)
40{
41 return BOOT_DEVICE_MMC1;
42}
43
44/* No confirmation data available in SPL yet. Hardcode bootmode */
45u32 spl_boot_mode(void)
46{
47 return MMCSD_MODE_RAW;
48}
49#endif
50
51int gpio_init(void)
52{
Hans de Goedef84269c2014-06-09 11:36:58 +020053#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
Ian Campbellcba69ee2014-05-05 11:52:26 +010054 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
55 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
56 sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
Hans de Goedef84269c2014-06-09 11:36:58 +020057#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
58 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
59 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
60 sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
61#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
62 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
63 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
64 sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
65#else
66#error Unsupported console port number. Please fix pin mux settings in board.c
67#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +010068
69 return 0;
70}
71
72void reset_cpu(ulong addr)
73{
Hans de Goedec7e79de2014-06-09 11:36:56 +020074 static const struct sunxi_wdog *wdog =
75 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
76
77 /* Set the watchdog for its shortest interval (.5s) and wait */
78 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
79 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeae5de5a2014-06-13 22:55:52 +020080
81 while (1) {
82 /* sun5i sometimes gets stuck without this */
83 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
84 }
Ian Campbellcba69ee2014-05-05 11:52:26 +010085}
86
87/* do some early init */
88void s_init(void)
89{
90#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
91 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
92 asm volatile(
93 "mrc p15, 0, r0, c1, c0, 1\n"
94 "orr r0, r0, #1 << 6\n"
95 "mcr p15, 0, r0, c1, c0, 1\n");
96#endif
97
98 clock_init();
99 timer_init();
100 gpio_init();
Hans de Goede66203772014-06-13 22:55:49 +0200101 i2c_init_board();
Ian Campbellcba69ee2014-05-05 11:52:26 +0100102
103#ifdef CONFIG_SPL_BUILD
104 gd = &gdata;
105 preloader_console_init();
106
Hans de Goede66203772014-06-13 22:55:49 +0200107#ifdef CONFIG_SPL_I2C_SUPPORT
108 /* Needed early by sunxi_board_init if PMU is enabled */
109 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
110#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100111 sunxi_board_init();
112#endif
113}
114
115#ifndef CONFIG_SYS_DCACHE_OFF
116void enable_caches(void)
117{
118 /* Enable D-cache. I-cache is already enabled in start.S */
119 dcache_enable();
120}
121#endif
Ian Campbell58358232014-05-05 11:52:28 +0100122
123#ifdef CONFIG_CMD_NET
124/*
125 * Initializes on-chip ethernet controllers.
126 * to override, implement board_eth_init()
127 */
128int cpu_eth_init(bd_t *bis)
129{
Ian Campbell799aff32014-07-06 20:03:20 +0100130 __maybe_unused int rc;
Ian Campbell58358232014-05-05 11:52:28 +0100131
Hans de Goedefc703002014-07-26 17:09:13 +0200132#ifdef CONFIG_MACPWR
133 gpio_direction_output(CONFIG_MACPWR, 1);
134 mdelay(200);
135#endif
136
Hans de Goedec26fb9d2014-06-09 11:37:00 +0200137#ifdef CONFIG_SUNXI_EMAC
138 rc = sunxi_emac_initialize(bis);
139 if (rc < 0) {
140 printf("sunxi: failed to initialize emac\n");
141 return rc;
142 }
143#endif
144
Ian Campbell58358232014-05-05 11:52:28 +0100145#ifdef CONFIG_SUNXI_GMAC
146 rc = sunxi_gmac_initialize(bis);
147 if (rc < 0) {
148 printf("sunxi: failed to initialize gmac\n");
149 return rc;
150 }
151#endif
152
153 return 0;
154}
155#endif