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wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming1ced1212008-02-06 01:19:40 -06002 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30#include <command.h>
31#include <asm/cache.h>
32
James Yang591933c2008-02-08 16:44:53 -060033DECLARE_GLOBAL_DATA_PTR;
34
Andy Fleming1ced1212008-02-06 01:19:40 -060035struct cpu_type {
36 char name[15];
37 u32 soc_ver;
38};
39
40#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
41
42struct cpu_type cpu_type_list [] = {
43 CPU_TYPE_ENTRY(8533),
44 CPU_TYPE_ENTRY(8533_E),
45 CPU_TYPE_ENTRY(8540),
46 CPU_TYPE_ENTRY(8541),
47 CPU_TYPE_ENTRY(8541_E),
48 CPU_TYPE_ENTRY(8543),
49 CPU_TYPE_ENTRY(8543_E),
50 CPU_TYPE_ENTRY(8544),
51 CPU_TYPE_ENTRY(8544_E),
52 CPU_TYPE_ENTRY(8545),
53 CPU_TYPE_ENTRY(8545_E),
54 CPU_TYPE_ENTRY(8547_E),
55 CPU_TYPE_ENTRY(8548),
56 CPU_TYPE_ENTRY(8548_E),
57 CPU_TYPE_ENTRY(8555),
58 CPU_TYPE_ENTRY(8555_E),
59 CPU_TYPE_ENTRY(8560),
60 CPU_TYPE_ENTRY(8567),
61 CPU_TYPE_ENTRY(8567_E),
62 CPU_TYPE_ENTRY(8568),
63 CPU_TYPE_ENTRY(8568_E),
64 CPU_TYPE_ENTRY(8572),
65 CPU_TYPE_ENTRY(8572_E),
66};
67
wdenk42d1f032003-10-15 23:53:47 +000068int checkcpu (void)
69{
wdenk97d80fc2004-06-09 00:34:46 +000070 sys_info_t sysinfo;
71 uint lcrr; /* local bus clock ratio register */
72 uint clkdiv; /* clock divider portion of lcrr */
73 uint pvr, svr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050074 uint fam;
wdenk97d80fc2004-06-09 00:34:46 +000075 uint ver;
76 uint major, minor;
Andy Fleming1ced1212008-02-06 01:19:40 -060077 int i;
Kumar Galad4357932007-12-07 04:59:26 -060078 u32 ddr_ratio;
79 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk42d1f032003-10-15 23:53:47 +000080
wdenk97d80fc2004-06-09 00:34:46 +000081 svr = get_svr();
Andy Fleming1ced1212008-02-06 01:19:40 -060082 ver = SVR_SOC_VER(svr);
wdenk97d80fc2004-06-09 00:34:46 +000083 major = SVR_MAJ(svr);
84 minor = SVR_MIN(svr);
85
wdenk6c9e7892005-03-15 22:56:53 +000086 puts("CPU: ");
Andy Fleming1ced1212008-02-06 01:19:40 -060087
88 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
89 if (cpu_type_list[i].soc_ver == ver) {
90 puts(cpu_type_list[i].name);
91 break;
92 }
93
94 if (i == ARRAY_SIZE(cpu_type_list))
wdenk97d80fc2004-06-09 00:34:46 +000095 puts("Unknown");
Andy Fleming1ced1212008-02-06 01:19:40 -060096
wdenk97d80fc2004-06-09 00:34:46 +000097 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000098
wdenk6c9e7892005-03-15 22:56:53 +000099 pvr = get_pvr();
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500100 fam = PVR_FAM(pvr);
wdenk6c9e7892005-03-15 22:56:53 +0000101 ver = PVR_VER(pvr);
102 major = PVR_MAJ(pvr);
103 minor = PVR_MIN(pvr);
104
105 printf("Core: ");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500106 switch (fam) {
107 case PVR_FAM(PVR_85xx):
wdenk6c9e7892005-03-15 22:56:53 +0000108 puts("E500");
109 break;
110 default:
111 puts("Unknown");
112 break;
113 }
114 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
115
wdenk97d80fc2004-06-09 00:34:46 +0000116 get_sys_info(&sysinfo);
117
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500118 puts("Clock Configuration:\n");
wdenk6c9e7892005-03-15 22:56:53 +0000119 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
120 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
Kumar Galad4357932007-12-07 04:59:26 -0600121
122 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
123 switch (ddr_ratio) {
124 case 0x0:
125 printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
126 break;
127 case 0x7:
128 printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
129 break;
130 default:
131 printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
132 break;
133 }
wdenk97d80fc2004-06-09 00:34:46 +0000134
135#if defined(CFG_LBC_LCRR)
136 lcrr = CFG_LBC_LCRR;
137#else
138 {
Kumar Gala04db4002007-11-29 02:10:09 -0600139 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk97d80fc2004-06-09 00:34:46 +0000140
141 lcrr = lbc->lcrr;
142 }
143#endif
144 clkdiv = lcrr & 0x0f;
145 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
Andy Fleming151d5d92007-04-23 01:32:22 -0500146#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500147 /*
148 * Yes, the entire PQ38 family use the same
149 * bit-representation for twice the clock divider values.
150 */
151 clkdiv *= 2;
152#endif
wdenk97d80fc2004-06-09 00:34:46 +0000153 printf("LBC:%4lu MHz\n",
154 sysinfo.freqSystemBus / 1000000 / clkdiv);
155 } else {
wdenk6c9e7892005-03-15 22:56:53 +0000156 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
wdenk97d80fc2004-06-09 00:34:46 +0000157 }
158
Andy Fleming1ced1212008-02-06 01:19:40 -0600159#ifdef CONFIG_CPM2
160 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
161#endif
wdenk97d80fc2004-06-09 00:34:46 +0000162
wdenk6c9e7892005-03-15 22:56:53 +0000163 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000164
165 return 0;
166}
167
168
169/* ------------------------------------------------------------------------- */
170
171int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
172{
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800173 uint pvr;
174 uint ver;
175 pvr = get_pvr();
176 ver = PVR_VER(pvr);
177 if (ver & 1){
178 /* e500 v2 core has reset control register */
179 volatile unsigned int * rstcr;
180 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
Wolfgang Denk2f152782007-05-05 18:23:11 +0200181 *rstcr = 0x2; /* HRESET_REQ */
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800182 }else{
wdenk42d1f032003-10-15 23:53:47 +0000183 /*
184 * Initiate hard reset in debug control register DBCR0
185 * Make sure MSR[DE] = 1
186 */
urwithsughosh@gmail.comdf909682007-09-24 13:32:13 -0400187 unsigned long val, msr;
188
189 msr = mfmsr ();
190 msr |= MSR_DE;
191 mtmsr (msr);
192
Zang Roy-r6191196629cb2006-12-05 16:42:30 +0800193 val = mfspr(DBCR0);
194 val |= 0x70000000;
195 mtspr(DBCR0,val);
196 }
wdenk42d1f032003-10-15 23:53:47 +0000197 return 1;
198}
199
200
201/*
202 * Get timebase clock frequency
203 */
204unsigned long get_tbclk (void)
205{
James Yang591933c2008-02-08 16:44:53 -0600206 return (gd->bus_clk + 4UL)/8UL;
wdenk42d1f032003-10-15 23:53:47 +0000207}
208
209
210#if defined(CONFIG_WATCHDOG)
211void
212watchdog_reset(void)
213{
214 int re_enable = disable_interrupts();
215 reset_85xx_watchdog();
216 if (re_enable) enable_interrupts();
217}
218
219void
220reset_85xx_watchdog(void)
221{
222 /*
223 * Clear TSR(WIS) bit by writing 1
224 */
225 unsigned long val;
Andy Fleming03b81b42007-04-23 01:44:44 -0500226 val = mfspr(SPRN_TSR);
227 val |= TSR_WIS;
228 mtspr(SPRN_TSR, val);
wdenk42d1f032003-10-15 23:53:47 +0000229}
230#endif /* CONFIG_WATCHDOG */
231
232#if defined(CONFIG_DDR_ECC)
wdenk42d1f032003-10-15 23:53:47 +0000233void dma_init(void) {
Kumar Gala04db4002007-11-29 02:10:09 -0600234 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000235
236 dma->satr0 = 0x02c40000;
237 dma->datr0 = 0x02c40000;
Andy Fleming03b81b42007-04-23 01:44:44 -0500238 dma->sr0 = 0xfffffff; /* clear any errors */
wdenk42d1f032003-10-15 23:53:47 +0000239 asm("sync; isync; msync");
240 return;
241}
242
243uint dma_check(void) {
Kumar Gala04db4002007-11-29 02:10:09 -0600244 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000245 volatile uint status = dma->sr0;
246
247 /* While the channel is busy, spin */
248 while((status & 4) == 4) {
249 status = dma->sr0;
250 }
251
Andy Fleming03b81b42007-04-23 01:44:44 -0500252 /* clear MR0[CS] channel start bit */
253 dma->mr0 &= 0x00000001;
254 asm("sync;isync;msync");
255
wdenk42d1f032003-10-15 23:53:47 +0000256 if (status != 0) {
257 printf ("DMA Error: status = %x\n", status);
258 }
259 return status;
260}
261
262int dma_xfer(void *dest, uint count, void *src) {
Kumar Gala04db4002007-11-29 02:10:09 -0600263 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000264
265 dma->dar0 = (uint) dest;
266 dma->sar0 = (uint) src;
267 dma->bcr0 = count;
268 dma->mr0 = 0xf000004;
269 asm("sync;isync;msync");
270 dma->mr0 = 0xf000005;
271 asm("sync;isync;msync");
272 return dma_check();
273}
274#endif