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York Sun7288c2c2015-03-20 19:28:23 -07001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
13#include <fdt_support.h>
14#include <libfdt.h>
15#include <fsl_debug_server.h>
16#include <fsl-mc/fsl_mc.h>
17#include <environment.h>
18#include <i2c.h>
19#include <asm/arch-fsl-lsch3/soc.h>
20
21#include "../common/qixis.h"
22#include "ls2085aqds_qixis.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26unsigned long long get_qixis_addr(void)
27{
28 unsigned long long addr;
29
30 if (gd->flags & GD_FLG_RELOC)
31 addr = QIXIS_BASE_PHYS;
32 else
33 addr = QIXIS_BASE_PHYS_EARLY;
34
35 /*
36 * IFC address under 256MB is mapped to 0x30000000, any address above
37 * is mapped to 0x5_10000000 up to 4GB.
38 */
39 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
40
41 return addr;
42}
43
44int checkboard(void)
45{
46 char buf[64];
47 u8 sw;
48 static const char *const freq[] = {"100", "125", "156.25",
49 "100 separate SSCG"};
50 int clock;
51
Prabhakar Kushwahaff1b8e32015-05-28 14:54:07 +053052 cpu_name(buf);
53 printf("Board: %s-QDS, ", buf);
54
York Sun7288c2c2015-03-20 19:28:23 -070055 sw = QIXIS_READ(arch);
York Sun7288c2c2015-03-20 19:28:23 -070056 printf("Board Arch: V%d, ", sw >> 4);
57 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
58
Prabhakar Kushwahaff1b8e32015-05-28 14:54:07 +053059 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
60
York Sun7288c2c2015-03-20 19:28:23 -070061 sw = QIXIS_READ(brdcfg[0]);
62 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
63
64 if (sw < 0x8)
65 printf("vBank: %d\n", sw);
66 else if (sw == 0x8)
67 puts("PromJet\n");
68 else if (sw == 0x9)
69 puts("NAND\n");
70 else if (sw == 0x15)
71 printf("IFCCard\n");
72 else
73 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
74
75 printf("FPGA: v%d (%s), build %d",
76 (int)QIXIS_READ(scver), qixis_read_tag(buf),
77 (int)qixis_read_minor());
78 /* the timestamp string contains "\n" at the end */
79 printf(" on %s", qixis_read_time(buf));
80
81 /*
82 * Display the actual SERDES reference clocks as configured by the
83 * dip switches on the board. Note that the SWx registers could
84 * technically be set to force the reference clocks to match the
85 * values that the SERDES expects (or vice versa). For now, however,
86 * we just display both values and hope the user notices when they
87 * don't match.
88 */
89 puts("SERDES1 Reference : ");
90 sw = QIXIS_READ(brdcfg[2]);
91 clock = (sw >> 6) & 3;
92 printf("Clock1 = %sMHz ", freq[clock]);
93 clock = (sw >> 4) & 3;
94 printf("Clock2 = %sMHz", freq[clock]);
95
96 puts("\nSERDES2 Reference : ");
97 clock = (sw >> 2) & 3;
98 printf("Clock1 = %sMHz ", freq[clock]);
99 clock = (sw >> 0) & 3;
100 printf("Clock2 = %sMHz\n", freq[clock]);
101
102 return 0;
103}
104
105unsigned long get_board_sys_clk(void)
106{
107 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
108
109 switch (sysclk_conf & 0x0F) {
110 case QIXIS_SYSCLK_83:
111 return 83333333;
112 case QIXIS_SYSCLK_100:
113 return 100000000;
114 case QIXIS_SYSCLK_125:
115 return 125000000;
116 case QIXIS_SYSCLK_133:
117 return 133333333;
118 case QIXIS_SYSCLK_150:
119 return 150000000;
120 case QIXIS_SYSCLK_160:
121 return 160000000;
122 case QIXIS_SYSCLK_166:
123 return 166666666;
124 }
125 return 66666666;
126}
127
128unsigned long get_board_ddr_clk(void)
129{
130 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
131
132 switch ((ddrclk_conf & 0x30) >> 4) {
133 case QIXIS_DDRCLK_100:
134 return 100000000;
135 case QIXIS_DDRCLK_125:
136 return 125000000;
137 case QIXIS_DDRCLK_133:
138 return 133333333;
139 }
140 return 66666666;
141}
142
143int select_i2c_ch_pca9547(u8 ch)
144{
145 int ret;
146
147 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
148 if (ret) {
149 puts("PCA: failed to select proper channel\n");
150 return ret;
151 }
152
153 return 0;
154}
155
156int board_init(void)
157{
158 init_final_memctl_regs();
159
160#ifdef CONFIG_ENV_IS_NOWHERE
161 gd->env_addr = (ulong)&default_environment[0];
162#endif
163 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
164
165 return 0;
166}
167
168int board_early_init_f(void)
169{
170 fsl_lsch3_early_init_f();
171 return 0;
172}
173
174void detail_board_ddr_info(void)
175{
176 puts("\nDDR ");
177 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
178 print_ddr_info(0);
179 if (gd->bd->bi_dram[2].size) {
180 puts("\nDP-DDR ");
181 print_size(gd->bd->bi_dram[2].size, "");
182 print_ddr_info(CONFIG_DP_DDR_CTRL);
183 }
184}
185
186int dram_init(void)
187{
188 gd->ram_size = initdram(0);
189
190 return 0;
191}
192
193#if defined(CONFIG_ARCH_MISC_INIT)
194int arch_misc_init(void)
195{
196#ifdef CONFIG_FSL_DEBUG_SERVER
197 debug_server_init();
198#endif
199
200 return 0;
201}
202#endif
203
204unsigned long get_dram_size_to_hide(void)
205{
206 unsigned long dram_to_hide = 0;
207
208/* Carve the Debug Server private DRAM block from the end of DRAM */
209#ifdef CONFIG_FSL_DEBUG_SERVER
210 dram_to_hide += debug_server_get_dram_block_size();
211#endif
212
213/* Carve the MC private DRAM block from the end of DRAM */
214#ifdef CONFIG_FSL_MC_ENET
215 dram_to_hide += mc_get_dram_block_size();
216#endif
217
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530218 return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
York Sun7288c2c2015-03-20 19:28:23 -0700219}
220
York Sun7288c2c2015-03-20 19:28:23 -0700221#ifdef CONFIG_FSL_MC_ENET
222void fdt_fixup_board_enet(void *fdt)
223{
224 int offset;
225
226 offset = fdt_path_offset(fdt, "/fsl-mc");
227
228 if (offset < 0)
229 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
230
231 if (offset < 0) {
232 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
233 __func__, offset);
234 return;
235 }
236
237 if (get_mc_boot_status() == 0)
238 fdt_status_okay(fdt, offset);
239 else
240 fdt_status_fail(fdt, offset);
241}
242#endif
243
244#ifdef CONFIG_OF_BOARD_SETUP
245int ft_board_setup(void *blob, bd_t *bd)
246{
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530247 u64 base[CONFIG_NR_DRAM_BANKS];
248 u64 size[CONFIG_NR_DRAM_BANKS];
York Sun7288c2c2015-03-20 19:28:23 -0700249
250 ft_cpu_setup(blob, bd);
251
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530252 /* fixup DT for the two GPP DDR banks */
253 base[0] = gd->bd->bi_dram[0].start;
254 size[0] = gd->bd->bi_dram[0].size;
255 base[1] = gd->bd->bi_dram[1].start;
256 size[1] = gd->bd->bi_dram[1].size;
257
258 fdt_fixup_memory_banks(blob, base, size, 2);
York Sun7288c2c2015-03-20 19:28:23 -0700259
260#ifdef CONFIG_FSL_MC_ENET
261 fdt_fixup_board_enet(blob);
262 fsl_mc_ldpaa_exit(bd);
263#endif
264
265 return 0;
266}
267#endif
268
269void qixis_dump_switch(void)
270{
271 int i, nr_of_cfgsw;
272
273 QIXIS_WRITE(cms[0], 0x00);
274 nr_of_cfgsw = QIXIS_READ(cms[1]);
275
276 puts("DIP switch settings dump:\n");
277 for (i = 1; i <= nr_of_cfgsw; i++) {
278 QIXIS_WRITE(cms[0], i);
279 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
280 }
281}