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gerrit.cesnet.cz / github / trini / u-boot / 8142340ee3847c6422294fad0f1adc01c9d27e2b / . / arch / x86 / dts / bayleybay.dts
blob: 4a50d8665e59cce41509450fd38a7b6660ef18be [file] [log] [blame]
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]1/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/x86-gpio.h>
Bin Mengfe3fbd32015-07-30 03:49:18 -0700[diff] [blame]10#include <dt-bindings/interrupt-router/intel-irq.h>
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]11
12/include/ "skeleton.dtsi"
Simon Glass6b44ae62015-11-11 10:05:43 -0700[diff] [blame]13/include/ "keyboard.dtsi"
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]14/include/ "serial.dtsi"
15/include/ "rtc.dtsi"
Bin Meng80af3982015-11-13 00:11:22 -0800[diff] [blame]16/include/ "tsc_timer.dtsi"
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]17
18/ {
19 model = "Intel Bayley Bay";
20 compatible = "intel,bayleybay", "intel,baytrail";
21
22 aliases {
23 serial0 = &serial;
Bin Meng81aaa3d2016-01-27 00:56:34 -0800[diff] [blame]24 spi0 = &spi;
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]25 };
26
27 config {
28 silent_console = <0>;
29 };
30
31 chosen {
32 stdout-path = "/serial";
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 device_type = "cpu";
41 compatible = "intel,baytrail-cpu";
42 reg = <0>;
43 intel,apic-id = <0>;
44 };
45
46 cpu@1 {
47 device_type = "cpu";
48 compatible = "intel,baytrail-cpu";
49 reg = <1>;
50 intel,apic-id = <2>;
51 };
52
53 cpu@2 {
54 device_type = "cpu";
55 compatible = "intel,baytrail-cpu";
56 reg = <2>;
57 intel,apic-id = <4>;
58 };
59
60 cpu@3 {
61 device_type = "cpu";
62 compatible = "intel,baytrail-cpu";
63 reg = <3>;
64 intel,apic-id = <6>;
65 };
66 };
67
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]68 pci {
69 compatible = "pci-x86";
70 #address-cells = <3>;
71 #size-cells = <2>;
72 u-boot,dm-pre-reloc;
73 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
74 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
75 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Mengfe3fbd32015-07-30 03:49:18 -0700[diff] [blame]76
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]77 pch@1f,0 {
Bin Mengfe3fbd32015-07-30 03:49:18 -0700[diff] [blame]78 reg = <0x0000f800 0 0 0 0>;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]79 compatible = "intel,pch9";
Bin Meng3ddc1c72016-02-01 01:40:47 -0800[diff] [blame]80 #address-cells = <1>;
81 #size-cells = <1>;
Bin Mengfe3fbd32015-07-30 03:49:18 -0700[diff] [blame]82
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]83 irq-router {
84 compatible = "intel,irq-router";
85 intel,pirq-config = "ibase";
86 intel,ibase-offset = <0x50>;
Bin Mengce8dd772016-05-07 07:46:15 -0700[diff] [blame]87 intel,actl-addr = <0>;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]88 intel,pirq-link = <8 8>;
89 intel,pirq-mask = <0xdee0>;
90 intel,pirq-routing = <
91 /* BayTrail PCI devices */
92 PCI_BDF(0, 2, 0) INTA PIRQA
93 PCI_BDF(0, 3, 0) INTA PIRQA
94 PCI_BDF(0, 16, 0) INTA PIRQA
95 PCI_BDF(0, 17, 0) INTA PIRQA
96 PCI_BDF(0, 18, 0) INTA PIRQA
97 PCI_BDF(0, 19, 0) INTA PIRQA
98 PCI_BDF(0, 20, 0) INTA PIRQA
99 PCI_BDF(0, 21, 0) INTA PIRQA
100 PCI_BDF(0, 22, 0) INTA PIRQA
101 PCI_BDF(0, 23, 0) INTA PIRQA
102 PCI_BDF(0, 24, 0) INTA PIRQA
103 PCI_BDF(0, 24, 1) INTC PIRQC
104 PCI_BDF(0, 24, 2) INTD PIRQD
105 PCI_BDF(0, 24, 3) INTB PIRQB
106 PCI_BDF(0, 24, 4) INTA PIRQA
107 PCI_BDF(0, 24, 5) INTC PIRQC
108 PCI_BDF(0, 24, 6) INTD PIRQD
109 PCI_BDF(0, 24, 7) INTB PIRQB
110 PCI_BDF(0, 26, 0) INTA PIRQA
111 PCI_BDF(0, 27, 0) INTA PIRQA
112 PCI_BDF(0, 28, 0) INTA PIRQA
113 PCI_BDF(0, 28, 1) INTB PIRQB
114 PCI_BDF(0, 28, 2) INTC PIRQC
115 PCI_BDF(0, 28, 3) INTD PIRQD
116 PCI_BDF(0, 29, 0) INTA PIRQA
117 PCI_BDF(0, 30, 0) INTA PIRQA
118 PCI_BDF(0, 30, 1) INTD PIRQD
119 PCI_BDF(0, 30, 2) INTB PIRQB
120 PCI_BDF(0, 30, 3) INTC PIRQC
121 PCI_BDF(0, 30, 4) INTD PIRQD
122 PCI_BDF(0, 30, 5) INTB PIRQB
123 PCI_BDF(0, 31, 3) INTB PIRQB
124
125 /*
126 * PCIe root ports downstream
127 * interrupts
128 */
129 PCI_BDF(1, 0, 0) INTA PIRQA
130 PCI_BDF(1, 0, 0) INTB PIRQB
131 PCI_BDF(1, 0, 0) INTC PIRQC
132 PCI_BDF(1, 0, 0) INTD PIRQD
133 PCI_BDF(2, 0, 0) INTA PIRQB
134 PCI_BDF(2, 0, 0) INTB PIRQC
135 PCI_BDF(2, 0, 0) INTC PIRQD
136 PCI_BDF(2, 0, 0) INTD PIRQA
137 PCI_BDF(3, 0, 0) INTA PIRQC
138 PCI_BDF(3, 0, 0) INTB PIRQD
139 PCI_BDF(3, 0, 0) INTC PIRQA
140 PCI_BDF(3, 0, 0) INTD PIRQB
141 PCI_BDF(4, 0, 0) INTA PIRQD
142 PCI_BDF(4, 0, 0) INTB PIRQA
143 PCI_BDF(4, 0, 0) INTC PIRQB
144 PCI_BDF(4, 0, 0) INTD PIRQC
145 >;
146 };
147
Bin Meng81aaa3d2016-01-27 00:56:34 -0800[diff] [blame]148 spi: spi {
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]149 #address-cells = <1>;
150 #size-cells = <0>;
Bin Meng1f9eb592016-02-01 01:40:37 -0800[diff] [blame]151 compatible = "intel,ich9-spi";
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]152 spi-flash@0 {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 reg = <0>;
156 compatible = "winbond,w25q64dw",
157 "spi-flash";
158 memory-map = <0xff800000 0x00800000>;
159 rw-mrc-cache {
160 label = "rw-mrc-cache";
161 reg = <0x006e0000 0x00010000>;
162 };
163 };
164 };
Bin Meng3ddc1c72016-02-01 01:40:47 -0800[diff] [blame]165
166 gpioa {
167 compatible = "intel,ich6-gpio";
168 u-boot,dm-pre-reloc;
169 reg = <0 0x20>;
170 bank-name = "A";
171 };
172
173 gpiob {
174 compatible = "intel,ich6-gpio";
175 u-boot,dm-pre-reloc;
176 reg = <0x20 0x20>;
177 bank-name = "B";
178 };
179
180 gpioc {
181 compatible = "intel,ich6-gpio";
182 u-boot,dm-pre-reloc;
183 reg = <0x40 0x20>;
184 bank-name = "C";
185 };
186
187 gpiod {
188 compatible = "intel,ich6-gpio";
189 u-boot,dm-pre-reloc;
190 reg = <0x60 0x20>;
191 bank-name = "D";
192 };
193
194 gpioe {
195 compatible = "intel,ich6-gpio";
196 u-boot,dm-pre-reloc;
197 reg = <0x80 0x20>;
198 bank-name = "E";
199 };
200
201 gpiof {
202 compatible = "intel,ich6-gpio";
203 u-boot,dm-pre-reloc;
204 reg = <0xA0 0x20>;
205 bank-name = "F";
206 };
Bin Mengfe3fbd32015-07-30 03:49:18 -0700[diff] [blame]207 };
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]208 };
209
Andrew Bradfordf3b84a32015-08-07 08:36:35 -0400[diff] [blame]210 fsp {
211 compatible = "intel,baytrail-fsp";
212 fsp,mrc-init-tseg-size = <0>;
213 fsp,mrc-init-mmio-size = <0x800>;
214 fsp,mrc-init-spd-addr1 = <0xa0>;
215 fsp,mrc-init-spd-addr2 = <0xa2>;
216 fsp,emmc-boot-mode = <2>;
217 fsp,enable-sdio;
218 fsp,enable-sdcard;
219 fsp,enable-hsuart1;
220 fsp,enable-spi;
221 fsp,enable-sata;
222 fsp,sata-mode = <1>;
223 fsp,enable-lpe;
224 fsp,lpss-sio-enable-pci-mode;
225 fsp,enable-dma0;
226 fsp,enable-dma1;
227 fsp,enable-i2c0;
228 fsp,enable-i2c1;
229 fsp,enable-i2c2;
230 fsp,enable-i2c3;
231 fsp,enable-i2c4;
232 fsp,enable-i2c5;
233 fsp,enable-i2c6;
234 fsp,enable-pwm0;
235 fsp,enable-pwm1;
236 fsp,igd-dvmt50-pre-alloc = <2>;
237 fsp,aperture-size = <2>;
238 fsp,gtt-size = <2>;
239 fsp,serial-debug-port-address = <0x3f8>;
240 fsp,serial-debug-port-type = <1>;
241 fsp,scc-enable-pci-mode;
242 fsp,os-selection = <4>;
243 fsp,emmc45-ddr50-enabled;
244 fsp,emmc45-retune-timer-value = <8>;
245 fsp,enable-igd;
246 };
247
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]248 microcode {
249 update@0 {
250#include "microcode/m0230671117.dtsi"
251 };
Bin Meng5fb01512015-08-15 14:37:50 -0600[diff] [blame]252 update@1 {
Bin Mengbab4b962016-05-23 15:25:20 +0800[diff] [blame]253#include "microcode/m0130673325.dtsi"
Bin Meng5fb01512015-08-15 14:37:50 -0600[diff] [blame]254 };
255 update@2 {
Bin Mengbab4b962016-05-23 15:25:20 +0800[diff] [blame]256#include "microcode/m0130679907.dtsi"
Bin Meng5fb01512015-08-15 14:37:50 -0600[diff] [blame]257 };
Bin Meng9b911be2015-07-30 03:49:17 -0700[diff] [blame]258 };
259
260};