blob: a11add559134955129b5254ac5b438a79229bc9a [file] [log] [blame]
Thomas Chou8cbb0dd2010-04-21 08:40:59 +08001/*
2 * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This file is generated by sopc-create-config-files.
9 */
10#ifndef _CUSTOM_FPGA_H_
11#define _CUSTOM_FPGA_H_
12
13/* generated from std_1c20.sopc */
14
15/* cpu.data_master is a altera_nios2 */
16#define CONFIG_SYS_CLK_FREQ 50000000
17#define CONFIG_SYS_RESET_ADDR 0x00000000
18#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
19#define CONFIG_SYS_ICACHE_SIZE 4096
20#define CONFIG_SYS_ICACHELINE_SIZE 32
21#define CONFIG_SYS_DCACHE_SIZE 2048
22#define CONFIG_SYS_DCACHELINE_SIZE 4
23
24/* sdram.s1 is a altera_avalon_new_sdram_controller */
25#define CONFIG_SYS_SDRAM_BASE 0x01000000
26#define CONFIG_SYS_SDRAM_SIZE 0x01000000
27
28/* uart1.s1 is a altera_avalon_uart */
29#define CONFIG_SYS_UART_BASE 0x82120840
30#define CONFIG_SYS_UART_FREQ 50000000
31#define CONFIG_SYS_UART_BAUD 115200
32
33/* lan91c111.s1 is a altera_avalon_lan91c111 */
34#define CONFIG_SMC91111_BASE 0x82110300
35#define CONFIG_SMC91111
36#define CONFIG_SMC_USE_32_BIT
37
Thomas Chou551265f2010-04-30 11:34:18 +080038/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */
39#define EPCS_CONTROLLER_REG_BASE 0x82100200
40#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE }
41#define CONFIG_ALTERA_SPI
42#define CONFIG_CMD_SPI
43#define CONFIG_CMD_SF
44#define CONFIG_SF_DEFAULT_SPEED 30000000
45#define CONFIG_SPI_FLASH
46#define CONFIG_SPI_FLASH_STMICRO
47
Thomas Chou8cbb0dd2010-04-21 08:40:59 +080048/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
49#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
50
51/* led_pio.s1 is a altera_avalon_pio */
52#define LED_PIO_BASE 0x82120870
53
54/* high_res_timer.s1 is a altera_avalon_timer */
55#define CONFIG_SYS_TIMER_BASE 0x82120820
56#define CONFIG_SYS_TIMER_IRQ 3
57#define CONFIG_SYS_TIMER_FREQ 50000000
58
59/* ext_flash.s1 is a altera_avalon_cfi_flash */
60#define CONFIG_SYS_FLASH_BASE 0x80000000
61#define CONFIG_FLASH_CFI_DRIVER
62#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
63#define CONFIG_SYS_FLASH_CFI
64#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
65#define CONFIG_SYS_FLASH_PROTECTION
66#define CONFIG_SYS_MAX_FLASH_BANKS 1
67#define CONFIG_SYS_MAX_FLASH_SECT 1024
68
69/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
70#define CONFIG_SYS_SRAM_BASE 0x02000000
71#define CONFIG_SYS_SRAM_SIZE 0x00100000
72
73/* sysid.control_slave is a altera_avalon_sysid */
74#define CONFIG_SYS_SYSID_BASE 0x821208b8
75
76#endif /* _CUSTOM_FPGA_H_ */