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Bin Meng568868d2014-12-12 21:05:24 +08001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
Bin Meng9c7dea62015-05-25 22:35:04 +08009#include <dt-bindings/interrupt-router/intel-irq.h>
10
Bin Meng120c4162014-12-24 13:06:39 +080011/include/ "skeleton.dtsi"
Bin Meng9ca5a0c2014-12-24 13:06:38 +080012/include/ "serial.dtsi"
Bin Mengb0014b62015-06-23 12:18:43 +080013/include/ "rtc.dtsi"
Bin Meng568868d2014-12-12 21:05:24 +080014
15/ {
Bin Meng568868d2014-12-12 21:05:24 +080016 model = "Intel Crown Bay";
17 compatible = "intel,crownbay", "intel,queensbay";
18
Bin Meng0a9bb482015-04-15 12:00:11 +080019 aliases {
20 spi0 = "/spi";
21 };
22
Bin Meng568868d2014-12-12 21:05:24 +080023 config {
24 silent_console = <0>;
25 };
26
Bin Meng990acd02015-06-17 11:15:39 +080027 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "cpu-x86";
34 reg = <0>;
35 intel,apic-id = <0>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "cpu-x86";
41 reg = <1>;
42 intel,apic-id = <1>;
43 };
44
45 };
46
Bin Meng568868d2014-12-12 21:05:24 +080047 gpioa {
48 compatible = "intel,ich6-gpio";
49 u-boot,dm-pre-reloc;
50 reg = <0 0x20>;
51 bank-name = "A";
52 };
53
54 gpiob {
55 compatible = "intel,ich6-gpio";
56 u-boot,dm-pre-reloc;
57 reg = <0x20 0x20>;
58 bank-name = "B";
59 };
60
Bin Meng120c4162014-12-24 13:06:39 +080061 chosen {
Bin Mengb21b2082014-12-31 16:05:14 +080062 /*
63 * By default the legacy superio serial port is used as the
64 * U-Boot serial console. If we want to use UART from Topcliff
65 * PCH as the console, change this property to &pciuart#.
66 *
67 * For example, stdout-path = &pciuart0 will use the first
68 * UART on Topcliff PCH.
69 */
Bin Meng120c4162014-12-24 13:06:39 +080070 stdout-path = "/serial";
Bin Meng568868d2014-12-12 21:05:24 +080071 };
72
Bin Meng568868d2014-12-12 21:05:24 +080073 spi {
74 #address-cells = <1>;
75 #size-cells = <0>;
Bin Meng0a9bb482015-04-15 12:00:11 +080076 compatible = "intel,ich-spi";
Bin Meng568868d2014-12-12 21:05:24 +080077 spi-flash@0 {
78 reg = <0>;
79 compatible = "sst,25vf016b", "spi-flash";
80 memory-map = <0xffe00000 0x00200000>;
81 };
82 };
Simon Glass0f61de82014-12-17 15:50:37 +080083
84 microcode {
85 update@0 {
86#include "microcode/m0220661105_cv.dtsi"
87 };
88 };
89
Bin Mengb21b2082014-12-31 16:05:14 +080090 pci {
91 #address-cells = <3>;
92 #size-cells = <2>;
93 compatible = "intel,pci";
94 device_type = "pci";
95
96 pcie@17,0 {
97 #address-cells = <3>;
98 #size-cells = <2>;
99 compatible = "intel,pci";
100 device_type = "pci";
101
102 topcliff@0,0 {
103 #address-cells = <3>;
104 #size-cells = <2>;
105 compatible = "intel,pci";
106 device_type = "pci";
107
108 pciuart0: uart@a,1 {
109 compatible = "pci8086,8811.00",
110 "pci8086,8811",
111 "pciclass,070002",
112 "pciclass,0700",
113 "x86-uart";
114 reg = <0x00025100 0x0 0x0 0x0 0x0
115 0x01025110 0x0 0x0 0x0 0x0>;
116 reg-shift = <0>;
117 clock-frequency = <1843200>;
118 current-speed = <115200>;
119 };
120
121 pciuart1: uart@a,2 {
122 compatible = "pci8086,8812.00",
123 "pci8086,8812",
124 "pciclass,070002",
125 "pciclass,0700",
126 "x86-uart";
127 reg = <0x00025200 0x0 0x0 0x0 0x0
128 0x01025210 0x0 0x0 0x0 0x0>;
129 reg-shift = <0>;
130 clock-frequency = <1843200>;
131 current-speed = <115200>;
132 };
133
134 pciuart2: uart@a,3 {
135 compatible = "pci8086,8813.00",
136 "pci8086,8813",
137 "pciclass,070002",
138 "pciclass,0700",
139 "x86-uart";
140 reg = <0x00025300 0x0 0x0 0x0 0x0
141 0x01025310 0x0 0x0 0x0 0x0>;
142 reg-shift = <0>;
143 clock-frequency = <1843200>;
144 current-speed = <115200>;
145 };
146
147 pciuart3: uart@a,4 {
148 compatible = "pci8086,8814.00",
149 "pci8086,8814",
150 "pciclass,070002",
151 "pciclass,0700",
152 "x86-uart";
153 reg = <0x00025400 0x0 0x0 0x0 0x0
154 0x01025410 0x0 0x0 0x0 0x0>;
155 reg-shift = <0>;
156 clock-frequency = <1843200>;
157 current-speed = <115200>;
158 };
159 };
160 };
Bin Meng9c7dea62015-05-25 22:35:04 +0800161
162 irq-router@1f,0 {
163 reg = <0x0000f800 0 0 0 0>;
164 compatible = "intel,irq-router";
165 intel,pirq-config = "pci";
166 intel,pirq-link = <0x60 8>;
167 intel,pirq-mask = <0xdee0>;
168 intel,pirq-routing = <
169 /* TunnelCreek PCI devices */
170 PCI_BDF(0, 2, 0) INTA PIRQE
171 PCI_BDF(0, 3, 0) INTA PIRQF
172 PCI_BDF(0, 23, 0) INTA PIRQE
173 PCI_BDF(0, 24, 0) INTA PIRQF
174 PCI_BDF(0, 25, 0) INTA PIRQG
175 PCI_BDF(0, 26, 0) INTA PIRQH
176 PCI_BDF(0, 27, 0) INTA PIRQG
177 /*
178 * Topcliff PCI devices
179 *
180 * Note on the Crown Bay board, Topcliff chipset
181 * is connected to TunnelCreek PCIe port 0, so
182 * its bus number is 1 for its PCIe port and 2
183 * for its PCI devices per U-Boot currnet PCI
184 * bus enumeration algorithm.
185 */
186 PCI_BDF(1, 0, 0) INTA PIRQA
187 PCI_BDF(2, 0, 1) INTA PIRQA
188 PCI_BDF(2, 0, 2) INTA PIRQA
189 PCI_BDF(2, 2, 0) INTB PIRQB
190 PCI_BDF(2, 2, 1) INTB PIRQB
191 PCI_BDF(2, 2, 2) INTB PIRQB
192 PCI_BDF(2, 2, 3) INTB PIRQB
193 PCI_BDF(2, 2, 4) INTB PIRQB
194 PCI_BDF(2, 4, 0) INTC PIRQC
195 PCI_BDF(2, 4, 1) INTC PIRQC
196 PCI_BDF(2, 6, 0) INTD PIRQD
197 PCI_BDF(2, 8, 0) INTA PIRQA
198 PCI_BDF(2, 8, 1) INTA PIRQA
199 PCI_BDF(2, 8, 2) INTA PIRQA
200 PCI_BDF(2, 8, 3) INTA PIRQA
201 PCI_BDF(2, 10, 0) INTB PIRQB
202 PCI_BDF(2, 10, 1) INTB PIRQB
203 PCI_BDF(2, 10, 2) INTB PIRQB
204 PCI_BDF(2, 10, 3) INTB PIRQB
205 PCI_BDF(2, 10, 4) INTB PIRQB
206 PCI_BDF(2, 12, 0) INTC PIRQC
207 PCI_BDF(2, 12, 1) INTC PIRQC
208 PCI_BDF(2, 12, 2) INTC PIRQC
209 PCI_BDF(2, 12, 3) INTC PIRQC
210 PCI_BDF(2, 12, 4) INTC PIRQC
211 >;
212 };
Bin Mengb21b2082014-12-31 16:05:14 +0800213 };
214
Bin Meng568868d2014-12-12 21:05:24 +0800215};