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stroese1bc0f142004-12-16 18:20:14 +00001/*
Matthias Fuchs0b987252008-04-21 14:42:11 +02002 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
stroese1bc0f142004-12-16 18:20:14 +00005 * (C) Copyright 2001-2003
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
Matthias Fuchs0b987252008-04-21 14:42:11 +020029#include <asm/io.h>
stroese1bc0f142004-12-16 18:20:14 +000030#include <command.h>
31#include <malloc.h>
Matthias Fuchs0b987252008-04-21 14:42:11 +020032#include <flash.h>
33#include <asm/4xx_pci.h>
34#include <pci.h>
stroese1bc0f142004-12-16 18:20:14 +000035
Wolfgang Denkd87080b2006-03-31 18:32:53 +020036DECLARE_GLOBAL_DATA_PTR;
stroese1bc0f142004-12-16 18:20:14 +000037
Matthias Fuchs0b987252008-04-21 14:42:11 +020038#undef FPGA_DEBUG
stroese1bc0f142004-12-16 18:20:14 +000039
40extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
41extern void lxt971_no_sleep(void);
Matthias Fuchs0b987252008-04-21 14:42:11 +020042extern ulong flash_get_size (ulong base, int banknum);
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
stroese1bc0f142004-12-16 18:20:14 +000045
46/* fpga configuration data - gzip compressed and generated by bin2c */
47const unsigned char fpgadata[] =
48{
49#include "fpgadata.c"
50};
51
52/*
53 * include common fpga code (for esd boards)
54 */
55#include "../common/fpga.c"
56
stroese1bc0f142004-12-16 18:20:14 +000057/* Prototypes */
58int gunzip(void *, int, unsigned char *, unsigned long *);
59
stroese1bc0f142004-12-16 18:20:14 +000060#ifdef CONFIG_LCD_USED
61/* logo bitmap data - gzip compressed and generated by bin2c */
62unsigned char logo_bmp[] =
63{
Matthias Fuchs0b987252008-04-21 14:42:11 +020064#include "logo_640_480_24bpp.c"
stroese1bc0f142004-12-16 18:20:14 +000065};
66
67/*
68 * include common lcd code (for esd boards)
69 */
70#include "../common/lcd.c"
Matthias Fuchs0b987252008-04-21 14:42:11 +020071#include "../common/s1d13505_640_480_16bpp.h"
72#include "../common/s1d13806_640_480_16bpp.h"
stroese1bc0f142004-12-16 18:20:14 +000073#endif /* CONFIG_LCD_USED */
74
Matthias Fuchs0b987252008-04-21 14:42:11 +020075/*
76 * include common auto-update code (for esd boards)
77 */
78#include "../common/auto_update.h"
79
80au_image_t au_image[] = {
81 {"preinst.img", 0, -1, AU_SCRIPT},
82 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
83 {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
84 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
85 {"work.img", 0xfe500000, 0x01400000, AU_NOR},
86 {"data.img", 0xff900000, 0x00580000, AU_NOR},
87 {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
88 {"postinst.img", 0, 0, AU_SCRIPT},
89};
90
91int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
stroese1bc0f142004-12-16 18:20:14 +000092
stroese04e93ec2005-04-13 10:06:07 +000093int board_revision(void)
94{
95 unsigned long cntrl0Reg;
Matthias Fuchs049216f2009-02-20 10:19:18 +010096 unsigned long value;
stroese04e93ec2005-04-13 10:06:07 +000097
98 /*
99 * Get version of APC405 board from GPIO's
100 */
101
Matthias Fuchs0b987252008-04-21 14:42:11 +0200102 /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
stroese04e93ec2005-04-13 10:06:07 +0000103 cntrl0Reg = mfdcr(cntrl0);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200104 mtdcr(cntrl0, cntrl0Reg | 0x03800000);
105 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
106 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
stroese04e93ec2005-04-13 10:06:07 +0000107
Matthias Fuchs0b987252008-04-21 14:42:11 +0200108 /* wait some time before reading input */
109 udelay(1000);
110
111 /* get config bits */
112 value = in_be32((void*)GPIO0_IR) & 0x001c0000;
stroese04e93ec2005-04-13 10:06:07 +0000113 /*
114 * Restore GPIO settings
115 */
116 mtdcr(cntrl0, cntrl0Reg);
117
118 switch (value) {
Matthias Fuchs0b987252008-04-21 14:42:11 +0200119 case 0x001c0000:
120 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
stroese04e93ec2005-04-13 10:06:07 +0000121 return 2;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200122 case 0x000c0000:
123 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
stroese04e93ec2005-04-13 10:06:07 +0000124 return 3;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200125 case 0x00180000:
126 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
127 return 6;
128 case 0x00140000:
129 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
130 return 8;
stroese04e93ec2005-04-13 10:06:07 +0000131 default:
132 /* should not be reached! */
133 return 0;
134 }
135}
136
stroese1bc0f142004-12-16 18:20:14 +0000137int board_early_init_f (void)
138{
139 /*
Matthias Fuchs0b987252008-04-21 14:42:11 +0200140 * First pull fpga-prg pin low, to disable fpga logic
stroese1bc0f142004-12-16 18:20:14 +0000141 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200142 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200144 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
stroese1bc0f142004-12-16 18:20:14 +0000145
146 /*
147 * IRQ 0-15 405GP internally generated; active high; level sensitive
148 * IRQ 16 405GP internally generated; active low; level sensitive
149 * IRQ 17-24 RESERVED
150 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
151 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
152 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
153 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
154 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
155 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
156 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
157 */
158 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
159 mtdcr(uicer, 0x00000000); /* disable all ints */
160 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
161 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
162 mtdcr(uictr, 0x10000000); /* set int trigger levels */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200163 mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
stroese1bc0f142004-12-16 18:20:14 +0000164 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
165
166 /*
Matthias Fuchs0b987252008-04-21 14:42:11 +0200167 * EBC Configuration Register: set ready timeout to 512 ebc-clks
stroese1bc0f142004-12-16 18:20:14 +0000168 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200169 mtebc(epcr, 0xa8400000); /* ebc always driven */
170
171 /*
172 * New boards have a single 32MB flash connected to CS0
173 * instead of two 16MB flashes on CS0+1.
174 */
175 if (board_revision() >= 8) {
176 /* disable CS1 */
177 mtebc(pb1ap, 0);
178 mtebc(pb1cr, 0);
179
180 /* resize CS0 to 32MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
182 mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200183 }
stroese1bc0f142004-12-16 18:20:14 +0000184
185 return 0;
186}
187
Matthias Fuchs0b987252008-04-21 14:42:11 +0200188int board_early_init_r(void)
stroese1bc0f142004-12-16 18:20:14 +0000189{
Matthias Fuchs0b987252008-04-21 14:42:11 +0200190 if (gd->board_type >= 8)
191 flash_banks = 1;
192
193 return 0;
stroese1bc0f142004-12-16 18:20:14 +0000194}
195
Matthias Fuchs0b987252008-04-21 14:42:11 +0200196#define FUJI_BASE 0xf0100200
197#define LCDBL_PWM 0xa0
198#define LCDBL_PWMMIN 0xa4
199#define LCDBL_PWMMAX 0xa8
stroese1bc0f142004-12-16 18:20:14 +0000200
Matthias Fuchs0b987252008-04-21 14:42:11 +0200201int misc_init_r(void)
stroese1bc0f142004-12-16 18:20:14 +0000202{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
204 u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200205 u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
206 u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
stroese1bc0f142004-12-16 18:20:14 +0000207 unsigned char *dst;
208 ulong len = sizeof(fpgadata);
209 int status;
210 int index;
211 int i;
212 unsigned long cntrl0Reg;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200213 char *str;
214 uchar *logo_addr;
215 ulong logo_size;
216 ushort minb, maxb;
217 int result;
stroese1bc0f142004-12-16 18:20:14 +0000218
219 /*
220 * Setup GPIO pins (CS6+CS7 as GPIO)
221 */
222 cntrl0Reg = mfdcr(cntrl0);
223 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
226 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
Matthias Fuchs0b987252008-04-21 14:42:11 +0200227 printf("GUNZIP ERROR - must RESET board to recover\n");
228 do_reset(NULL, 0, 0, NULL);
stroese1bc0f142004-12-16 18:20:14 +0000229 }
230
231 status = fpga_boot(dst, len);
232 if (status != 0) {
233 printf("\nFPGA: Booting failed ");
234 switch (status) {
235 case ERROR_FPGA_PRG_INIT_LOW:
Matthias Fuchs0b987252008-04-21 14:42:11 +0200236 printf("(Timeout: "
237 "INIT not low after asserting PROGRAM*)\n ");
stroese1bc0f142004-12-16 18:20:14 +0000238 break;
239 case ERROR_FPGA_PRG_INIT_HIGH:
Matthias Fuchs0b987252008-04-21 14:42:11 +0200240 printf("(Timeout: "
241 "INIT not high after deasserting PROGRAM*)\n ");
stroese1bc0f142004-12-16 18:20:14 +0000242 break;
243 case ERROR_FPGA_PRG_DONE:
Matthias Fuchs0b987252008-04-21 14:42:11 +0200244 printf("(Timeout: "
245 "DONE not high after programming FPGA)\n ");
stroese1bc0f142004-12-16 18:20:14 +0000246 break;
247 }
248
249 /* display infos on fpgaimage */
250 index = 15;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200251 for (i = 0; i < 4; i++) {
stroese1bc0f142004-12-16 18:20:14 +0000252 len = dst[index];
253 printf("FPGA: %s\n", &(dst[index+1]));
Matthias Fuchs0b987252008-04-21 14:42:11 +0200254 index += len + 3;
stroese1bc0f142004-12-16 18:20:14 +0000255 }
Matthias Fuchs0b987252008-04-21 14:42:11 +0200256 putc('\n');
stroese1bc0f142004-12-16 18:20:14 +0000257 /* delayed reboot */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200258 for (i = 20; i > 0; i--) {
stroese1bc0f142004-12-16 18:20:14 +0000259 printf("Rebooting in %2d seconds \r",i);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200260 for (index = 0; index < 1000; index++)
stroese1bc0f142004-12-16 18:20:14 +0000261 udelay(1000);
262 }
Matthias Fuchs0b987252008-04-21 14:42:11 +0200263 putc('\n');
stroese1bc0f142004-12-16 18:20:14 +0000264 do_reset(NULL, 0, 0, NULL);
265 }
266
267 /* restore gpio/cs settings */
268 mtdcr(cntrl0, cntrl0Reg);
269
270 puts("FPGA: ");
271
272 /* display infos on fpgaimage */
273 index = 15;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200274 for (i = 0; i < 4; i++) {
stroese1bc0f142004-12-16 18:20:14 +0000275 len = dst[index];
Matthias Fuchs0b987252008-04-21 14:42:11 +0200276 printf("%s ", &(dst[index + 1]));
277 index += len + 3;
stroese1bc0f142004-12-16 18:20:14 +0000278 }
Matthias Fuchs0b987252008-04-21 14:42:11 +0200279 putc('\n');
stroese1bc0f142004-12-16 18:20:14 +0000280
281 free(dst);
282
283 /*
284 * Reset FPGA via FPGA_DATA pin
285 */
286 SET_FPGA(FPGA_PRG | FPGA_CLK);
287 udelay(1000); /* wait 1ms */
288 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
289 udelay(1000); /* wait 1ms */
290
291 /*
stroese04e93ec2005-04-13 10:06:07 +0000292 * Write board revision in FPGA
293 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200294 out_be16(fpga_ctrl2,
295 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
stroese04e93ec2005-04-13 10:06:07 +0000296
297 /*
stroese1bc0f142004-12-16 18:20:14 +0000298 * Enable power on PS/2 interface (with reset)
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300 out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
stroese1bc0f142004-12-16 18:20:14 +0000301 for (i=0;i<100;i++)
302 udelay(1000);
303 udelay(1000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304 out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
stroese1bc0f142004-12-16 18:20:14 +0000305
306 /*
307 * Enable interrupts in exar duart mcr[3]
308 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200309 out_8(duart0_mcr, 0x08);
310 out_8(duart1_mcr, 0x08);
stroese1bc0f142004-12-16 18:20:14 +0000311
312 /*
313 * Init lcd interface and display logo
314 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200315 str = getenv("splashimage");
316 if (str) {
317 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
Matthias Fuchs0b987252008-04-21 14:42:11 +0200319 } else {
320 logo_addr = logo_bmp;
321 logo_size = sizeof(logo_bmp);
322 }
323
324 if (gd->board_type >= 6) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
326 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
Matthias Fuchs0b987252008-04-21 14:42:11 +0200327 regs_13505_640_480_16bpp,
328 sizeof(regs_13505_640_480_16bpp) /
329 sizeof(regs_13505_640_480_16bpp[0]),
330 logo_addr, logo_size);
331 if (result && str) {
332 /* retry with internal image */
333 logo_addr = logo_bmp;
334 logo_size = sizeof(logo_bmp);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
336 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
Matthias Fuchs0b987252008-04-21 14:42:11 +0200337 regs_13505_640_480_16bpp,
338 sizeof(regs_13505_640_480_16bpp) /
339 sizeof(regs_13505_640_480_16bpp[0]),
340 logo_addr, logo_size);
341 }
342 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
344 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
Matthias Fuchs0b987252008-04-21 14:42:11 +0200345 regs_13806_640_480_16bpp,
346 sizeof(regs_13806_640_480_16bpp) /
347 sizeof(regs_13806_640_480_16bpp[0]),
348 logo_addr, logo_size);
349 if (result && str) {
350 /* retry with internal image */
351 logo_addr = logo_bmp;
352 logo_size = sizeof(logo_bmp);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
354 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
Matthias Fuchs0b987252008-04-21 14:42:11 +0200355 regs_13806_640_480_16bpp,
356 sizeof(regs_13806_640_480_16bpp) /
357 sizeof(regs_13806_640_480_16bpp[0]),
358 logo_addr, logo_size);
359 }
360 }
stroese1bc0f142004-12-16 18:20:14 +0000361
362 /*
stroese04e93ec2005-04-13 10:06:07 +0000363 * Reset microcontroller and setup backlight PWM controller
stroese1bc0f142004-12-16 18:20:14 +0000364 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200365 out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
stroese04e93ec2005-04-13 10:06:07 +0000366 for (i=0;i<10;i++)
367 udelay(1000);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200368 out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
369
370 minb = 0;
371 maxb = 0xff;
372 str = getenv("lcdbl");
373 if (str) {
374 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
375 if (str && (*str=',')) {
376 str++;
377 maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
378 } else
379 minb = 0;
380
381 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
382 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
383
384 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
385 }
386 out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
387
Matthias Fuchs8e048c42008-04-25 12:01:39 +0200388 /*
389 * fix environment for field updated units
390 */
391 if (getenv("altbootcmd") == NULL) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
393 setenv("usbargs", CONFIG_SYS_USB_ARGS);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200394 setenv("bootcmd", CONFIG_BOOTCOMMAND);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
396 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
397 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200398 saveenv();
399 }
stroese1bc0f142004-12-16 18:20:14 +0000400
401 return (0);
402}
403
stroese1bc0f142004-12-16 18:20:14 +0000404/*
405 * Check Board Identity:
406 */
stroese1bc0f142004-12-16 18:20:14 +0000407int checkboard (void)
408{
Matthias Fuchs0b987252008-04-21 14:42:11 +0200409 char str[64];
stroese1bc0f142004-12-16 18:20:14 +0000410 int i = getenv_r ("serial#", str, sizeof(str));
411
412 puts ("Board: ");
413
414 if (i == -1) {
415 puts ("### No HW ID - assuming APC405");
416 } else {
417 puts(str);
418 }
419
stroese04e93ec2005-04-13 10:06:07 +0000420 gd->board_type = board_revision();
Matthias Fuchs0b987252008-04-21 14:42:11 +0200421 printf(", Rev. 1.%ld\n", gd->board_type);
stroese1bc0f142004-12-16 18:20:14 +0000422
423 return 0;
424}
425
stroese1bc0f142004-12-16 18:20:14 +0000426#ifdef CONFIG_IDE_RESET
stroese1bc0f142004-12-16 18:20:14 +0000427void ide_set_reset(int on)
428{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
stroese1bc0f142004-12-16 18:20:14 +0000430
431 /*
432 * Assert or deassert CompactFlash Reset Pin
433 */
Matthias Fuchs0b987252008-04-21 14:42:11 +0200434 if (on) {
435 out_be16(fpga_mode,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
Matthias Fuchs0b987252008-04-21 14:42:11 +0200437 } else {
438 out_be16(fpga_mode,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
stroese1bc0f142004-12-16 18:20:14 +0000440 }
441}
stroese1bc0f142004-12-16 18:20:14 +0000442#endif /* CONFIG_IDE_RESET */
443
Matthias Fuchs0b987252008-04-21 14:42:11 +0200444void reset_phy(void)
445{
446 /*
447 * Disable sleep mode in LXT971
448 */
449 lxt971_no_sleep();
450}
451
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
Matthias Fuchs0b987252008-04-21 14:42:11 +0200453int usb_board_init(void)
454{
455 return 0;
456}
457
458int usb_board_stop(void)
459{
460 unsigned short tmp;
461 int i;
462
463 /*
464 * reset PCI bus
465 * This is required to make some very old Linux OHCI driver
466 * work after U-Boot has used the OHCI controller.
467 */
468 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
469 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
470
471 for (i = 0; i < 100; i++)
472 udelay(1000);
473
474 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
475 return 0;
476}
477
478int usb_board_init_fail(void)
479{
480 usb_board_stop();
481 return 0;
482}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */