Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Graeme Russ, graeme.russ@gmail.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
Graeme Russ | bf16500 | 2010-04-24 00:05:47 +1000 | [diff] [blame] | 24 | #include <asm/ibmpc.h> |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 25 | /* |
| 26 | * board/config.h - configuration options, board specific |
| 27 | */ |
| 28 | |
| 29 | #ifndef __CONFIG_H |
| 30 | #define __CONFIG_H |
| 31 | |
| 32 | /* |
| 33 | * Stuff still to be dealt with - |
| 34 | */ |
| 35 | #define CONFIG_RTC_MC146818 |
Graeme Russ | 2183100 | 2011-02-12 15:11:43 +1100 | [diff] [blame] | 36 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * High Level Configuration Options |
| 40 | * (easy to change) |
| 41 | */ |
| 42 | #define DEBUG_PARSER |
| 43 | |
| 44 | #define CONFIG_X86 1 /* Intel X86 CPU */ |
Graeme Russ | 6d83e3a | 2009-02-24 21:12:20 +1100 | [diff] [blame] | 45 | #define CONFIG_SYS_SC520 1 /* AMD SC520 */ |
| 46 | #define CONFIG_SYS_SC520_SSI |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 47 | #define CONFIG_SHOW_BOOT_PROGRESS 1 |
| 48 | #define CONFIG_LAST_STAGE_INIT 1 |
| 49 | |
| 50 | /* |
| 51 | * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the |
| 52 | * bottom (processor) board MUST be removed! |
| 53 | */ |
| 54 | #undef CONFIG_WATCHDOG |
Graeme Russ | 880c59e | 2010-04-24 00:05:58 +1000 | [diff] [blame] | 55 | #define CONFIG_HW_WATCHDOG |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 56 | |
| 57 | /*----------------------------------------------------------------------- |
Graeme Russ | bf16500 | 2010-04-24 00:05:47 +1000 | [diff] [blame] | 58 | * Serial Configuration |
| 59 | */ |
| 60 | #define CONFIG_SERIAL_MULTI |
Graeme Russ | bf16500 | 2010-04-24 00:05:47 +1000 | [diff] [blame] | 61 | #define CONFIG_CONS_INDEX 1 |
| 62 | #define CONFIG_SYS_NS16550 |
| 63 | #define CONFIG_SYS_NS16550_SERIAL |
| 64 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 65 | #define CONFIG_SYS_NS16550_CLK 1843200 |
| 66 | #define CONFIG_BAUDRATE 9600 |
| 67 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 68 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 69 | |
| 70 | #define CONFIG_SYS_NS16550_COM1 UART0_BASE |
| 71 | #define CONFIG_SYS_NS16550_COM2 UART1_BASE |
| 72 | #define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) |
| 73 | #define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) |
| 74 | #define CONFIG_SYS_NS16550_PORT_MAPPED |
| 75 | |
| 76 | /*----------------------------------------------------------------------- |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 77 | * Video Configuration |
| 78 | */ |
| 79 | #undef CONFIG_VIDEO /* No Video Hardware */ |
| 80 | #undef CONFIG_CFB_CONSOLE |
| 81 | |
| 82 | /* |
| 83 | * Size of malloc() pool |
| 84 | */ |
Graeme Russ | b4feeb4 | 2009-11-24 20:04:13 +1100 | [diff] [blame] | 85 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 86 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 87 | /*----------------------------------------------------------------------- |
| 88 | * Command line configuration. |
| 89 | */ |
| 90 | #include <config_cmd_default.h> |
| 91 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 92 | #define CONFIG_CMD_BDI /* bdinfo */ |
| 93 | #define CONFIG_CMD_BOOTD /* bootd */ |
| 94 | #define CONFIG_CMD_CONSOLE /* coninfo */ |
Graeme Russ | 2183100 | 2011-02-12 15:11:43 +1100 | [diff] [blame] | 95 | #define CONFIG_CMD_DATE |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 96 | #define CONFIG_CMD_ECHO /* echo arguments */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 97 | #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
| 98 | #define CONFIG_CMD_FPGA /* FPGA configuration Support */ |
| 99 | #define CONFIG_CMD_IMI /* iminfo */ |
| 100 | #define CONFIG_CMD_IMLS /* List all found images */ |
Wolfgang Denk | 74de7ae | 2009-04-01 23:34:12 +0200 | [diff] [blame] | 101 | #define CONFIG_CMD_IRQ /* IRQ Information */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 102 | #define CONFIG_CMD_ITEST /* Integer (and string) test */ |
| 103 | #define CONFIG_CMD_LOADB /* loadb */ |
| 104 | #define CONFIG_CMD_LOADS /* loads */ |
| 105 | #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ |
| 106 | #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ |
Graeme Russ | 8fd8056 | 2010-04-24 00:05:55 +1000 | [diff] [blame] | 107 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 108 | #undef CONFIG_CMD_NFS /* NFS support */ |
Graeme Russ | 5b34a29 | 2009-08-23 12:59:58 +1000 | [diff] [blame] | 109 | #define CONFIG_CMD_PCI /* PCI support */ |
Graeme Russ | 8fd8056 | 2010-04-24 00:05:55 +1000 | [diff] [blame] | 110 | #define CONFIG_CMD_PING /* ICMP echo support */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 111 | #define CONFIG_CMD_RUN /* run command in env variable */ |
Wolfgang Denk | 74de7ae | 2009-04-01 23:34:12 +0200 | [diff] [blame] | 112 | #define CONFIG_CMD_SAVEENV /* saveenv */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 113 | #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ |
Wolfgang Denk | 74de7ae | 2009-04-01 23:34:12 +0200 | [diff] [blame] | 114 | #define CONFIG_CMD_SOURCE /* "source" command Support */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 115 | #define CONFIG_CMD_XIMG /* Load part of Multi Image */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 116 | |
| 117 | #define CONFIG_BOOTDELAY 15 |
| 118 | #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" |
| 119 | /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ |
| 120 | |
| 121 | #if defined(CONFIG_CMD_KGDB) |
| 122 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| 123 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 124 | #endif |
| 125 | |
| 126 | /* |
| 127 | * Miscellaneous configurable options |
| 128 | */ |
| 129 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 130 | #define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ |
| 131 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 132 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 133 | sizeof(CONFIG_SYS_PROMPT) + \ |
| 134 | 16) /* Print Buffer Size */ |
| 135 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 136 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 137 | |
| 138 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 139 | #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ |
| 140 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 141 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 142 | |
Graeme Russ | 4f197c3 | 2010-04-24 00:05:52 +1000 | [diff] [blame] | 143 | #define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 144 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 145 | /*----------------------------------------------------------------------- |
| 146 | * SDRAM Configuration |
| 147 | */ |
| 148 | #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 |
| 149 | #define CONFIG_NR_DRAM_BANKS 4 |
| 150 | |
| 151 | /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ |
| 152 | #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY |
| 153 | #undef CONFIG_SYS_SDRAM_REFRESH_RATE |
| 154 | #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY |
| 155 | #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T |
| 156 | #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T |
| 157 | |
| 158 | /*----------------------------------------------------------------------- |
| 159 | * CPU Features |
| 160 | */ |
| 161 | #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ |
Graeme Russ | f2a5505 | 2010-04-24 00:05:57 +1000 | [diff] [blame] | 162 | #define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ |
Graeme Russ | 6d83e3a | 2009-02-24 21:12:20 +1100 | [diff] [blame] | 163 | #define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */ |
| 164 | #undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */ |
| 165 | #undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 166 | #define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those |
| 167 | * in the SC520 on the CDP */ |
Graeme Russ | abf0cd3 | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 168 | #define CONFIG_SYS_PCAT_INTERRUPTS |
| 169 | #define CONFIG_SYS_NUM_IRQS 16 |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 170 | |
| 171 | /*----------------------------------------------------------------------- |
| 172 | * Memory organization |
| 173 | */ |
| 174 | #define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */ |
| 175 | #define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */ |
| 176 | #define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */ |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 178 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 179 | #define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ |
| 180 | #define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ |
| 181 | #define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ |
| 182 | |
| 183 | /* timeout values are in ticks */ |
| 184 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| 185 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
| 186 | |
| 187 | /* allow to overwrite serial and ethaddr */ |
| 188 | #define CONFIG_ENV_OVERWRITE |
| 189 | |
| 190 | /*----------------------------------------------------------------------- |
| 191 | * FLASH configuration |
| 192 | */ |
| 193 | #define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ |
| 194 | #define CONFIG_FLASH_CFI_LEGACY |
| 195 | #define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ |
| 196 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
| 197 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
| 198 | CONFIG_SYS_FLASH_BASE_1, \ |
| 199 | CONFIG_SYS_FLASH_BASE_2} |
| 200 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Graeme Russ | 6fd445c | 2010-04-24 00:05:51 +1000 | [diff] [blame] | 201 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 202 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
| 203 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT |
| 204 | #define CONFIG_SYS_FLASH_LEGACY_512Kx8 |
| 205 | |
| 206 | /*----------------------------------------------------------------------- |
| 207 | * Environment configuration |
| 208 | */ |
| 209 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 210 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ |
Graeme Russ | f3a8d6b | 2009-08-23 12:59:48 +1000 | [diff] [blame] | 211 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
| 212 | #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 |
| 213 | /* Redundant Copy */ |
| 214 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 215 | CONFIG_ENV_SECT_SIZE) |
Graeme Russ | f3a8d6b | 2009-08-23 12:59:48 +1000 | [diff] [blame] | 216 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 217 | |
| 218 | |
| 219 | /*----------------------------------------------------------------------- |
| 220 | * PCI configuration |
| 221 | */ |
Graeme Russ | 5b34a29 | 2009-08-23 12:59:58 +1000 | [diff] [blame] | 222 | #define CONFIG_PCI /* include pci support */ |
| 223 | #define CONFIG_PCI_PNP /* pci plug-and-play */ |
| 224 | #define CONFIG_SYS_FIRST_PCI_IRQ 10 |
| 225 | #define CONFIG_SYS_SECOND_PCI_IRQ 9 |
| 226 | #define CONFIG_SYS_THIRD_PCI_IRQ 11 |
| 227 | #define CONFIG_SYS_FORTH_PCI_IRQ 15 |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 228 | |
Graeme Russ | 8fd8056 | 2010-04-24 00:05:55 +1000 | [diff] [blame] | 229 | /* |
| 230 | * Network device (TRL8100B) support |
| 231 | */ |
| 232 | #define CONFIG_NET_MULTI |
| 233 | #define CONFIG_RTL8139 |
| 234 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 235 | /*----------------------------------------------------------------------- |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 236 | * FPGA configuration |
| 237 | */ |
| 238 | #define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 |
| 239 | #define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000 |
| 240 | #define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000 |
| 241 | #define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16 |
| 242 | #define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16 |
| 243 | #define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16 |
| 244 | #define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16 |
| 245 | #define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ |
| 246 | #define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */ |
| 247 | #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ |
| 248 | #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ |
| 249 | |
Graeme Russ | 420c7c0 | 2011-02-12 15:11:45 +1100 | [diff] [blame] | 250 | /*----------------------------------------------------------------------- |
| 251 | * BOOTCS Control (for AM29LV040B-120JC) |
| 252 | * |
| 253 | * 000 0 00 0 000 11 0 011 }- 0x0033 |
| 254 | * \ / | \| | \ / \| | \ / |
| 255 | * | | | | | | | | |
| 256 | * | | | | | | | +---- 3 Wait States (First Access) |
| 257 | * | | | | | | +------- Reserved |
| 258 | * | | | | | +--------- 3 Wait States (Subsequent Access) |
| 259 | * | | | | +------------- Reserved |
| 260 | * | | | +---------------- Non-Paged Mode |
| 261 | * | | +------------------ 8 Bit Wide |
| 262 | * | +--------------------- GP Bus |
| 263 | * +------------------------ Reserved |
| 264 | */ |
| 265 | #define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 |
| 266 | |
| 267 | /*----------------------------------------------------------------------- |
| 268 | * ROMCS Control (for E28F128J3A-150 StrataFlash) |
| 269 | * |
| 270 | * 000 0 01 1 000 01 0 101 }- 0x0615 |
| 271 | * \ / | \| | \ / \| | \ / |
| 272 | * | | | | | | | | |
| 273 | * | | | | | | | +---- 5 Wait States (First Access) |
| 274 | * | | | | | | +------- Reserved |
| 275 | * | | | | | +--------- 1 Wait State (Subsequent Access) |
| 276 | * | | | | +------------- Reserved |
| 277 | * | | | +---------------- Paged Mode |
| 278 | * | | +------------------ 16 Bit Wide |
| 279 | * | +--------------------- GP Bus |
| 280 | * +------------------------ Reserved |
| 281 | */ |
| 282 | #define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 |
| 283 | #define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 |
| 284 | |
| 285 | /*----------------------------------------------------------------------- |
| 286 | * SC520 General Purpose Bus configuration |
| 287 | * |
| 288 | * Chip Select Offset 1 Clock Cycle |
| 289 | * Chip Select Pulse Width 8 Clock Cycles |
| 290 | * Chip Select Read Offset 2 Clock Cycles |
| 291 | * Chip Select Read Width 6 Clock Cycles |
| 292 | * Chip Select Write Offset 2 Clock Cycles |
| 293 | * Chip Select Write Width 6 Clock Cycles |
| 294 | * Chip Select Recovery Time 2 Clock Cycles |
| 295 | * |
| 296 | * Timing Diagram (from SC520 Register Set Manual - Order #22005B) |
| 297 | * |
| 298 | * |<-------------General Purpose Bus Cycle---------------->| |
| 299 | * | | |
| 300 | * ----------------------\__________________/------------------ |
| 301 | * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> | |
| 302 | * |
| 303 | * ------------------------\_______________/------------------- |
| 304 | * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->| |
| 305 | * |
| 306 | * --------------------------\_______________/----------------- |
| 307 | * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->| |
| 308 | * |
| 309 | * ________/-----------\_______________________________________ |
| 310 | * |<--->|<--------->| |
| 311 | * ^ ^ |
| 312 | * (GPALEOFF + 1) | |
| 313 | * | |
| 314 | * (GPALEW + 1) |
| 315 | */ |
| 316 | #define CONFIG_SYS_SC520_GPCSOFF 0x00 |
| 317 | #define CONFIG_SYS_SC520_GPCSPW 0x07 |
| 318 | #define CONFIG_SYS_SC520_GPRDOFF 0x01 |
| 319 | #define CONFIG_SYS_SC520_GPRDW 0x05 |
| 320 | #define CONFIG_SYS_SC520_GPWROFF 0x01 |
| 321 | #define CONFIG_SYS_SC520_GPWRW 0x05 |
| 322 | #define CONFIG_SYS_SC520_GPCSRT 0x01 |
| 323 | |
| 324 | /*----------------------------------------------------------------------- |
| 325 | * SC520 Programmable I/O configuration |
| 326 | * |
| 327 | * Pin Mode Dir. Description |
| 328 | * ---------------------------------------------------------------------- |
| 329 | * PIO0 PIO Output Unused |
| 330 | * PIO1 GPBHE# Output GP Bus Byte High Enable (active low) |
| 331 | * PIO2 PIO Output Auxiliary power output enable |
| 332 | * PIO3 GPAEN Output GP Bus Address Enable |
| 333 | * PIO4 PIO Output Top Board Enable (active low) |
| 334 | * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode) |
| 335 | * PIO6 PIO Input Data output of Power Supply ADC |
| 336 | * PIO7 PIO Output Clock input to Power Supply ADC |
| 337 | * PIO8 PIO Output Chip Select input of Power Supply ADC |
| 338 | * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low) |
| 339 | * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low) |
| 340 | * PIO11 PIO Input StrataFlash 1 Status |
| 341 | * PIO12 PIO Input StrataFlash 2 Status |
| 342 | * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low) |
| 343 | * PIO14 PIO Input Low Input Voltage Warning (active low) |
| 344 | * PIO15 PIO Output Watchdog (must toggle at least every 1.6s) |
| 345 | * PIO16 PIO Input Power Fail |
| 346 | * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low) |
| 347 | * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low) |
| 348 | * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low) |
| 349 | * PIO20 GPIRQ3 Input UART D IRQ |
| 350 | * PIO21 GPIRQ2 Input UART C IRQ |
| 351 | * PIO22 GPIRQ1 Input UART B IRQ |
| 352 | * PIO23 GPIRQ0 Input UART A IRQ |
| 353 | * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable |
| 354 | * PIO25 PIO Input Battery OK Indication |
| 355 | * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access |
| 356 | * PIO27 GPCS0# Output SRAM 1 Chip Select |
| 357 | * PIO28 PIO Input Top Board UART CTS |
| 358 | * PIO29 PIO Output FPGA Program Mode (active low) |
| 359 | * PIO30 PIO Input FPGA Initialised (active low) |
| 360 | * PIO31 PIO Input FPGA Done (active low) |
| 361 | */ |
| 362 | #define CONFIG_SYS_SC520_PIOPFS15_0 0x200a |
| 363 | #define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe |
| 364 | #define CONFIG_SYS_SC520_PIODIR15_0 0x87bf |
| 365 | #define CONFIG_SYS_SC520_PIODIR31_16 0x2900 |
| 366 | |
| 367 | /*----------------------------------------------------------------------- |
| 368 | * PIO Pin defines |
| 369 | */ |
| 370 | #define CONFIG_SYS_ENET_AUX_PWR 0x0004 |
| 371 | #define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010 |
| 372 | #define CONFIG_SYS_ENET_SF_WIDTH 0x0020 |
| 373 | #define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040 |
| 374 | #define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080 |
| 375 | #define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100 |
| 376 | #define CONFIG_SYS_ENET_SF1_MODE 0x0200 |
| 377 | #define CONFIG_SYS_ENET_SF2_MODE 0x0400 |
| 378 | #define CONFIG_SYS_ENET_SF1_STATUS 0x0800 |
| 379 | #define CONFIG_SYS_ENET_SF2_STATUS 0x1000 |
| 380 | #define CONFIG_SYS_ENET_PWR_STATUS 0x4000 |
| 381 | #define CONFIG_SYS_ENET_WATCHDOG 0x8000 |
| 382 | |
| 383 | #define CONFIG_SYS_ENET_PWR_FAIL 0x0001 |
| 384 | #define CONFIG_SYS_ENET_BAT_OK 0x0200 |
| 385 | #define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000 |
| 386 | #define CONFIG_SYS_ENET_FPGA_PROG 0x2000 |
| 387 | #define CONFIG_SYS_ENET_FPGA_INIT 0x4000 |
| 388 | #define CONFIG_SYS_ENET_FPGA_DONE 0x8000 |
| 389 | |
| 390 | /*----------------------------------------------------------------------- |
| 391 | * Chip Select Pin Function Select |
| 392 | * |
| 393 | * 1 1 1 1 1 0 0 0 }- 0xf8 |
| 394 | * | | | | | | | | |
| 395 | * | | | | | | | +--- Reserved |
| 396 | * | | | | | | +----- GPCS1_SEL = ROMCS1# |
| 397 | * | | | | | +------- GPCS2_SEL = ROMCS2# |
| 398 | * | | | | +--------- GPCS3_SEL = GPCS3 |
| 399 | * | | | +----------- GPCS4_SEL = GPCS4 |
| 400 | * | | +------------- GPCS5_SEL = GPCS5 |
| 401 | * | +--------------- GPCS6_SEL = GPCS6 |
| 402 | * +----------------- GPCS7_SEL = GPCS7 |
| 403 | */ |
| 404 | #define CONFIG_SYS_SC520_CSPFS 0xf8 |
| 405 | |
| 406 | /*----------------------------------------------------------------------- |
| 407 | * Clock Select (CLKTIMER[CLKTEST] pin) |
| 408 | * |
| 409 | * 0 111 00 1 0 }- 0x72 |
| 410 | * | \ / \| | | |
| 411 | * | | | | +--- Pin Disabled |
| 412 | * | | | +----- Pin is an output |
| 413 | * | | +------- Reserved |
| 414 | * | +----------- Disabled (pin stays Low) |
| 415 | * +-------------- Reserved |
| 416 | */ |
| 417 | #define CONFIG_SYS_SC520_CLKSEL 0x72 |
| 418 | |
| 419 | /*----------------------------------------------------------------------- |
| 420 | * Address Decode Control |
| 421 | * |
| 422 | * 0 00 0 0 0 0 0 }- 0x00 |
| 423 | * | \| | | | | | |
| 424 | * | | | | | | +--- Integrated UART 1 is enabled |
| 425 | * | | | | | +----- Integrated UART 2 is enabled |
| 426 | * | | | | +------- Integrated RTC is enabled |
| 427 | * | | | +--------- Reserved |
| 428 | * | | +----------- I/O Hole accesses are forwarded to the external GP bus |
| 429 | * | +------------- Reserved |
| 430 | * +---------------- Write-protect violations do not generate an IRQ |
| 431 | */ |
| 432 | #define CONFIG_SYS_SC520_ADDDECCTL 0x00 |
| 433 | |
| 434 | /*----------------------------------------------------------------------- |
| 435 | * UART Control |
| 436 | * |
| 437 | * 00000 1 1 1 }- 0x07 |
| 438 | * \___/ | | | |
| 439 | * | | | +--- Transmit TC interrupt enable |
| 440 | * | | +----- Receive TC interrupt enable |
| 441 | * | +------- 1.8432 MHz |
| 442 | * +----------- Reserved |
| 443 | */ |
| 444 | #define CONFIG_SYS_SC520_UART1CTL 0x07 |
| 445 | #define CONFIG_SYS_SC520_UART2CTL 0x07 |
| 446 | |
| 447 | /*----------------------------------------------------------------------- |
| 448 | * System Arbiter Control |
| 449 | * |
| 450 | * 00000 1 1 0 }- 0x06 |
| 451 | * \___/ | | | |
| 452 | * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt |
| 453 | * | | +----- The system arbiter operates in concurrent mode |
| 454 | * | +------- Park the PCI bus on the last master that acquired the bus |
| 455 | * +----------- Reserved |
| 456 | */ |
| 457 | #define CONFIG_SYS_SC520_SYSARBCTL 0x06 |
| 458 | |
| 459 | /*----------------------------------------------------------------------- |
| 460 | * System Arbiter Master Enable |
| 461 | * |
| 462 | * 00000000000 0 0 0 1 1 }- 0x06 |
| 463 | * \_________/ | | | | | |
| 464 | * | | | | | +--- PCI master REQ0 enabled (Ethernet 1) |
| 465 | * | | | | +----- PCI master REQ1 enabled (Ethernet 2) |
| 466 | * | | | +------- PCI master REQ2 disabled |
| 467 | * | | +--------- PCI master REQ3 disabled |
| 468 | * | +----------- PCI master REQ4 disabled |
| 469 | * +------------------ Reserved |
| 470 | */ |
| 471 | #define CONFIG_SYS_SC520_SYSARBMENB 0x0003 |
| 472 | |
| 473 | /*----------------------------------------------------------------------- |
| 474 | * System Arbiter Master Enable |
| 475 | * |
| 476 | * 0 0000 0 00 0000 1 000 }- 0x06 |
| 477 | * | \__/ | \| \__/ | \_/ |
| 478 | * | | | | | | +---- Reserved |
| 479 | * | | | | | +------- Enable CPU-to-PCI bus write posting |
| 480 | * | | | | +---------- Reserved |
| 481 | * | | | +-------------- PCI bus reads to SDRAM are not automatically |
| 482 | * | | | retried |
| 483 | * | | +----------------- Target read FIFOs are not snooped during write |
| 484 | * | | transactions |
| 485 | * | +-------------------- Reserved |
| 486 | * +------------------------ Deassert the PCI bus reset signal |
| 487 | */ |
| 488 | #define CONFIG_SYS_SC520_HBCTL 0x08 |
| 489 | |
| 490 | /*----------------------------------------------------------------------- |
| 491 | * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS |
| 492 | * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800 |
| 493 | * \ / | | | | \----+----/ \-----+------/ |
| 494 | * | | | | | | +---------- Start at 0x38000000 |
| 495 | * | | | | | +----------------------- 512kB Region Size |
| 496 | * | | | | | ((7 + 1) * 64kB) |
| 497 | * | | | | +------------------------------ 64kB Page Size |
| 498 | * | | | +-------------------------------- Writes Enabled (So it can be |
| 499 | * | | | reprogrammed!) |
| 500 | * | | +---------------------------------- Caching Disabled |
| 501 | * | +------------------------------------ Execution Enabled |
| 502 | * +--------------------------------------- BOOTCS |
| 503 | */ |
| 504 | #define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800 |
| 505 | |
| 506 | /*----------------------------------------------------------------------- |
| 507 | * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6 |
| 508 | * |
| 509 | * 001 110 0 000100000 0001000000000000 }- 0x38201000 |
| 510 | * \ / \ / | \---+---/ \------+-------/ |
| 511 | * | | | | +----------- Start at 0x00001000 |
| 512 | * | | | +------------------------ 33 Bytes (0x20 + 1) |
| 513 | * | | +------------------------------ Ignored |
| 514 | * | +--------------------------------- GPCS6 |
| 515 | * +------------------------------------- GP Bus I/O |
| 516 | */ |
| 517 | #define CONFIG_SYS_SC520_LLIO_PAR 0x38201000 |
| 518 | |
| 519 | /*----------------------------------------------------------------------- |
| 520 | * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5 |
| 521 | * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7 |
| 522 | * |
| 523 | * 010 101 0 0000000 100000000000000000 }- 0x54020000 |
| 524 | * 010 111 0 0000000 100000000000000001 }- 0x5c020001 |
| 525 | * \ / \ / | \--+--/ \-------+--------/ |
| 526 | * | | | | +------------ Start at 0x200000000 |
| 527 | * | | | | 0x200010000 |
| 528 | * | | | +------------------------- 4kB Region Size |
| 529 | * | | | ((0 + 1) * 4kB) |
| 530 | * | | +------------------------------ 4k Page Size |
| 531 | * | +--------------------------------- GPCS5 |
| 532 | * | GPCS7 |
| 533 | * +------------------------------------- GP Bus Memory |
| 534 | */ |
| 535 | #define CONFIG_SYS_SC520_CF1_PAR 0x54020000 |
| 536 | #define CONFIG_SYS_SC520_CF2_PAR 0x5c020001 |
| 537 | |
| 538 | /*----------------------------------------------------------------------- |
| 539 | * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0 |
| 540 | * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3 |
| 541 | * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4 |
| 542 | * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5 |
| 543 | * |
| 544 | * 001 000 0 000000111 0001001111111000 }- 0x200713f8 |
| 545 | * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8 |
| 546 | * 001 011 0 000000111 0001001011111000 }- 0x300711f8 |
| 547 | * 001 011 0 000000111 0001001011111000 }- 0x340710f8 |
| 548 | * \ / \ / | \---+---/ \------+-------/ |
| 549 | * | | | | +----------- Start at 0x013f8 |
| 550 | * | | | | 0x012f8 |
| 551 | * | | | | 0x011f8 |
| 552 | * | | | | 0x010f8 |
| 553 | * | | | +------------------------ 33 Bytes (32 + 1) |
| 554 | * | | +------------------------------ Ignored |
| 555 | * | +--------------------------------- GPCS6 |
| 556 | * +------------------------------------- GP Bus I/O |
| 557 | */ |
| 558 | #define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8 |
| 559 | #define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8 |
| 560 | #define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8 |
| 561 | #define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8 |
| 562 | |
| 563 | /*----------------------------------------------------------------------- |
| 564 | * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1 |
| 565 | * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2 |
| 566 | * |
| 567 | * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000 |
| 568 | * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100 |
| 569 | * \ / | | | | \----+----/ \-----+------/ |
| 570 | * | | | | | | +---------- Start at 0x10000000 |
| 571 | * | | | | | | 0x11000000 |
| 572 | * | | | | | +----------------------- 16MB Region Size |
| 573 | * | | | | | ((255 + 1) * 64kB) |
| 574 | * | | | | +------------------------------ 64kB Page Size |
| 575 | * | | | +-------------------------------- Writes Enabled |
| 576 | * | | +---------------------------------- Caching Disabled |
| 577 | * | +------------------------------------ Execution Enabled |
| 578 | * +--------------------------------------- ROMCS1 |
| 579 | * ROMCS2 |
| 580 | */ |
| 581 | #define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000 |
| 582 | #define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100 |
| 583 | |
| 584 | /*----------------------------------------------------------------------- |
| 585 | * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0 |
| 586 | * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3 |
| 587 | * |
| 588 | * 010 000 1 00000001111 01100100000000 }- 0x4203d900 |
| 589 | * 010 011 1 00000001111 01100100010000 }- 0x4e03d910 |
| 590 | * \ / \ / | \----+----/ \-----+------/ |
| 591 | * | | | | +---------- Start at 0x19000000 |
| 592 | * | | | | 0x19100000 |
| 593 | * | | | +----------------------- 1MB Region Size |
| 594 | * | | | ((15 + 1) * 64kB) |
| 595 | * | | +------------------------------ 64kB Page Size |
| 596 | * | +--------------------------------- GPCS0 |
| 597 | * | GPCS3 |
| 598 | * +------------------------------------- GP Bus Memory |
| 599 | */ |
| 600 | #define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900 |
| 601 | #define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910 |
| 602 | |
| 603 | /*----------------------------------------------------------------------- |
| 604 | * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4 |
| 605 | * |
| 606 | * 010 100 0 00000000 11000000100000000 }- 0x50018100 |
| 607 | * \ / \ / | \---+--/ \-------+-------/ |
| 608 | * | | | | +----------- Start at 0x18100000 |
| 609 | * | | | +------------------------ 4kB Region Size |
| 610 | * | | | ((0 + 1) * 4kB) |
| 611 | * | | +------------------------------ 4kB Page Size |
| 612 | * | +--------------------------------- GPCS4 |
| 613 | * +------------------------------------- GP Bus Memory |
| 614 | */ |
| 615 | #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100 |
| 616 | |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 617 | #ifndef __ASSEMBLER__ |
| 618 | extern unsigned long ip; |
| 619 | |
Graeme Russ | 141a62c | 2009-11-24 20:04:16 +1100 | [diff] [blame] | 620 | #define PRINTIP asm ("call 0\n" \ |
| 621 | "0:\n" \ |
Graeme Russ | c620c01 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 622 | "pop %%eax\n" \ |
| 623 | "movl %%eax, %0\n" \ |
| 624 | :"=r"(ip) \ |
| 625 | : /* No Input Registers */ \ |
| 626 | :"%eax"); \ |
| 627 | printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__); |
| 628 | |
| 629 | #endif |
| 630 | #endif /* __CONFIG_H */ |