blob: 6d503562171c377ea7ccea12c330a36466390c9a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardb312c592017-09-04 17:56:22 +02002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotardb312c592017-09-04 17:56:22 +02005 */
6
7#include <common.h>
8#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -07009#include <cpu_func.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020010#include <dm.h>
11#include <fdtdec.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070013#include <malloc.h>
Simon Glasscd93d622020-05-10 11:40:13 -060014#include <asm/bitops.h>
Simon Glass90526e92020-05-10 11:39:56 -060015#include <asm/cache.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060017#include <linux/delay.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090018#include <linux/libfdt.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020019#include <mmc.h>
20#include <reset.h>
21#include <asm/io.h>
22#include <asm/gpio.h>
23#include <linux/iopoll.h>
Christophe Kerello48ac7232019-07-30 19:16:45 +020024#include <watchdog.h>
Patrice Chotardb312c592017-09-04 17:56:22 +020025
26struct stm32_sdmmc2_plat {
27 struct mmc_config cfg;
28 struct mmc mmc;
29};
30
31struct stm32_sdmmc2_priv {
32 fdt_addr_t base;
33 struct clk clk;
34 struct reset_ctl reset_ctl;
35 struct gpio_desc cd_gpio;
36 u32 clk_reg_msk;
37 u32 pwr_reg_msk;
38};
39
40struct stm32_sdmmc2_ctx {
41 u32 cache_start;
42 u32 cache_end;
43 u32 data_length;
44 bool dpsm_abort;
45};
46
47/* SDMMC REGISTERS OFFSET */
48#define SDMMC_POWER 0x00 /* SDMMC power control */
49#define SDMMC_CLKCR 0x04 /* SDMMC clock control */
50#define SDMMC_ARG 0x08 /* SDMMC argument */
51#define SDMMC_CMD 0x0C /* SDMMC command */
52#define SDMMC_RESP1 0x14 /* SDMMC response 1 */
53#define SDMMC_RESP2 0x18 /* SDMMC response 2 */
54#define SDMMC_RESP3 0x1C /* SDMMC response 3 */
55#define SDMMC_RESP4 0x20 /* SDMMC response 4 */
56#define SDMMC_DTIMER 0x24 /* SDMMC data timer */
57#define SDMMC_DLEN 0x28 /* SDMMC data length */
58#define SDMMC_DCTRL 0x2C /* SDMMC data control */
59#define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
60#define SDMMC_STA 0x34 /* SDMMC status */
61#define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
62#define SDMMC_MASK 0x3C /* SDMMC mask */
63#define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
64#define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
65
66/* SDMMC_POWER register */
Patrick Delaunay7d118162018-06-27 10:15:33 +020067#define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
68#define SDMMC_POWER_PWRCTRL_OFF 0
69#define SDMMC_POWER_PWRCTRL_CYCLE 2
70#define SDMMC_POWER_PWRCTRL_ON 3
Patrice Chotardb312c592017-09-04 17:56:22 +020071#define SDMMC_POWER_VSWITCH BIT(2)
72#define SDMMC_POWER_VSWITCHEN BIT(3)
73#define SDMMC_POWER_DIRPOL BIT(4)
74
75/* SDMMC_CLKCR register */
76#define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
77#define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
78#define SDMMC_CLKCR_PWRSAV BIT(12)
79#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
80#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
81#define SDMMC_CLKCR_NEGEDGE BIT(16)
82#define SDMMC_CLKCR_HWFC_EN BIT(17)
83#define SDMMC_CLKCR_DDR BIT(18)
84#define SDMMC_CLKCR_BUSSPEED BIT(19)
Patrick Delaunay167f2c92018-02-07 17:19:59 +010085#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
86#define SDMMC_CLKCR_SELCLKRX_CK 0
87#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
88#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
Patrice Chotardb312c592017-09-04 17:56:22 +020089
90/* SDMMC_CMD register */
91#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
92#define SDMMC_CMD_CMDTRANS BIT(6)
93#define SDMMC_CMD_CMDSTOP BIT(7)
94#define SDMMC_CMD_WAITRESP GENMASK(9, 8)
95#define SDMMC_CMD_WAITRESP_0 BIT(8)
96#define SDMMC_CMD_WAITRESP_1 BIT(9)
97#define SDMMC_CMD_WAITINT BIT(10)
98#define SDMMC_CMD_WAITPEND BIT(11)
99#define SDMMC_CMD_CPSMEN BIT(12)
100#define SDMMC_CMD_DTHOLD BIT(13)
101#define SDMMC_CMD_BOOTMODE BIT(14)
102#define SDMMC_CMD_BOOTEN BIT(15)
103#define SDMMC_CMD_CMDSUSPEND BIT(16)
104
105/* SDMMC_DCTRL register */
106#define SDMMC_DCTRL_DTEN BIT(0)
107#define SDMMC_DCTRL_DTDIR BIT(1)
108#define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
109#define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
110#define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
111#define SDMMC_DCTRL_RWSTART BIT(8)
112#define SDMMC_DCTRL_RWSTOP BIT(9)
113#define SDMMC_DCTRL_RWMOD BIT(10)
114#define SDMMC_DCTRL_SDMMCEN BIT(11)
115#define SDMMC_DCTRL_BOOTACKEN BIT(12)
116#define SDMMC_DCTRL_FIFORST BIT(13)
117
118/* SDMMC_STA register */
119#define SDMMC_STA_CCRCFAIL BIT(0)
120#define SDMMC_STA_DCRCFAIL BIT(1)
121#define SDMMC_STA_CTIMEOUT BIT(2)
122#define SDMMC_STA_DTIMEOUT BIT(3)
123#define SDMMC_STA_TXUNDERR BIT(4)
124#define SDMMC_STA_RXOVERR BIT(5)
125#define SDMMC_STA_CMDREND BIT(6)
126#define SDMMC_STA_CMDSENT BIT(7)
127#define SDMMC_STA_DATAEND BIT(8)
128#define SDMMC_STA_DHOLD BIT(9)
129#define SDMMC_STA_DBCKEND BIT(10)
130#define SDMMC_STA_DABORT BIT(11)
131#define SDMMC_STA_DPSMACT BIT(12)
132#define SDMMC_STA_CPSMACT BIT(13)
133#define SDMMC_STA_TXFIFOHE BIT(14)
134#define SDMMC_STA_RXFIFOHF BIT(15)
135#define SDMMC_STA_TXFIFOF BIT(16)
136#define SDMMC_STA_RXFIFOF BIT(17)
137#define SDMMC_STA_TXFIFOE BIT(18)
138#define SDMMC_STA_RXFIFOE BIT(19)
139#define SDMMC_STA_BUSYD0 BIT(20)
140#define SDMMC_STA_BUSYD0END BIT(21)
141#define SDMMC_STA_SDMMCIT BIT(22)
142#define SDMMC_STA_ACKFAIL BIT(23)
143#define SDMMC_STA_ACKTIMEOUT BIT(24)
144#define SDMMC_STA_VSWEND BIT(25)
145#define SDMMC_STA_CKSTOP BIT(26)
146#define SDMMC_STA_IDMATE BIT(27)
147#define SDMMC_STA_IDMABTC BIT(28)
148
149/* SDMMC_ICR register */
150#define SDMMC_ICR_CCRCFAILC BIT(0)
151#define SDMMC_ICR_DCRCFAILC BIT(1)
152#define SDMMC_ICR_CTIMEOUTC BIT(2)
153#define SDMMC_ICR_DTIMEOUTC BIT(3)
154#define SDMMC_ICR_TXUNDERRC BIT(4)
155#define SDMMC_ICR_RXOVERRC BIT(5)
156#define SDMMC_ICR_CMDRENDC BIT(6)
157#define SDMMC_ICR_CMDSENTC BIT(7)
158#define SDMMC_ICR_DATAENDC BIT(8)
159#define SDMMC_ICR_DHOLDC BIT(9)
160#define SDMMC_ICR_DBCKENDC BIT(10)
161#define SDMMC_ICR_DABORTC BIT(11)
162#define SDMMC_ICR_BUSYD0ENDC BIT(21)
163#define SDMMC_ICR_SDMMCITC BIT(22)
164#define SDMMC_ICR_ACKFAILC BIT(23)
165#define SDMMC_ICR_ACKTIMEOUTC BIT(24)
166#define SDMMC_ICR_VSWENDC BIT(25)
167#define SDMMC_ICR_CKSTOPC BIT(26)
168#define SDMMC_ICR_IDMATEC BIT(27)
169#define SDMMC_ICR_IDMABTCC BIT(28)
170#define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
171
172/* SDMMC_MASK register */
173#define SDMMC_MASK_CCRCFAILIE BIT(0)
174#define SDMMC_MASK_DCRCFAILIE BIT(1)
175#define SDMMC_MASK_CTIMEOUTIE BIT(2)
176#define SDMMC_MASK_DTIMEOUTIE BIT(3)
177#define SDMMC_MASK_TXUNDERRIE BIT(4)
178#define SDMMC_MASK_RXOVERRIE BIT(5)
179#define SDMMC_MASK_CMDRENDIE BIT(6)
180#define SDMMC_MASK_CMDSENTIE BIT(7)
181#define SDMMC_MASK_DATAENDIE BIT(8)
182#define SDMMC_MASK_DHOLDIE BIT(9)
183#define SDMMC_MASK_DBCKENDIE BIT(10)
184#define SDMMC_MASK_DABORTIE BIT(11)
185#define SDMMC_MASK_TXFIFOHEIE BIT(14)
186#define SDMMC_MASK_RXFIFOHFIE BIT(15)
187#define SDMMC_MASK_RXFIFOFIE BIT(17)
188#define SDMMC_MASK_TXFIFOEIE BIT(18)
189#define SDMMC_MASK_BUSYD0ENDIE BIT(21)
190#define SDMMC_MASK_SDMMCITIE BIT(22)
191#define SDMMC_MASK_ACKFAILIE BIT(23)
192#define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
193#define SDMMC_MASK_VSWENDIE BIT(25)
194#define SDMMC_MASK_CKSTOPIE BIT(26)
195#define SDMMC_MASK_IDMABTCIE BIT(28)
196
197/* SDMMC_IDMACTRL register */
198#define SDMMC_IDMACTRL_IDMAEN BIT(0)
199
200#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
Patrice Chotard23441fb2019-07-22 11:41:10 +0200201#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
Patrice Chotardb312c592017-09-04 17:56:22 +0200202
Patrice Chotardb312c592017-09-04 17:56:22 +0200203static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
204 struct mmc_data *data,
205 struct stm32_sdmmc2_ctx *ctx)
206{
207 u32 data_ctrl, idmabase0;
208
209 /* Configure the SDMMC DPSM (Data Path State Machine) */
210 data_ctrl = (__ilog2(data->blocksize) <<
211 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
212 SDMMC_DCTRL_DBLOCKSIZE;
213
214 if (data->flags & MMC_DATA_READ) {
215 data_ctrl |= SDMMC_DCTRL_DTDIR;
216 idmabase0 = (u32)data->dest;
217 } else {
218 idmabase0 = (u32)data->src;
219 }
220
Patrice Chotardb312c592017-09-04 17:56:22 +0200221 /* Set the SDMMC DataLength value */
222 writel(ctx->data_length, priv->base + SDMMC_DLEN);
223
224 /* Write to SDMMC DCTRL */
225 writel(data_ctrl, priv->base + SDMMC_DCTRL);
226
227 /* Cache align */
228 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
229 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
230 ARCH_DMA_MINALIGN);
231
232 /*
233 * Flush data cache before DMA start (clean and invalidate)
234 * Clean also needed for read
235 * Avoid issue on buffer not cached-aligned
236 */
237 flush_dcache_range(ctx->cache_start, ctx->cache_end);
238
239 /* Enable internal DMA */
240 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
241 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
242}
243
244static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
Christophe Kerelloc406a472018-12-06 15:58:10 +0100245 struct mmc_cmd *cmd, u32 cmd_param,
246 struct stm32_sdmmc2_ctx *ctx)
Patrice Chotardb312c592017-09-04 17:56:22 +0200247{
Christophe Kerelloc406a472018-12-06 15:58:10 +0100248 u32 timeout = 0;
249
Patrice Chotard635159a2018-05-17 16:53:57 +0200250 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
251 writel(0, priv->base + SDMMC_CMD);
Patrice Chotardb312c592017-09-04 17:56:22 +0200252
253 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
254 if (cmd->resp_type & MMC_RSP_PRESENT) {
255 if (cmd->resp_type & MMC_RSP_136)
256 cmd_param |= SDMMC_CMD_WAITRESP;
257 else if (cmd->resp_type & MMC_RSP_CRC)
258 cmd_param |= SDMMC_CMD_WAITRESP_0;
259 else
260 cmd_param |= SDMMC_CMD_WAITRESP_1;
261 }
262
Christophe Kerelloc406a472018-12-06 15:58:10 +0100263 /*
264 * SDMMC_DTIME must be set in two case:
265 * - on data transfert.
266 * - on busy request.
267 * If not done or too short, the dtimeout flag occurs and DPSM stays
268 * enabled/busy and waits for abort (stop transmission cmd).
269 * Next data command is not possible whereas DPSM is activated.
270 */
271 if (ctx->data_length) {
272 timeout = SDMMC_CMD_TIMEOUT;
273 } else {
274 writel(0, priv->base + SDMMC_DCTRL);
275
276 if (cmd->resp_type & MMC_RSP_BUSY)
277 timeout = SDMMC_CMD_TIMEOUT;
278 }
279
280 /* Set the SDMMC Data TimeOut value */
281 writel(timeout, priv->base + SDMMC_DTIMER);
282
Patrice Chotardb312c592017-09-04 17:56:22 +0200283 /* Clear flags */
284 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
285
286 /* Set SDMMC argument value */
287 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
288
289 /* Set SDMMC command parameters */
290 writel(cmd_param, priv->base + SDMMC_CMD);
291}
292
293static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
294 struct mmc_cmd *cmd,
295 struct stm32_sdmmc2_ctx *ctx)
296{
297 u32 mask = SDMMC_STA_CTIMEOUT;
298 u32 status;
299 int ret;
300
301 if (cmd->resp_type & MMC_RSP_PRESENT) {
302 mask |= SDMMC_STA_CMDREND;
303 if (cmd->resp_type & MMC_RSP_CRC)
304 mask |= SDMMC_STA_CCRCFAIL;
305 } else {
306 mask |= SDMMC_STA_CMDSENT;
307 }
308
309 /* Polling status register */
310 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
Christophe Kerello6c36e972017-10-09 17:02:28 +0200311 10000);
Patrice Chotardb312c592017-09-04 17:56:22 +0200312
313 if (ret < 0) {
314 debug("%s: timeout reading SDMMC_STA register\n", __func__);
315 ctx->dpsm_abort = true;
316 return ret;
317 }
318
319 /* Check status */
320 if (status & SDMMC_STA_CTIMEOUT) {
321 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
322 __func__, status, cmd->cmdidx);
323 ctx->dpsm_abort = true;
324 return -ETIMEDOUT;
325 }
326
327 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
328 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
329 __func__, status, cmd->cmdidx);
330 ctx->dpsm_abort = true;
331 return -EILSEQ;
332 }
333
334 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
335 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
336 if (cmd->resp_type & MMC_RSP_136) {
337 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
338 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
339 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
340 }
Christophe Kerelloc406a472018-12-06 15:58:10 +0100341
342 /* Wait for BUSYD0END flag if busy status is detected */
343 if (cmd->resp_type & MMC_RSP_BUSY &&
344 status & SDMMC_STA_BUSYD0) {
345 mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
346
347 /* Polling status register */
348 ret = readl_poll_timeout(priv->base + SDMMC_STA,
349 status, status & mask,
350 SDMMC_BUSYD0END_TIMEOUT_US);
351
352 if (ret < 0) {
353 debug("%s: timeout reading SDMMC_STA\n",
354 __func__);
355 ctx->dpsm_abort = true;
356 return ret;
357 }
358
359 if (status & SDMMC_STA_DTIMEOUT) {
360 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
361 __func__, status);
362 ctx->dpsm_abort = true;
363 return -ETIMEDOUT;
364 }
365 }
Patrice Chotardb312c592017-09-04 17:56:22 +0200366 }
367
368 return 0;
369}
370
371static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
372 struct mmc_cmd *cmd,
373 struct mmc_data *data,
374 struct stm32_sdmmc2_ctx *ctx)
375{
376 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
377 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
378 u32 status;
379
380 if (data->flags & MMC_DATA_READ)
381 mask |= SDMMC_STA_RXOVERR;
382 else
383 mask |= SDMMC_STA_TXUNDERR;
384
385 status = readl(priv->base + SDMMC_STA);
386 while (!(status & mask))
387 status = readl(priv->base + SDMMC_STA);
388
389 /*
390 * Need invalidate the dcache again to avoid any
391 * cache-refill during the DMA operations (pre-fetching)
392 */
393 if (data->flags & MMC_DATA_READ)
394 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
395
396 if (status & SDMMC_STA_DCRCFAIL) {
397 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
398 __func__, status, cmd->cmdidx);
399 if (readl(priv->base + SDMMC_DCOUNT))
400 ctx->dpsm_abort = true;
401 return -EILSEQ;
402 }
403
404 if (status & SDMMC_STA_DTIMEOUT) {
405 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
406 __func__, status, cmd->cmdidx);
407 ctx->dpsm_abort = true;
408 return -ETIMEDOUT;
409 }
410
411 if (status & SDMMC_STA_TXUNDERR) {
412 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
413 __func__, status, cmd->cmdidx);
414 ctx->dpsm_abort = true;
415 return -EIO;
416 }
417
418 if (status & SDMMC_STA_RXOVERR) {
419 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
420 __func__, status, cmd->cmdidx);
421 ctx->dpsm_abort = true;
422 return -EIO;
423 }
424
425 if (status & SDMMC_STA_IDMATE) {
426 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
427 __func__, status, cmd->cmdidx);
428 ctx->dpsm_abort = true;
429 return -EIO;
430 }
431
432 return 0;
433}
434
435static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
436 struct mmc_data *data)
437{
438 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
439 struct stm32_sdmmc2_ctx ctx;
440 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
441 int ret, retry = 3;
442
Christophe Kerello48ac7232019-07-30 19:16:45 +0200443 WATCHDOG_RESET();
444
Patrice Chotardb312c592017-09-04 17:56:22 +0200445retry_cmd:
446 ctx.data_length = 0;
447 ctx.dpsm_abort = false;
448
449 if (data) {
450 ctx.data_length = data->blocks * data->blocksize;
451 stm32_sdmmc2_start_data(priv, data, &ctx);
452 }
453
Christophe Kerelloc406a472018-12-06 15:58:10 +0100454 stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
Patrice Chotardb312c592017-09-04 17:56:22 +0200455
456 debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
457 __func__, cmd->cmdidx,
458 data ? ctx.data_length : 0, (unsigned int)data);
459
460 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
461
462 if (data && !ret)
463 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
464
465 /* Clear flags */
466 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
467 if (data)
468 writel(0x0, priv->base + SDMMC_IDMACTRL);
469
470 /*
471 * To stop Data Path State Machine, a stop_transmission command
472 * shall be send on cmd or data errors.
473 */
474 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
475 struct mmc_cmd stop_cmd;
476
477 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
478 stop_cmd.cmdarg = 0;
479 stop_cmd.resp_type = MMC_RSP_R1b;
480
481 debug("%s: send STOP command to abort dpsm treatments\n",
482 __func__);
483
Christophe Kerelloc406a472018-12-06 15:58:10 +0100484 ctx.data_length = 0;
485
486 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
487 SDMMC_CMD_CMDSTOP, &ctx);
Patrice Chotardb312c592017-09-04 17:56:22 +0200488 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
489
490 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
491 }
492
493 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
494 printf("%s: cmd %d failed, retrying ...\n",
495 __func__, cmd->cmdidx);
496 retry--;
497 goto retry_cmd;
498 }
499
500 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
501
502 return ret;
503}
504
Patrick Delaunay7d118162018-06-27 10:15:33 +0200505/*
506 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
507 * This will reset the SDMMC to the reset state and the CPSM and DPSM
508 * to the Idle state. SDMMC is disabled, Signals Hiz.
509 */
510static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
Patrice Chotardb312c592017-09-04 17:56:22 +0200511{
512 /* Reset */
513 reset_assert(&priv->reset_ctl);
514 udelay(2);
515 reset_deassert(&priv->reset_ctl);
516
Patrick Delaunay7d118162018-06-27 10:15:33 +0200517 /* init the needed SDMMC register after reset */
518 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
519}
Patrice Chotardb312c592017-09-04 17:56:22 +0200520
Patrick Delaunay7d118162018-06-27 10:15:33 +0200521/*
522 * Set the SDMMC in power-cycle state.
523 * This will make that the SDMMC_D[7:0],
524 * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
525 * supplied through the signal lines.
526 */
527static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
528{
529 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
530 SDMMC_POWER_PWRCTRL_CYCLE)
531 return;
532
533 stm32_sdmmc2_reset(priv);
Patrick Delaunay7d118162018-06-27 10:15:33 +0200534}
535
536/*
537 * set the SDMMC state Power-on: the card is clocked
538 * manage the SDMMC state control:
539 * Reset => Power-Cycle => Power-Off => Power
540 * PWRCTRL=10 PWCTRL=00 PWCTRL=11
541 */
542static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
543{
544 u32 pwrctrl =
545 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
546
547 if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
548 return;
549
550 /* warning: same PWRCTRL value after reset and for power-off state
551 * it is the reset state here = the only managed by the driver
552 */
553 if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
554 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
555 priv->base + SDMMC_POWER);
556 }
Patrice Chotardb312c592017-09-04 17:56:22 +0200557
558 /*
Patrick Delaunay7d118162018-06-27 10:15:33 +0200559 * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
560 * switch to Power-Off state: SDMCC disable, signals drive 1
Patrice Chotardb312c592017-09-04 17:56:22 +0200561 */
Patrick Delaunay7d118162018-06-27 10:15:33 +0200562 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
563 priv->base + SDMMC_POWER);
564
565 /* After the 1ms delay set the SDMMC to power-on */
566 mdelay(1);
567 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
568 priv->base + SDMMC_POWER);
569
570 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
Patrice Chotardb312c592017-09-04 17:56:22 +0200571}
572
573#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
574static int stm32_sdmmc2_set_ios(struct udevice *dev)
575{
576 struct mmc *mmc = mmc_get_mmc_dev(dev);
577 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
Patrice Chotardb312c592017-09-04 17:56:22 +0200578 u32 desired = mmc->clock;
579 u32 sys_clock = clk_get_rate(&priv->clk);
580 u32 clk = 0;
581
582 debug("%s: bus_with = %d, clock = %d\n", __func__,
583 mmc->bus_width, mmc->clock);
584
Patrick Delaunay7d118162018-06-27 10:15:33 +0200585 if (mmc->clk_disable)
586 stm32_sdmmc2_pwrcycle(priv);
587 else
Patrice Chotardb312c592017-09-04 17:56:22 +0200588 stm32_sdmmc2_pwron(priv);
589
590 /*
591 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
592 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
593 * SDMMCCLK rising edge
594 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
595 * SDMMCCLK falling edge
596 */
597 if (desired && ((sys_clock > desired) ||
598 IS_RISING_EDGE(priv->clk_reg_msk))) {
599 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
600 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
601 clk = SDMMC_CLKCR_CLKDIV_MAX;
602 }
603
604 if (mmc->bus_width == 4)
605 clk |= SDMMC_CLKCR_WIDBUS_4;
606 if (mmc->bus_width == 8)
607 clk |= SDMMC_CLKCR_WIDBUS_8;
608
Patrick Delaunaya72dd8e2018-02-07 17:19:58 +0100609 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
610 priv->base + SDMMC_CLKCR);
Patrice Chotardb312c592017-09-04 17:56:22 +0200611
612 return 0;
613}
614
615static int stm32_sdmmc2_getcd(struct udevice *dev)
616{
617 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
618
619 debug("stm32_sdmmc2_getcd called\n");
620
621 if (dm_gpio_is_valid(&priv->cd_gpio))
622 return dm_gpio_get_value(&priv->cd_gpio);
623
624 return 1;
625}
626
Yann Gautiera8ef8b22019-09-19 17:56:13 +0200627static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
628{
629 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
630
631 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
632 priv->base + SDMMC_POWER);
633
634 return 0;
635}
636
Patrice Chotardb312c592017-09-04 17:56:22 +0200637static const struct dm_mmc_ops stm32_sdmmc2_ops = {
638 .send_cmd = stm32_sdmmc2_send_cmd,
639 .set_ios = stm32_sdmmc2_set_ios,
640 .get_cd = stm32_sdmmc2_getcd,
Yann Gautiera8ef8b22019-09-19 17:56:13 +0200641 .host_power_cycle = stm32_sdmmc2_host_power_cycle,
Patrice Chotardb312c592017-09-04 17:56:22 +0200642};
643
644static int stm32_sdmmc2_probe(struct udevice *dev)
645{
646 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
647 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
648 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
649 struct mmc_config *cfg = &plat->cfg;
650 int ret;
651
652 priv->base = dev_read_addr(dev);
653 if (priv->base == FDT_ADDR_T_NONE)
654 return -EINVAL;
655
Patrick Delaunayb6115352018-11-16 10:25:54 +0100656 if (dev_read_bool(dev, "st,neg-edge"))
Patrice Chotardb312c592017-09-04 17:56:22 +0200657 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
Patrick Delaunayb6115352018-11-16 10:25:54 +0100658 if (dev_read_bool(dev, "st,sig-dir"))
Patrice Chotardb312c592017-09-04 17:56:22 +0200659 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
Patrick Delaunayb6115352018-11-16 10:25:54 +0100660 if (dev_read_bool(dev, "st,use-ckin"))
Patrick Delaunay167f2c92018-02-07 17:19:59 +0100661 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
Patrice Chotardb312c592017-09-04 17:56:22 +0200662
663 ret = clk_get_by_index(dev, 0, &priv->clk);
664 if (ret)
665 return ret;
666
667 ret = clk_enable(&priv->clk);
668 if (ret)
669 goto clk_free;
670
671 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
672 if (ret)
673 goto clk_disable;
674
675 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
676 GPIOD_IS_IN);
677
678 cfg->f_min = 400000;
679 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
680 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
681 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Patrick Delaunayd7244e42020-04-30 09:52:13 +0200682 cfg->name = "STM32 SD/MMC";
Patrice Chotardb312c592017-09-04 17:56:22 +0200683
684 cfg->host_caps = 0;
685 if (cfg->f_max > 25000000)
686 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
687
688 switch (dev_read_u32_default(dev, "bus-width", 1)) {
689 case 8:
690 cfg->host_caps |= MMC_MODE_8BIT;
Patrick Delaunay0e9fb252019-06-21 15:26:42 +0200691 /* fall through */
Patrice Chotardb312c592017-09-04 17:56:22 +0200692 case 4:
693 cfg->host_caps |= MMC_MODE_4BIT;
694 break;
695 case 1:
696 break;
697 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900698 pr_err("invalid \"bus-width\" property, force to 1\n");
Patrice Chotardb312c592017-09-04 17:56:22 +0200699 }
700
701 upriv->mmc = &plat->mmc;
702
Patrick Delaunay7d118162018-06-27 10:15:33 +0200703 /* SDMMC init */
704 stm32_sdmmc2_reset(priv);
Patrice Chotardb312c592017-09-04 17:56:22 +0200705 return 0;
706
707clk_disable:
708 clk_disable(&priv->clk);
709clk_free:
710 clk_free(&priv->clk);
711
712 return ret;
713}
714
Patrick Delaunay0e9fb252019-06-21 15:26:42 +0200715static int stm32_sdmmc_bind(struct udevice *dev)
Patrice Chotardb312c592017-09-04 17:56:22 +0200716{
717 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
718
719 return mmc_bind(dev, &plat->mmc, &plat->cfg);
720}
721
722static const struct udevice_id stm32_sdmmc2_ids[] = {
723 { .compatible = "st,stm32-sdmmc2" },
724 { }
725};
726
727U_BOOT_DRIVER(stm32_sdmmc2) = {
728 .name = "stm32_sdmmc2",
729 .id = UCLASS_MMC,
730 .of_match = stm32_sdmmc2_ids,
731 .ops = &stm32_sdmmc2_ops,
732 .probe = stm32_sdmmc2_probe,
733 .bind = stm32_sdmmc_bind,
734 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
735 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
736};