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Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Haiying Wang3d98b852007-01-22 12:37:30 -06002 * Copyright 2006, 2007 Freescale Semiconductor.
Jon Loeligerdebb7352006-04-26 17:58:56 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthout63cec582007-08-02 14:09:49 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerdebb7352006-04-26 17:58:56 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <pci.h>
25#include <asm/processor.h>
26#include <asm/immap_86xx.h>
Ed Swarthout63cec582007-08-02 14:09:49 -050027#include <asm/immap_fsl_pci.h>
Kumar Gala6a8e5692008-08-26 15:01:35 -050028#include <asm/fsl_ddr_sdram.h>
Haiying Wang3d98b852007-01-22 12:37:30 -060029#include <asm/io.h>
Jon Loeligerea9f7392007-11-28 14:47:18 -060030#include <libfdt.h>
31#include <fdt_support.h>
Ben Warren0b252f52008-08-31 21:41:08 -070032#include <netdev.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050033
Jon Loeliger4ce91772007-08-15 12:20:40 -050034#include "../common/pixis.h"
Jon Loeliger4d3d7292006-05-31 11:24:28 -050035
Becky Bruce4c77de32008-10-31 17:13:32 -050036phys_size_t fixed_sdram(void);
Jon Loeligerdebb7352006-04-26 17:58:56 -050037
Jon Loeliger80e955c2006-08-22 12:25:27 -050038int board_early_init_f(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050039{
Jon Loeligercb5965f2006-05-31 12:44:44 -050040 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -050041}
42
Jon Loeliger80e955c2006-08-22 12:25:27 -050043int checkboard(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050044{
Wolfgang Denk9b55a252008-07-11 01:16:00 +020045 printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Gala7de8c212008-06-19 01:45:27 -050047 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
Becky Bruce2331e182009-02-12 10:43:32 -060049#ifdef CONFIG_PHYS_64BIT
50 printf (" 36-bit physical address map\n");
51#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -050052 return 0;
53}
54
55
Becky Bruce9973e3c2008-06-09 16:03:40 -050056phys_size_t
Jon Loeligerdebb7352006-04-26 17:58:56 -050057initdram(int board_type)
58{
Becky Bruce4c77de32008-10-31 17:13:32 -050059 phys_size_t dram_size = 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -050060
61#if defined(CONFIG_SPD_EEPROM)
Kumar Gala6a8e5692008-08-26 15:01:35 -050062 dram_size = fsl_ddr_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050063#else
Jon Loeliger80e955c2006-08-22 12:25:27 -050064 dram_size = fixed_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050065#endif
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeligerdebb7352006-04-26 17:58:56 -050068 puts(" DDR: ");
69 return dram_size;
70#endif
Jon Loeligercb5965f2006-05-31 12:44:44 -050071
Jon Loeligerdebb7352006-04-26 17:58:56 -050072 puts(" DDR: ");
73 return dram_size;
74}
75
76
Jon Loeligerdebb7352006-04-26 17:58:56 -050077#if !defined(CONFIG_SPD_EEPROM)
Jon Loeliger5c9efb32006-04-27 10:15:16 -050078/*
79 * Fixed sdram init -- doesn't use serial presence detect.
80 */
Becky Bruce4c77de32008-10-31 17:13:32 -050081phys_size_t
Jon Loeliger80e955c2006-08-22 12:25:27 -050082fixed_sdram(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050083{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#if !defined(CONFIG_SYS_RAMBOOT)
85 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Jon Loeliger80e955c2006-08-22 12:25:27 -050086 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
Jon Loeligerdebb7352006-04-26 17:58:56 -050087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
89 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
90 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
91 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
92 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
93 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
94 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
95 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
99 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
100 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500101
102#if defined (CONFIG_DDR_ECC)
103 ddr->err_disable = 0x0000008D;
104 ddr->err_sbe = 0x00ff0000;
105#endif
106 asm("sync;isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -0500107
Jon Loeligerdebb7352006-04-26 17:58:56 -0500108 udelay(500);
109
110#if defined (CONFIG_DDR_ECC)
111 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500113#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
115 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500116#endif
117 asm("sync; isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -0500118
Jon Loeligerdebb7352006-04-26 17:58:56 -0500119 udelay(500);
120#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500122}
123#endif /* !defined(CONFIG_SPD_EEPROM) */
124
125
126#if defined(CONFIG_PCI)
Becky Bruce98693b82008-10-31 17:14:00 -0500127static struct pci_controller pci1_hose;
Jon Loeliger80e955c2006-08-22 12:25:27 -0500128#endif /* CONFIG_PCI */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500129
Ed Swarthout63cec582007-08-02 14:09:49 -0500130#ifdef CONFIG_PCI2
131static struct pci_controller pci2_hose;
132#endif /* CONFIG_PCI2 */
133
134int first_free_busno = 0;
135
Kumar Galac2083e02008-10-22 14:38:55 -0500136extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
137extern void fsl_pci_init(struct pci_controller *hose);
Ed Swarthout63cec582007-08-02 14:09:49 -0500138
Jon Loeliger80e955c2006-08-22 12:25:27 -0500139void pci_init_board(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500140{
Ed Swarthout63cec582007-08-02 14:09:49 -0500141#ifdef CONFIG_PCI1
142{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
Ed Swarthout63cec582007-08-02 14:09:49 -0500144 struct pci_controller *hose = &pci1_hose;
Kumar Galac2083e02008-10-22 14:38:55 -0500145 struct pci_region *r = hose->regions;
Becky Bruceaf5d1002008-10-31 17:14:14 -0500146 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
147 volatile ccsr_gur_t *gur = &immap->im_gur;
148 uint devdisr = gur->devdisr;
149 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
150 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
Kumar Galac2083e02008-10-22 14:38:55 -0500151
Ed Swarthout63cec582007-08-02 14:09:49 -0500152#ifdef DEBUG
Jon Loeligera551cee2008-02-20 14:22:26 -0600153 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
154 >> MPC8641_PORBMSR_HA_SHIFT;
Ed Swarthout63cec582007-08-02 14:09:49 -0500155 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
156#endif
157 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
158 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
159 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
160 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
161 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
162 if (pci->pme_msg_det) {
163 pci->pme_msg_det = 0xffffffff;
164 debug(" with errors. Clearing. Now 0x%08x",
165 pci->pme_msg_det);
166 }
167 debug("\n");
168
Ed Swarthout63cec582007-08-02 14:09:49 -0500169 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500170 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600171 CONFIG_SYS_PCI1_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 CONFIG_SYS_PCI1_MEM_PHYS,
173 CONFIG_SYS_PCI1_MEM_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500174 PCI_REGION_MEM);
175
176 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500177 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600178 CONFIG_SYS_PCI1_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 CONFIG_SYS_PCI1_IO_PHYS,
180 CONFIG_SYS_PCI1_IO_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500181 PCI_REGION_IO);
182
Becky Bruce2ecca342009-02-03 18:10:49 -0600183 /* inbound */
184 r += fsl_pci_setup_inbound_windows(r);
185
Kumar Galac2083e02008-10-22 14:38:55 -0500186 hose->region_count = r - hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500187
188 hose->first_busno=first_free_busno;
189 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
190
191 fsl_pci_init(hose);
192
193 first_free_busno=hose->last_busno+1;
194 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
195 hose->first_busno,hose->last_busno);
196
197 /*
198 * Activate ULI1575 legacy chip by performing a fake
199 * memory access. Needed to make ULI RTC work.
200 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600201 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
Ed Swarthout63cec582007-08-02 14:09:49 -0500203
204 } else {
205 puts("PCI-EXPRESS 1: Disabled\n");
206 }
207}
208#else
209 puts("PCI-EXPRESS1: Disabled\n");
210#endif /* CONFIG_PCI1 */
211
212#ifdef CONFIG_PCI2
213{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
Ed Swarthout63cec582007-08-02 14:09:49 -0500215 struct pci_controller *hose = &pci2_hose;
Kumar Galac2083e02008-10-22 14:38:55 -0500216 struct pci_region *r = hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500217
Ed Swarthout63cec582007-08-02 14:09:49 -0500218 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500219 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600220 CONFIG_SYS_PCI2_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 CONFIG_SYS_PCI2_MEM_PHYS,
222 CONFIG_SYS_PCI2_MEM_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500223 PCI_REGION_MEM);
224
225 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500226 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600227 CONFIG_SYS_PCI2_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 CONFIG_SYS_PCI2_IO_PHYS,
229 CONFIG_SYS_PCI2_IO_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500230 PCI_REGION_IO);
231
Becky Bruce2ecca342009-02-03 18:10:49 -0600232 /* inbound */
233 r += fsl_pci_setup_inbound_windows(r);
234
Kumar Galac2083e02008-10-22 14:38:55 -0500235 hose->region_count = r - hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500236
237 hose->first_busno=first_free_busno;
238 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
239
240 fsl_pci_init(hose);
241
242 first_free_busno=hose->last_busno+1;
243 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
244 hose->first_busno,hose->last_busno);
245}
246#else
247 puts("PCI-EXPRESS 2: Disabled\n");
248#endif /* CONFIG_PCI2 */
249
Jon Loeligerdebb7352006-04-26 17:58:56 -0500250}
251
Jon Loeliger13f54332008-02-18 14:01:56 -0600252
Jon Loeligerea9f7392007-11-28 14:47:18 -0600253#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Galac2083e02008-10-22 14:38:55 -0500254extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100255 struct pci_controller *hose);
Jon Loeliger13f54332008-02-18 14:01:56 -0600256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257void
258ft_board_setup(void *blob, bd_t *bd)
259{
Becky Bruced52082b2008-11-07 13:46:19 -0600260 int off;
261 u64 *tmp;
262 u32 *addrcells;
263
Jon Loeliger13f54332008-02-18 14:01:56 -0600264 ft_cpu_setup(blob, bd);
Jon Loeligerea9f7392007-11-28 14:47:18 -0600265
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500266#ifdef CONFIG_PCI1
Kumar Galac2083e02008-10-22 14:38:55 -0500267 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500268#endif
269#ifdef CONFIG_PCI2
Kumar Galac2083e02008-10-22 14:38:55 -0500270 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500271#endif
Becky Bruced52082b2008-11-07 13:46:19 -0600272
273 /*
274 * Warn if it looks like the device tree doesn't match u-boot.
275 * This is just an estimation, based on the location of CCSR,
276 * which is defined by the "reg" property in the soc node.
277 */
278 off = fdt_path_offset(blob, "/soc8641");
279 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
280 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
281
282 if (tmp) {
283 u64 addr;
Becky Bruce3f510db2008-11-10 19:45:35 -0600284 if (addrcells && (*addrcells == 1))
Becky Bruced52082b2008-11-07 13:46:19 -0600285 addr = *(u32 *)tmp;
Becky Bruce3f510db2008-11-10 19:45:35 -0600286 else
287 addr = *tmp;
Becky Bruced52082b2008-11-07 13:46:19 -0600288
289 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
290 printf("WARNING: The CCSRBAR address in your .dts "
291 "does not match the address of the CCSR "
292 "in u-boot. This means your .dts might "
293 "be old.\n");
294 }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500295}
296#endif
297
Jon Loeligerdebb7352006-04-26 17:58:56 -0500298
Haiying Wang239db372006-07-28 12:41:18 -0400299/*
300 * get_board_sys_clk
301 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
302 */
303
Jon Loeliger80e955c2006-08-22 12:25:27 -0500304unsigned long
305get_board_sys_clk(ulong dummy)
Haiying Wang239db372006-07-28 12:41:18 -0400306{
307 u8 i, go_bit, rd_clks;
308 ulong val = 0;
309
310 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
311 go_bit &= 0x01;
312
313 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
314 rd_clks &= 0x1C;
315
316 /*
317 * Only if both go bit and the SCLK bit in VCFGEN0 are set
318 * should we be using the AUX register. Remember, we also set the
319 * GO bit to boot from the alternate bank on the on-board flash
320 */
321
322 if (go_bit) {
323 if (rd_clks == 0x1c)
324 i = in8(PIXIS_BASE + PIXIS_AUX);
325 else
326 i = in8(PIXIS_BASE + PIXIS_SPD);
327 } else {
328 i = in8(PIXIS_BASE + PIXIS_SPD);
329 }
330
331 i &= 0x07;
332
333 switch (i) {
334 case 0:
335 val = 33000000;
336 break;
337 case 1:
338 val = 40000000;
339 break;
340 case 2:
341 val = 50000000;
342 break;
343 case 3:
344 val = 66000000;
345 break;
346 case 4:
347 val = 83000000;
348 break;
349 case 5:
350 val = 100000000;
351 break;
352 case 6:
353 val = 134000000;
354 break;
355 case 7:
356 val = 166000000;
357 break;
358 }
359
360 return val;
361}
Ben Warren0b252f52008-08-31 21:41:08 -0700362
363int board_eth_init(bd_t *bis)
364{
365 /* Initialize TSECs */
366 cpu_eth_init(bis);
367 return pci_eth_init(bis);
368}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600369
370void board_reset(void)
371{
372 out8(PIXIS_BASE + PIXIS_RST, 0);
373
374 while (1)
375 ;
376}
Becky Brucef6ef8b72009-03-31 18:38:37 -0500377
Kumar Gala7649a592009-03-31 23:02:38 -0500378#ifdef CONFIG_MP
Becky Brucef6ef8b72009-03-31 18:38:37 -0500379extern void cpu_mp_lmb_reserve(struct lmb *lmb);
380
381void board_lmb_reserve(struct lmb *lmb)
382{
383 cpu_mp_lmb_reserve(lmb);
384}
385#endif