Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 2 | |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 3 | /* |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 4 | * Freescale QuadSPI driver. |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 5 | * |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 6 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 7 | * Copyright (C) 2018 Bootlin |
| 8 | * Copyright (C) 2018 exceet electronics GmbH |
| 9 | * Copyright (C) 2018 Kontron Electronics GmbH |
| 10 | * Copyright 2019-2020 NXP |
| 11 | * |
| 12 | * This driver is a ported version of Linux Freescale QSPI driver taken from |
| 13 | * v5.5-rc1 tag having following information. |
| 14 | * |
| 15 | * Transition to SPI MEM interface: |
| 16 | * Authors: |
| 17 | * Boris Brezillon <bbrezillon@kernel.org> |
| 18 | * Frieder Schrempf <frieder.schrempf@kontron.de> |
| 19 | * Yogesh Gaur <yogeshnarayan.gaur@nxp.com> |
| 20 | * Suresh Gupta <suresh.gupta@nxp.com> |
| 21 | * |
| 22 | * Based on the original fsl-quadspi.c spi-nor driver. |
| 23 | * Transition to spi-mem in spi-fsl-qspi.c |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include <common.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 27 | #include <log.h> |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 28 | #include <asm/io.h> |
Simon Glass | 4d72caa | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 29 | #include <linux/libfdt.h> |
| 30 | #include <linux/sizes.h> |
| 31 | #include <linux/iopoll.h> |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 32 | #include <dm.h> |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 33 | #include <linux/iopoll.h> |
| 34 | #include <linux/sizes.h> |
| 35 | #include <linux/err.h> |
| 36 | #include <spi.h> |
| 37 | #include <spi-mem.h> |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 38 | |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 41 | /* |
| 42 | * The driver only uses one single LUT entry, that is updated on |
| 43 | * each call of exec_op(). Index 0 is preset at boot with a basic |
| 44 | * read operation, so let's use the last entry (15). |
| 45 | */ |
| 46 | #define SEQID_LUT 15 |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 47 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 48 | /* Registers used by the driver */ |
| 49 | #define QUADSPI_MCR 0x00 |
| 50 | #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) |
| 51 | #define QUADSPI_MCR_MDIS_MASK BIT(14) |
| 52 | #define QUADSPI_MCR_CLR_TXF_MASK BIT(11) |
| 53 | #define QUADSPI_MCR_CLR_RXF_MASK BIT(10) |
| 54 | #define QUADSPI_MCR_DDR_EN_MASK BIT(7) |
| 55 | #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) |
| 56 | #define QUADSPI_MCR_SWRSTHD_MASK BIT(1) |
| 57 | #define QUADSPI_MCR_SWRSTSD_MASK BIT(0) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 58 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 59 | #define QUADSPI_IPCR 0x08 |
| 60 | #define QUADSPI_IPCR_SEQID(x) ((x) << 24) |
| 61 | #define QUADSPI_FLSHCR 0x0c |
| 62 | #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) |
| 63 | #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) |
| 64 | #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 65 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 66 | #define QUADSPI_BUF3CR 0x1c |
| 67 | #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) |
| 68 | #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) |
| 69 | #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 70 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 71 | #define QUADSPI_BFGENCR 0x20 |
| 72 | #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) |
Peng Fan | a235878 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 73 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 74 | #define QUADSPI_BUF0IND 0x30 |
| 75 | #define QUADSPI_BUF1IND 0x34 |
| 76 | #define QUADSPI_BUF2IND 0x38 |
| 77 | #define QUADSPI_SFAR 0x100 |
Peng Fan | a235878 | 2015-01-04 17:07:14 +0800 | [diff] [blame] | 78 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 79 | #define QUADSPI_SMPR 0x108 |
| 80 | #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) |
| 81 | #define QUADSPI_SMPR_FSDLY_MASK BIT(6) |
| 82 | #define QUADSPI_SMPR_FSPHS_MASK BIT(5) |
| 83 | #define QUADSPI_SMPR_HSENA_MASK BIT(0) |
Yuan Yao | febffe8 | 2016-03-15 14:36:42 +0800 | [diff] [blame] | 84 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 85 | #define QUADSPI_RBCT 0x110 |
| 86 | #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) |
| 87 | #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 88 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 89 | #define QUADSPI_TBDR 0x154 |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 90 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 91 | #define QUADSPI_SR 0x15c |
| 92 | #define QUADSPI_SR_IP_ACC_MASK BIT(1) |
| 93 | #define QUADSPI_SR_AHB_ACC_MASK BIT(2) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 94 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 95 | #define QUADSPI_FR 0x160 |
| 96 | #define QUADSPI_FR_TFF_MASK BIT(0) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 97 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 98 | #define QUADSPI_RSER 0x164 |
| 99 | #define QUADSPI_RSER_TFIE BIT(0) |
| 100 | |
| 101 | #define QUADSPI_SPTRCLR 0x16c |
| 102 | #define QUADSPI_SPTRCLR_IPPTRC BIT(8) |
| 103 | #define QUADSPI_SPTRCLR_BFPTRC BIT(0) |
| 104 | |
| 105 | #define QUADSPI_SFA1AD 0x180 |
| 106 | #define QUADSPI_SFA2AD 0x184 |
| 107 | #define QUADSPI_SFB1AD 0x188 |
| 108 | #define QUADSPI_SFB2AD 0x18c |
| 109 | #define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) |
| 110 | |
| 111 | #define QUADSPI_LUTKEY 0x300 |
| 112 | #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 |
| 113 | |
| 114 | #define QUADSPI_LCKCR 0x304 |
| 115 | #define QUADSPI_LCKER_LOCK BIT(0) |
| 116 | #define QUADSPI_LCKER_UNLOCK BIT(1) |
| 117 | |
| 118 | #define QUADSPI_LUT_BASE 0x310 |
| 119 | #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) |
| 120 | #define QUADSPI_LUT_REG(idx) \ |
| 121 | (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) |
| 122 | |
| 123 | /* Instruction set for the LUT register */ |
| 124 | #define LUT_STOP 0 |
| 125 | #define LUT_CMD 1 |
| 126 | #define LUT_ADDR 2 |
| 127 | #define LUT_DUMMY 3 |
| 128 | #define LUT_MODE 4 |
| 129 | #define LUT_MODE2 5 |
| 130 | #define LUT_MODE4 6 |
| 131 | #define LUT_FSL_READ 7 |
| 132 | #define LUT_FSL_WRITE 8 |
| 133 | #define LUT_JMP_ON_CS 9 |
| 134 | #define LUT_ADDR_DDR 10 |
| 135 | #define LUT_MODE_DDR 11 |
| 136 | #define LUT_MODE2_DDR 12 |
| 137 | #define LUT_MODE4_DDR 13 |
| 138 | #define LUT_FSL_READ_DDR 14 |
| 139 | #define LUT_FSL_WRITE_DDR 15 |
| 140 | #define LUT_DATA_LEARN 16 |
| 141 | |
| 142 | /* |
| 143 | * The PAD definitions for LUT register. |
| 144 | * |
| 145 | * The pad stands for the number of IO lines [0:3]. |
| 146 | * For example, the quad read needs four IO lines, |
| 147 | * so you should use LUT_PAD(4). |
| 148 | */ |
| 149 | #define LUT_PAD(x) (fls(x) - 1) |
| 150 | |
| 151 | /* |
| 152 | * Macro for constructing the LUT entries with the following |
| 153 | * register layout: |
| 154 | * |
| 155 | * --------------------------------------------------- |
| 156 | * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | |
| 157 | * --------------------------------------------------- |
| 158 | */ |
| 159 | #define LUT_DEF(idx, ins, pad, opr) \ |
| 160 | ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) |
| 161 | |
| 162 | /* Controller needs driver to swap endianness */ |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 163 | #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) |
| 164 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 165 | /* Controller needs 4x internal clock */ |
| 166 | #define QUADSPI_QUIRK_4X_INT_CLK BIT(1) |
| 167 | |
| 168 | /* |
| 169 | * TKT253890, the controller needs the driver to fill the txfifo with |
| 170 | * 16 bytes at least to trigger a data transfer, even though the extra |
| 171 | * data won't be transferred. |
| 172 | */ |
| 173 | #define QUADSPI_QUIRK_TKT253890 BIT(2) |
| 174 | |
| 175 | /* TKT245618, the controller cannot wake up from wait mode */ |
| 176 | #define QUADSPI_QUIRK_TKT245618 BIT(3) |
| 177 | |
| 178 | /* |
| 179 | * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) |
| 180 | * internally. No need to add it when setting SFXXAD and SFAR registers |
| 181 | */ |
| 182 | #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) |
| 183 | |
| 184 | /* |
| 185 | * Controller uses TDH bits in register QUADSPI_FLSHCR. |
| 186 | * They need to be set in accordance with the DDR/SDR mode. |
| 187 | */ |
| 188 | #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 189 | |
| 190 | struct fsl_qspi_devtype_data { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 191 | unsigned int rxfifo; |
| 192 | unsigned int txfifo; |
| 193 | unsigned int ahb_buf_size; |
| 194 | unsigned int quirks; |
| 195 | bool little_endian; |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 196 | }; |
| 197 | |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 198 | static const struct fsl_qspi_devtype_data vybrid_data = { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 199 | .rxfifo = SZ_128, |
| 200 | .txfifo = SZ_64, |
| 201 | .ahb_buf_size = SZ_1K, |
| 202 | .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, |
| 203 | .little_endian = true, |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | static const struct fsl_qspi_devtype_data imx6sx_data = { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 207 | .rxfifo = SZ_128, |
| 208 | .txfifo = SZ_512, |
| 209 | .ahb_buf_size = SZ_1K, |
| 210 | .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, |
| 211 | .little_endian = true, |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 212 | }; |
| 213 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 214 | static const struct fsl_qspi_devtype_data imx7d_data = { |
| 215 | .rxfifo = SZ_128, |
| 216 | .txfifo = SZ_512, |
| 217 | .ahb_buf_size = SZ_1K, |
| 218 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
| 219 | QUADSPI_QUIRK_USE_TDH_SETTING, |
| 220 | .little_endian = true, |
Ye Li | ce7575a | 2019-08-14 11:31:36 +0000 | [diff] [blame] | 221 | }; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 222 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 223 | static const struct fsl_qspi_devtype_data imx6ul_data = { |
| 224 | .rxfifo = SZ_128, |
| 225 | .txfifo = SZ_512, |
| 226 | .ahb_buf_size = SZ_1K, |
| 227 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | |
| 228 | QUADSPI_QUIRK_USE_TDH_SETTING, |
| 229 | .little_endian = true, |
Ye Li | 9699fb4 | 2019-08-14 11:31:40 +0000 | [diff] [blame] | 230 | }; |
| 231 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 232 | static const struct fsl_qspi_devtype_data ls1021a_data = { |
| 233 | .rxfifo = SZ_128, |
| 234 | .txfifo = SZ_64, |
| 235 | .ahb_buf_size = SZ_1K, |
| 236 | .quirks = 0, |
| 237 | .little_endian = false, |
| 238 | }; |
| 239 | |
| 240 | static const struct fsl_qspi_devtype_data ls1088a_data = { |
| 241 | .rxfifo = SZ_128, |
| 242 | .txfifo = SZ_128, |
| 243 | .ahb_buf_size = SZ_1K, |
| 244 | .quirks = QUADSPI_QUIRK_TKT253890, |
| 245 | .little_endian = true, |
| 246 | }; |
| 247 | |
| 248 | static const struct fsl_qspi_devtype_data ls2080a_data = { |
| 249 | .rxfifo = SZ_128, |
| 250 | .txfifo = SZ_64, |
| 251 | .ahb_buf_size = SZ_1K, |
| 252 | .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, |
| 253 | .little_endian = true, |
| 254 | }; |
| 255 | |
| 256 | struct fsl_qspi { |
| 257 | struct udevice *dev; |
| 258 | void __iomem *iobase; |
| 259 | void __iomem *ahb_addr; |
| 260 | u32 memmap_phy; |
| 261 | const struct fsl_qspi_devtype_data *devtype_data; |
| 262 | int selected; |
| 263 | }; |
| 264 | |
| 265 | static inline int needs_swap_endian(struct fsl_qspi *q) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 266 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 267 | return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 268 | } |
| 269 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 270 | static inline int needs_4x_clock(struct fsl_qspi *q) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 271 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 272 | return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 273 | } |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 274 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 275 | static inline int needs_fill_txfifo(struct fsl_qspi *q) |
Rajat Srivastava | 1f55356 | 2018-03-22 13:30:55 +0530 | [diff] [blame] | 276 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 277 | return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; |
Rajat Srivastava | 1f55356 | 2018-03-22 13:30:55 +0530 | [diff] [blame] | 278 | } |
| 279 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 280 | static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 281 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 282 | return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 283 | } |
| 284 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 285 | static inline int needs_amba_base_offset(struct fsl_qspi *q) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 286 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 287 | return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 288 | } |
| 289 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 290 | static inline int needs_tdh_setting(struct fsl_qspi *q) |
| 291 | { |
| 292 | return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; |
| 293 | } |
| 294 | |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 295 | /* |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 296 | * An IC bug makes it necessary to rearrange the 32-bit data. |
| 297 | * Later chips, such as IMX6SLX, have fixed this bug. |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 298 | */ |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 299 | static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 300 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 301 | return needs_swap_endian(q) ? __swab32(a) : a; |
| 302 | } |
| 303 | |
| 304 | /* |
| 305 | * R/W functions for big- or little-endian registers: |
| 306 | * The QSPI controller's endianness is independent of |
| 307 | * the CPU core's endianness. So far, although the CPU |
| 308 | * core is little-endian the QSPI controller can use |
| 309 | * big-endian or little-endian. |
| 310 | */ |
| 311 | static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) |
| 312 | { |
| 313 | if (q->devtype_data->little_endian) |
| 314 | out_le32(addr, val); |
| 315 | else |
| 316 | out_be32(addr, val); |
| 317 | } |
| 318 | |
| 319 | static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) |
| 320 | { |
| 321 | if (q->devtype_data->little_endian) |
| 322 | return in_le32(addr); |
| 323 | |
| 324 | return in_be32(addr); |
| 325 | } |
| 326 | |
| 327 | static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) |
| 328 | { |
| 329 | switch (width) { |
| 330 | case 1: |
| 331 | case 2: |
| 332 | case 4: |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | return -ENOTSUPP; |
| 337 | } |
| 338 | |
| 339 | static bool fsl_qspi_supports_op(struct spi_slave *slave, |
| 340 | const struct spi_mem_op *op) |
| 341 | { |
| 342 | struct fsl_qspi *q = dev_get_priv(slave->dev->parent); |
| 343 | int ret; |
| 344 | |
| 345 | ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); |
| 346 | |
| 347 | if (op->addr.nbytes) |
| 348 | ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); |
| 349 | |
| 350 | if (op->dummy.nbytes) |
| 351 | ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); |
| 352 | |
| 353 | if (op->data.nbytes) |
| 354 | ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); |
| 355 | |
| 356 | if (ret) |
| 357 | return false; |
| 358 | |
| 359 | /* |
| 360 | * The number of instructions needed for the op, needs |
| 361 | * to fit into a single LUT entry. |
| 362 | */ |
| 363 | if (op->addr.nbytes + |
| 364 | (op->dummy.nbytes ? 1 : 0) + |
| 365 | (op->data.nbytes ? 1 : 0) > 6) |
| 366 | return false; |
| 367 | |
| 368 | /* Max 64 dummy clock cycles supported */ |
| 369 | if (op->dummy.nbytes && |
| 370 | (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) |
| 371 | return false; |
| 372 | |
| 373 | /* Max data length, check controller limits and alignment */ |
| 374 | if (op->data.dir == SPI_MEM_DATA_IN && |
| 375 | (op->data.nbytes > q->devtype_data->ahb_buf_size || |
| 376 | (op->data.nbytes > q->devtype_data->rxfifo - 4 && |
| 377 | !IS_ALIGNED(op->data.nbytes, 8)))) |
| 378 | return false; |
| 379 | |
| 380 | if (op->data.dir == SPI_MEM_DATA_OUT && |
| 381 | op->data.nbytes > q->devtype_data->txfifo) |
| 382 | return false; |
| 383 | |
| 384 | return true; |
| 385 | } |
| 386 | |
| 387 | static void fsl_qspi_prepare_lut(struct fsl_qspi *q, |
| 388 | const struct spi_mem_op *op) |
| 389 | { |
| 390 | void __iomem *base = q->iobase; |
| 391 | u32 lutval[4] = {}; |
| 392 | int lutidx = 1, i; |
| 393 | |
| 394 | lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), |
| 395 | op->cmd.opcode); |
| 396 | |
| 397 | /* |
| 398 | * For some unknown reason, using LUT_ADDR doesn't work in some |
| 399 | * cases (at least with only one byte long addresses), so |
| 400 | * let's use LUT_MODE to write the address bytes one by one |
| 401 | */ |
| 402 | for (i = 0; i < op->addr.nbytes; i++) { |
| 403 | u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); |
| 404 | |
| 405 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, |
| 406 | LUT_PAD(op->addr.buswidth), |
| 407 | addrbyte); |
| 408 | lutidx++; |
| 409 | } |
| 410 | |
| 411 | if (op->dummy.nbytes) { |
| 412 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, |
| 413 | LUT_PAD(op->dummy.buswidth), |
| 414 | op->dummy.nbytes * 8 / |
| 415 | op->dummy.buswidth); |
| 416 | lutidx++; |
| 417 | } |
| 418 | |
| 419 | if (op->data.nbytes) { |
| 420 | lutval[lutidx / 2] |= LUT_DEF(lutidx, |
| 421 | op->data.dir == SPI_MEM_DATA_IN ? |
| 422 | LUT_FSL_READ : LUT_FSL_WRITE, |
| 423 | LUT_PAD(op->data.buswidth), |
| 424 | 0); |
| 425 | lutidx++; |
| 426 | } |
| 427 | |
| 428 | lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); |
| 429 | |
| 430 | /* unlock LUT */ |
| 431 | qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); |
| 432 | qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); |
| 433 | |
| 434 | dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", |
| 435 | op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); |
| 436 | |
| 437 | /* fill LUT */ |
| 438 | for (i = 0; i < ARRAY_SIZE(lutval); i++) |
| 439 | qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); |
| 440 | |
| 441 | /* lock LUT */ |
| 442 | qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); |
| 443 | qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * If we have changed the content of the flash by writing or erasing, or if we |
| 448 | * read from flash with a different offset into the page buffer, we need to |
| 449 | * invalidate the AHB buffer. If we do not do so, we may read out the wrong |
| 450 | * data. The spec tells us reset the AHB domain and Serial Flash domain at |
| 451 | * the same time. |
| 452 | */ |
| 453 | static void fsl_qspi_invalidate(struct fsl_qspi *q) |
| 454 | { |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 455 | u32 reg; |
| 456 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 457 | reg = qspi_readl(q, q->iobase + QUADSPI_MCR); |
| 458 | reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; |
| 459 | qspi_writel(q, reg, q->iobase + QUADSPI_MCR); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 460 | |
| 461 | /* |
| 462 | * The minimum delay : 1 AHB + 2 SFCK clocks. |
| 463 | * Delay 1 us is enough. |
| 464 | */ |
| 465 | udelay(1); |
| 466 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 467 | reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); |
| 468 | qspi_writel(q, reg, q->iobase + QUADSPI_MCR); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 469 | } |
| 470 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 471 | static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 472 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 473 | struct dm_spi_slave_platdata *plat = |
| 474 | dev_get_parent_platdata(slave->dev); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 475 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 476 | if (q->selected == plat->cs) |
| 477 | return; |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 478 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 479 | q->selected = plat->cs; |
| 480 | fsl_qspi_invalidate(q); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 481 | } |
| 482 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 483 | static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 484 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 485 | memcpy_fromio(op->data.buf.in, |
| 486 | q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, |
| 487 | op->data.nbytes); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 488 | } |
| 489 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 490 | static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, |
| 491 | const struct spi_mem_op *op) |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 492 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 493 | void __iomem *base = q->iobase; |
Gong Qianyu | 5207014 | 2016-01-26 15:06:40 +0800 | [diff] [blame] | 494 | int i; |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 495 | u32 val; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 496 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 497 | for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { |
| 498 | memcpy(&val, op->data.buf.out + i, 4); |
| 499 | val = fsl_qspi_endian_xchg(q, val); |
| 500 | qspi_writel(q, val, base + QUADSPI_TBDR); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 501 | } |
| 502 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 503 | if (i < op->data.nbytes) { |
| 504 | memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); |
| 505 | val = fsl_qspi_endian_xchg(q, val); |
| 506 | qspi_writel(q, val, base + QUADSPI_TBDR); |
| 507 | } |
| 508 | |
| 509 | if (needs_fill_txfifo(q)) { |
| 510 | for (i = op->data.nbytes; i < 16; i += 4) |
| 511 | qspi_writel(q, 0, base + QUADSPI_TBDR); |
| 512 | } |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 513 | } |
| 514 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 515 | static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, |
| 516 | const struct spi_mem_op *op) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 517 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 518 | void __iomem *base = q->iobase; |
| 519 | int i; |
| 520 | u8 *buf = op->data.buf.in; |
| 521 | u32 val; |
Yuan Yao | febffe8 | 2016-03-15 14:36:42 +0800 | [diff] [blame] | 522 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 523 | for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { |
| 524 | val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); |
| 525 | val = fsl_qspi_endian_xchg(q, val); |
| 526 | memcpy(buf + i, &val, 4); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 527 | } |
| 528 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 529 | if (i < op->data.nbytes) { |
| 530 | val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); |
| 531 | val = fsl_qspi_endian_xchg(q, val); |
| 532 | memcpy(buf + i, &val, op->data.nbytes - i); |
| 533 | } |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 534 | } |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 535 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 536 | static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, |
| 537 | u32 mask, u32 delay_us, u32 timeout_us) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 538 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 539 | u32 reg; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 540 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 541 | if (!q->devtype_data->little_endian) |
| 542 | mask = (u32)cpu_to_be32(mask); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 543 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 544 | return readl_poll_timeout(base, reg, !(reg & mask), timeout_us); |
| 545 | } |
Alexander Stein | beedbc2 | 2015-11-04 09:19:10 +0100 | [diff] [blame] | 546 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 547 | static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) |
| 548 | { |
| 549 | void __iomem *base = q->iobase; |
| 550 | int err = 0; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 551 | |
Suresh Gupta | 1050998 | 2017-06-05 14:37:20 +0530 | [diff] [blame] | 552 | /* |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 553 | * Always start the sequence at the same index since we update |
| 554 | * the LUT at each exec_op() call. And also specify the DATA |
| 555 | * length, since it's has not been specified in the LUT. |
Suresh Gupta | 1050998 | 2017-06-05 14:37:20 +0530 | [diff] [blame] | 556 | */ |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 557 | qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), |
| 558 | base + QUADSPI_IPCR); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 559 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 560 | /* wait for the controller being ready */ |
| 561 | err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, |
| 562 | (QUADSPI_SR_IP_ACC_MASK | |
| 563 | QUADSPI_SR_AHB_ACC_MASK), |
| 564 | 10, 1000); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 565 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 566 | if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) |
| 567 | fsl_qspi_read_rxfifo(q, op); |
| 568 | |
| 569 | return err; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 570 | } |
| 571 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 572 | static int fsl_qspi_exec_op(struct spi_slave *slave, |
| 573 | const struct spi_mem_op *op) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 574 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 575 | struct fsl_qspi *q = dev_get_priv(slave->dev->parent); |
| 576 | void __iomem *base = q->iobase; |
| 577 | u32 addr_offset = 0; |
| 578 | int err = 0; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 579 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 580 | /* wait for the controller being ready */ |
| 581 | fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | |
| 582 | QUADSPI_SR_AHB_ACC_MASK), 10, 1000); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 583 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 584 | fsl_qspi_select_mem(q, slave); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 585 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 586 | if (needs_amba_base_offset(q)) |
| 587 | addr_offset = q->memmap_phy; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 588 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 589 | qspi_writel(q, |
| 590 | q->selected * q->devtype_data->ahb_buf_size + addr_offset, |
| 591 | base + QUADSPI_SFAR); |
Alexander Stein | 4df24f2 | 2017-06-01 09:32:19 +0200 | [diff] [blame] | 592 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 593 | qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | |
| 594 | QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, |
| 595 | base + QUADSPI_MCR); |
| 596 | |
| 597 | qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, |
| 598 | base + QUADSPI_SPTRCLR); |
| 599 | |
| 600 | fsl_qspi_prepare_lut(q, op); |
| 601 | |
| 602 | /* |
| 603 | * If we have large chunks of data, we read them through the AHB bus |
| 604 | * by accessing the mapped memory. In all other cases we use |
| 605 | * IP commands to access the flash. |
| 606 | */ |
| 607 | if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && |
| 608 | op->data.dir == SPI_MEM_DATA_IN) { |
| 609 | fsl_qspi_read_ahb(q, op); |
| 610 | } else { |
| 611 | qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | |
| 612 | QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); |
| 613 | |
| 614 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) |
| 615 | fsl_qspi_fill_txfifo(q, op); |
| 616 | |
| 617 | err = fsl_qspi_do_op(q, op); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 618 | } |
| 619 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 620 | /* Invalidate the data in the AHB buffer. */ |
| 621 | fsl_qspi_invalidate(q); |
| 622 | |
| 623 | return err; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 624 | } |
| 625 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 626 | static int fsl_qspi_adjust_op_size(struct spi_slave *slave, |
| 627 | struct spi_mem_op *op) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 628 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 629 | struct fsl_qspi *q = dev_get_priv(slave->dev->parent); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 630 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 631 | if (op->data.dir == SPI_MEM_DATA_OUT) { |
| 632 | if (op->data.nbytes > q->devtype_data->txfifo) |
| 633 | op->data.nbytes = q->devtype_data->txfifo; |
| 634 | } else { |
| 635 | if (op->data.nbytes > q->devtype_data->ahb_buf_size) |
| 636 | op->data.nbytes = q->devtype_data->ahb_buf_size; |
| 637 | else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) |
| 638 | op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 639 | } |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 640 | |
| 641 | return 0; |
| 642 | } |
| 643 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 644 | static int fsl_qspi_default_setup(struct fsl_qspi *q) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 645 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 646 | void __iomem *base = q->iobase; |
| 647 | u32 reg, addr_offset = 0; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 648 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 649 | /* Reset the module */ |
| 650 | qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, |
| 651 | base + QUADSPI_MCR); |
| 652 | udelay(1); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 653 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 654 | /* Disable the module */ |
| 655 | qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, |
| 656 | base + QUADSPI_MCR); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 657 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 658 | /* |
| 659 | * Previous boot stages (BootROM, bootloader) might have used DDR |
| 660 | * mode and did not clear the TDH bits. As we currently use SDR mode |
| 661 | * only, clear the TDH bits if necessary. |
| 662 | */ |
| 663 | if (needs_tdh_setting(q)) |
| 664 | qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & |
| 665 | ~QUADSPI_FLSHCR_TDH_MASK, |
| 666 | base + QUADSPI_FLSHCR); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 667 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 668 | reg = qspi_readl(q, base + QUADSPI_SMPR); |
| 669 | qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK |
| 670 | | QUADSPI_SMPR_FSPHS_MASK |
| 671 | | QUADSPI_SMPR_HSENA_MASK |
| 672 | | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 673 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 674 | /* We only use the buffer3 for AHB read */ |
| 675 | qspi_writel(q, 0, base + QUADSPI_BUF0IND); |
| 676 | qspi_writel(q, 0, base + QUADSPI_BUF1IND); |
| 677 | qspi_writel(q, 0, base + QUADSPI_BUF2IND); |
Peng Fan | 5f7f70c | 2015-01-08 10:40:20 +0800 | [diff] [blame] | 678 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 679 | qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), |
| 680 | q->iobase + QUADSPI_BFGENCR); |
| 681 | qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); |
| 682 | qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | |
| 683 | QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), |
| 684 | base + QUADSPI_BUF3CR); |
| 685 | |
| 686 | if (needs_amba_base_offset(q)) |
| 687 | addr_offset = q->memmap_phy; |
| 688 | |
| 689 | /* |
| 690 | * In HW there can be a maximum of four chips on two buses with |
| 691 | * two chip selects on each bus. We use four chip selects in SW |
| 692 | * to differentiate between the four chips. |
| 693 | * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, |
| 694 | * SFB2AD accordingly. |
| 695 | */ |
| 696 | qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, |
| 697 | base + QUADSPI_SFA1AD); |
| 698 | qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, |
| 699 | base + QUADSPI_SFA2AD); |
| 700 | qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, |
| 701 | base + QUADSPI_SFB1AD); |
| 702 | qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, |
| 703 | base + QUADSPI_SFB2AD); |
| 704 | |
| 705 | q->selected = -1; |
| 706 | |
| 707 | /* Enable the module */ |
| 708 | qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, |
| 709 | base + QUADSPI_MCR); |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 710 | return 0; |
| 711 | } |
| 712 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 713 | static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { |
| 714 | .adjust_op_size = fsl_qspi_adjust_op_size, |
| 715 | .supports_op = fsl_qspi_supports_op, |
| 716 | .exec_op = fsl_qspi_exec_op, |
| 717 | }; |
| 718 | |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 719 | static int fsl_qspi_probe(struct udevice *bus) |
| 720 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 721 | struct dm_spi_bus *dm_bus = bus->uclass_priv; |
| 722 | struct fsl_qspi *q = dev_get_priv(bus); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 723 | const void *blob = gd->fdt_blob; |
Simon Glass | e160f7d | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 724 | int node = dev_of_offset(bus); |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 725 | struct fdt_resource res; |
| 726 | int ret; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 727 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 728 | q->dev = bus; |
| 729 | q->devtype_data = (struct fsl_qspi_devtype_data *) |
| 730 | dev_get_driver_data(bus); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 731 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 732 | /* find the resources */ |
| 733 | ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI", |
| 734 | &res); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 735 | if (ret) { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 736 | dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 737 | return -ENOMEM; |
| 738 | } |
| 739 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 740 | q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 741 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 742 | ret = fdt_get_named_resource(blob, node, "reg", "reg-names", |
| 743 | "QuadSPI-memory", &res); |
| 744 | if (ret) { |
| 745 | dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret); |
| 746 | return -ENOMEM; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 747 | } |
| 748 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 749 | q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); |
| 750 | q->memmap_phy = res.start; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 751 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 752 | dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", |
| 753 | 66000000); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 754 | |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 755 | fsl_qspi_default_setup(q); |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 756 | |
| 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 761 | const void *dout, void *din, unsigned long flags) |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 762 | { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 763 | return 0; |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 764 | } |
| 765 | |
| 766 | static int fsl_qspi_claim_bus(struct udevice *dev) |
| 767 | { |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | static int fsl_qspi_release_bus(struct udevice *dev) |
| 772 | { |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 773 | return 0; |
| 774 | } |
| 775 | |
| 776 | static int fsl_qspi_set_speed(struct udevice *bus, uint speed) |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 777 | { |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 778 | return 0; |
Alison Wang | 6b57ff6 | 2014-05-06 09:13:01 +0800 | [diff] [blame] | 779 | } |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 780 | |
| 781 | static int fsl_qspi_set_mode(struct udevice *bus, uint mode) |
| 782 | { |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 783 | return 0; |
| 784 | } |
| 785 | |
| 786 | static const struct dm_spi_ops fsl_qspi_ops = { |
| 787 | .claim_bus = fsl_qspi_claim_bus, |
| 788 | .release_bus = fsl_qspi_release_bus, |
| 789 | .xfer = fsl_qspi_xfer, |
| 790 | .set_speed = fsl_qspi_set_speed, |
| 791 | .set_mode = fsl_qspi_set_mode, |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 792 | .mem_ops = &fsl_qspi_mem_ops, |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 793 | }; |
| 794 | |
| 795 | static const struct udevice_id fsl_qspi_ids[] = { |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 796 | { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, }, |
| 797 | { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, |
| 798 | { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, |
| 799 | { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, |
| 800 | { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, |
| 801 | { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, |
| 802 | { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 803 | { } |
| 804 | }; |
| 805 | |
| 806 | U_BOOT_DRIVER(fsl_qspi) = { |
| 807 | .name = "fsl_qspi", |
| 808 | .id = UCLASS_SPI, |
| 809 | .of_match = fsl_qspi_ids, |
| 810 | .ops = &fsl_qspi_ops, |
Kuldeep Singh | 91afd36 | 2020-02-20 22:57:52 +0530 | [diff] [blame] | 811 | .priv_auto_alloc_size = sizeof(struct fsl_qspi), |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 812 | .probe = fsl_qspi_probe, |
Haikun.Wang@freescale.com | 5bc4830 | 2015-04-01 11:10:40 +0800 | [diff] [blame] | 813 | }; |