Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Clock initialization for OMAP4 |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Aneesh V <aneesh@ti.com> |
| 9 | * |
| 10 | * Based on previous work by: |
| 11 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 12 | * Rajendra Nayak <rnayak@ti.com> |
| 13 | * |
| 14 | * See file CREDITS for list of people who contributed to this |
| 15 | * project. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 30 | * MA 02111-1307 USA |
| 31 | */ |
| 32 | #include <common.h> |
| 33 | #include <asm/omap_common.h> |
| 34 | #include <asm/arch/clocks.h> |
| 35 | #include <asm/arch/sys_proto.h> |
| 36 | #include <asm/utils.h> |
| 37 | |
| 38 | #ifndef CONFIG_SPL_BUILD |
| 39 | /* |
| 40 | * printing to console doesn't work unless |
| 41 | * this code is executed from SPL |
| 42 | */ |
| 43 | #define printf(fmt, args...) |
| 44 | #define puts(s) |
| 45 | #endif |
| 46 | |
| 47 | #define abs(x) (((x) < 0) ? ((x)*-1) : (x)) |
| 48 | |
| 49 | struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; |
| 50 | |
| 51 | static const u32 sys_clk_array[8] = { |
| 52 | 12000000, /* 12 MHz */ |
| 53 | 13000000, /* 13 MHz */ |
| 54 | 16800000, /* 16.8 MHz */ |
| 55 | 19200000, /* 19.2 MHz */ |
| 56 | 26000000, /* 26 MHz */ |
| 57 | 27000000, /* 27 MHz */ |
| 58 | 38400000, /* 38.4 MHz */ |
| 59 | }; |
| 60 | |
| 61 | /* |
| 62 | * The M & N values in the following tables are created using the |
| 63 | * following tool: |
| 64 | * tools/omap/clocks_get_m_n.c |
| 65 | * Please use this tool for creating the table for any new frequency. |
| 66 | */ |
| 67 | |
| 68 | /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */ |
| 69 | static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { |
| 70 | {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 71 | {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 72 | {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 73 | {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 74 | {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 75 | {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 76 | {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
| 77 | }; |
| 78 | |
| 79 | /* dpll locked at 1200 MHz - MPU clk at 600 MHz */ |
| 80 | static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { |
| 81 | {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 82 | {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 83 | {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 84 | {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 85 | {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 86 | {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 87 | {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
| 88 | }; |
| 89 | |
| 90 | static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
| 91 | {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
| 92 | {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
| 93 | {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
| 94 | {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
| 95 | {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
| 96 | {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
| 97 | {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
| 98 | }; |
| 99 | |
| 100 | static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { |
| 101 | {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
| 102 | {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
| 103 | {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
| 104 | {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
| 105 | {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
| 106 | {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
| 107 | {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
| 108 | }; |
| 109 | |
| 110 | static const struct dpll_params |
| 111 | core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { |
| 112 | {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ |
| 113 | {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ |
| 114 | {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
| 115 | {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
| 116 | {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ |
| 117 | {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ |
| 118 | {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
| 119 | }; |
| 120 | |
| 121 | static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { |
| 122 | {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ |
| 123 | {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ |
| 124 | {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ |
| 125 | {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ |
| 126 | {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ |
| 127 | {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ |
| 128 | {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ |
| 129 | }; |
| 130 | |
| 131 | static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { |
| 132 | {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ |
| 133 | {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ |
| 134 | {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ |
| 135 | {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ |
| 136 | {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ |
| 137 | {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ |
| 138 | {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ |
| 139 | }; |
| 140 | |
| 141 | /* ABE M & N values with sys_clk as source */ |
| 142 | static const struct dpll_params |
| 143 | abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
| 144 | {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ |
| 145 | {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ |
| 146 | {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 147 | {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 148 | {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ |
| 149 | {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ |
| 150 | {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ |
| 151 | }; |
| 152 | |
| 153 | /* ABE M & N values with 32K clock as source */ |
| 154 | static const struct dpll_params abe_dpll_params_32k_196608khz = { |
| 155 | 750, 0, 1, 1, -1, -1, -1, -1 |
| 156 | }; |
| 157 | |
| 158 | |
| 159 | static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
| 160 | {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 161 | {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 162 | {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 163 | {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 164 | {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 165 | {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 166 | {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
| 167 | }; |
| 168 | |
| 169 | static inline u32 __get_sys_clk_index(void) |
| 170 | { |
| 171 | u32 ind; |
| 172 | /* |
| 173 | * For ES1 the ROM code calibration of sys clock is not reliable |
| 174 | * due to hw issue. So, use hard-coded value. If this value is not |
| 175 | * correct for any board over-ride this function in board file |
| 176 | * From ES2.0 onwards you will get this information from |
| 177 | * CM_SYS_CLKSEL |
| 178 | */ |
| 179 | if (omap_revision() == OMAP4430_ES1_0) |
| 180 | ind = OMAP_SYS_CLK_IND_38_4_MHZ; |
| 181 | else { |
| 182 | /* SYS_CLKSEL - 1 to match the dpll param array indices */ |
| 183 | ind = (readl(&prcm->cm_sys_clksel) & |
| 184 | CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; |
| 185 | } |
| 186 | return ind; |
| 187 | } |
| 188 | |
| 189 | u32 get_sys_clk_index(void) |
| 190 | __attribute__ ((weak, alias("__get_sys_clk_index"))); |
| 191 | |
| 192 | u32 get_sys_clk_freq(void) |
| 193 | { |
| 194 | u8 index = get_sys_clk_index(); |
| 195 | return sys_clk_array[index]; |
| 196 | } |
| 197 | |
| 198 | static inline void do_bypass_dpll(u32 *const base) |
| 199 | { |
| 200 | struct dpll_regs *dpll_regs = (struct dpll_regs *)base; |
| 201 | |
| 202 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 203 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 204 | DPLL_EN_FAST_RELOCK_BYPASS << |
| 205 | CM_CLKMODE_DPLL_EN_SHIFT); |
| 206 | } |
| 207 | |
| 208 | static inline void wait_for_bypass(u32 *const base) |
| 209 | { |
| 210 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 211 | |
| 212 | if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, |
| 213 | LDELAY)) { |
| 214 | printf("Bypassing DPLL failed %p\n", base); |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | static inline void do_lock_dpll(u32 *const base) |
| 219 | { |
| 220 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 221 | |
| 222 | clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
| 223 | CM_CLKMODE_DPLL_DPLL_EN_MASK, |
| 224 | DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); |
| 225 | } |
| 226 | |
| 227 | static inline void wait_for_lock(u32 *const base) |
| 228 | { |
| 229 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 230 | |
| 231 | if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, |
| 232 | &dpll_regs->cm_idlest_dpll, LDELAY)) { |
| 233 | printf("DPLL locking failed for %p\n", base); |
| 234 | hang(); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | static void do_setup_dpll(u32 *const base, const struct dpll_params *params, |
| 239 | u8 lock) |
| 240 | { |
| 241 | u32 temp; |
| 242 | struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
| 243 | |
| 244 | bypass_dpll(base); |
| 245 | |
| 246 | /* Set M & N */ |
| 247 | temp = readl(&dpll_regs->cm_clksel_dpll); |
| 248 | |
| 249 | temp &= ~CM_CLKSEL_DPLL_M_MASK; |
| 250 | temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; |
| 251 | |
| 252 | temp &= ~CM_CLKSEL_DPLL_N_MASK; |
| 253 | temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; |
| 254 | |
| 255 | writel(temp, &dpll_regs->cm_clksel_dpll); |
| 256 | |
| 257 | /* Lock */ |
| 258 | if (lock) |
| 259 | do_lock_dpll(base); |
| 260 | |
| 261 | /* Setup post-dividers */ |
| 262 | if (params->m2 >= 0) |
| 263 | writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
| 264 | if (params->m3 >= 0) |
| 265 | writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
| 266 | if (params->m4 >= 0) |
| 267 | writel(params->m4, &dpll_regs->cm_div_m4_dpll); |
| 268 | if (params->m5 >= 0) |
| 269 | writel(params->m5, &dpll_regs->cm_div_m5_dpll); |
| 270 | if (params->m6 >= 0) |
| 271 | writel(params->m6, &dpll_regs->cm_div_m6_dpll); |
| 272 | if (params->m7 >= 0) |
| 273 | writel(params->m7, &dpll_regs->cm_div_m7_dpll); |
| 274 | |
| 275 | /* Wait till the DPLL locks */ |
| 276 | if (lock) |
| 277 | wait_for_lock(base); |
| 278 | } |
| 279 | |
| 280 | const struct dpll_params *get_core_dpll_params(void) |
| 281 | { |
| 282 | u32 sysclk_ind = get_sys_clk_index(); |
| 283 | |
| 284 | switch (omap_revision()) { |
| 285 | case OMAP4430_ES1_0: |
| 286 | return &core_dpll_params_es1_1524mhz[sysclk_ind]; |
| 287 | case OMAP4430_ES2_0: |
| 288 | case OMAP4430_SILICON_ID_INVALID: |
| 289 | /* safest */ |
| 290 | return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; |
| 291 | default: |
| 292 | return &core_dpll_params_1600mhz[sysclk_ind]; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | u32 omap4_ddr_clk(void) |
| 297 | { |
| 298 | u32 ddr_clk, sys_clk_khz; |
| 299 | const struct dpll_params *core_dpll_params; |
| 300 | |
| 301 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 302 | |
| 303 | core_dpll_params = get_core_dpll_params(); |
| 304 | |
| 305 | debug("sys_clk %d\n ", sys_clk_khz * 1000); |
| 306 | |
| 307 | /* Find Core DPLL locked frequency first */ |
| 308 | ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / |
| 309 | (core_dpll_params->n + 1); |
| 310 | /* |
| 311 | * DDR frequency is PHY_ROOT_CLK/2 |
| 312 | * PHY_ROOT_CLK = Fdpll/2/M2 |
| 313 | */ |
| 314 | ddr_clk = ddr_clk / 4 / core_dpll_params->m2; |
| 315 | |
| 316 | ddr_clk *= 1000; /* convert to Hz */ |
| 317 | debug("ddr_clk %d\n ", ddr_clk); |
| 318 | |
| 319 | return ddr_clk; |
| 320 | } |
| 321 | |
| 322 | static void setup_dplls(void) |
| 323 | { |
| 324 | u32 sysclk_ind, temp; |
| 325 | const struct dpll_params *params; |
| 326 | debug("setup_dplls\n"); |
| 327 | |
| 328 | sysclk_ind = get_sys_clk_index(); |
| 329 | |
| 330 | /* CORE dpll */ |
| 331 | params = get_core_dpll_params(); /* default - safest */ |
| 332 | /* |
| 333 | * Do not lock the core DPLL now. Just set it up. |
| 334 | * Core DPLL will be locked after setting up EMIF |
| 335 | * using the FREQ_UPDATE method(freq_update_core()) |
| 336 | */ |
| 337 | do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); |
| 338 | /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ |
| 339 | temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | |
| 340 | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | |
| 341 | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); |
| 342 | writel(temp, &prcm->cm_clksel_core); |
| 343 | debug("Core DPLL configured\n"); |
| 344 | |
| 345 | /* lock PER dpll */ |
| 346 | do_setup_dpll(&prcm->cm_clkmode_dpll_per, |
| 347 | &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); |
| 348 | debug("PER DPLL locked\n"); |
| 349 | |
| 350 | /* MPU dpll */ |
| 351 | if (omap_revision() == OMAP4430_ES1_0) |
| 352 | params = &mpu_dpll_params_1200mhz[sysclk_ind]; |
| 353 | else |
| 354 | params = &mpu_dpll_params_1584mhz[sysclk_ind]; |
| 355 | do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); |
| 356 | debug("MPU DPLL locked\n"); |
| 357 | } |
| 358 | |
| 359 | static void setup_non_essential_dplls(void) |
| 360 | { |
| 361 | u32 sys_clk_khz, abe_ref_clk; |
| 362 | u32 sysclk_ind, sd_div, num, den; |
| 363 | const struct dpll_params *params; |
| 364 | |
| 365 | sysclk_ind = get_sys_clk_index(); |
| 366 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 367 | |
| 368 | /* IVA */ |
| 369 | clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, |
| 370 | CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); |
| 371 | |
| 372 | do_setup_dpll(&prcm->cm_clkmode_dpll_iva, |
| 373 | &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); |
| 374 | |
| 375 | /* |
| 376 | * USB: |
| 377 | * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction |
| 378 | * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) |
| 379 | * - where CLKINP is sys_clk in MHz |
| 380 | * Use CLKINP in KHz and adjust the denominator accordingly so |
| 381 | * that we have enough accuracy and at the same time no overflow |
| 382 | */ |
| 383 | params = &usb_dpll_params_1920mhz[sysclk_ind]; |
| 384 | num = params->m * sys_clk_khz; |
| 385 | den = (params->n + 1) * 250 * 1000; |
| 386 | num += den - 1; |
| 387 | sd_div = num / den; |
| 388 | clrsetbits_le32(&prcm->cm_clksel_dpll_usb, |
| 389 | CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, |
| 390 | sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); |
| 391 | |
| 392 | /* Now setup the dpll with the regular function */ |
| 393 | do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); |
| 394 | |
| 395 | #ifdef CONFIG_SYS_OMAP4_ABE_SYSCK |
| 396 | params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; |
| 397 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; |
| 398 | #else |
| 399 | params = &abe_dpll_params_32k_196608khz; |
| 400 | abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; |
| 401 | /* |
| 402 | * We need to enable some additional options to achieve |
| 403 | * 196.608MHz from 32768 Hz |
| 404 | */ |
| 405 | setbits_le32(&prcm->cm_clkmode_dpll_abe, |
| 406 | CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| |
| 407 | CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| |
| 408 | CM_CLKMODE_DPLL_LPMODE_EN_MASK| |
| 409 | CM_CLKMODE_DPLL_REGM4XEN_MASK); |
| 410 | /* Spend 4 REFCLK cycles at each stage */ |
| 411 | clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, |
| 412 | CM_CLKMODE_DPLL_RAMP_RATE_MASK, |
| 413 | 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); |
| 414 | #endif |
| 415 | |
| 416 | /* Select the right reference clk */ |
| 417 | clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, |
| 418 | CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, |
| 419 | abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); |
| 420 | /* Lock the dpll */ |
| 421 | do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); |
| 422 | } |
| 423 | |
| 424 | static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) |
| 425 | { |
| 426 | u32 temp, offset_code; |
| 427 | u32 step = 12660; /* 12.66 mV represented in uV */ |
| 428 | u32 offset = volt_mv; |
| 429 | |
| 430 | /* convert to uV for better accuracy in the calculations */ |
| 431 | offset *= 1000; |
| 432 | |
| 433 | if (omap_revision() == OMAP4430_ES1_0) |
| 434 | offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; |
| 435 | else |
| 436 | offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; |
| 437 | |
| 438 | offset_code = (offset + step - 1) / step; |
| 439 | /* The code starts at 1 not 0 */ |
| 440 | offset_code++; |
| 441 | |
| 442 | debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, |
| 443 | offset_code); |
| 444 | |
| 445 | temp = SMPS_I2C_SLAVE_ADDR | |
| 446 | (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | |
| 447 | (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | |
| 448 | PRM_VC_VAL_BYPASS_VALID_BIT; |
| 449 | writel(temp, &prcm->prm_vc_val_bypass); |
| 450 | if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, |
| 451 | &prcm->prm_vc_val_bypass, LDELAY)) { |
| 452 | printf("Scaling voltage failed for 0x%x\n", vcore_reg); |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
| 458 | * We set the maximum voltages allowed here because Smart-Reflex is not |
| 459 | * enabled in bootloader. Voltage initialization in the kernel will set |
| 460 | * these to the nominal values after enabling Smart-Reflex |
| 461 | */ |
| 462 | static void scale_vcores(void) |
| 463 | { |
| 464 | u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp; |
| 465 | |
| 466 | sys_clk_khz = get_sys_clk_freq() / 1000; |
| 467 | |
| 468 | /* |
| 469 | * Setup the dedicated I2C controller for Voltage Control |
| 470 | * I2C clk - high period 40% low period 60% |
| 471 | */ |
| 472 | cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; |
| 473 | cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; |
| 474 | /* values to be set in register - less by 5 & 7 respectively */ |
| 475 | cycles_hi -= 5; |
| 476 | cycles_low -= 7; |
| 477 | temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | |
| 478 | (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); |
| 479 | writel(temp, &prcm->prm_vc_cfg_i2c_clk); |
| 480 | |
| 481 | /* Disable high speed mode and all advanced features */ |
| 482 | writel(0x0, &prcm->prm_vc_cfg_i2c_mode); |
| 483 | |
| 484 | /* |
| 485 | * VCORE 1 - 4430 : supplies vdd_mpu |
| 486 | * Setting a high voltage for Nitro mode as smart reflex is not enabled. |
| 487 | * We use the maximum possible value in the AVS range because the next |
| 488 | * higher voltage in the discrete range (code >= 0b111010) is way too |
| 489 | * high |
| 490 | */ |
| 491 | volt = 1417; |
| 492 | do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
| 493 | |
| 494 | /* VCORE 2 - supplies vdd_iva */ |
| 495 | volt = 1200; |
| 496 | do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
| 497 | |
| 498 | /* VCORE 3 - supplies vdd_core */ |
| 499 | volt = 1200; |
| 500 | do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); |
| 501 | } |
| 502 | |
| 503 | static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) |
| 504 | { |
| 505 | clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, |
| 506 | enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); |
| 507 | debug("Enable clock domain - 0x%08x\n", clkctrl_reg); |
| 508 | } |
| 509 | |
| 510 | static inline void wait_for_clk_enable(u32 *clkctrl_addr) |
| 511 | { |
| 512 | u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; |
| 513 | u32 bound = LDELAY; |
| 514 | |
| 515 | while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || |
| 516 | (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { |
| 517 | |
| 518 | clkctrl = readl(clkctrl_addr); |
| 519 | idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> |
| 520 | MODULE_CLKCTRL_IDLEST_SHIFT; |
| 521 | if (--bound == 0) { |
| 522 | printf("Clock enable failed for 0x%p idlest 0x%x\n", |
| 523 | clkctrl_addr, clkctrl); |
| 524 | return; |
| 525 | } |
| 526 | } |
| 527 | } |
| 528 | |
| 529 | static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, |
| 530 | u32 wait_for_enable) |
| 531 | { |
| 532 | clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, |
| 533 | enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 534 | debug("Enable clock module - 0x%08x\n", clkctrl_addr); |
| 535 | if (wait_for_enable) |
| 536 | wait_for_clk_enable(clkctrl_addr); |
| 537 | } |
| 538 | |
| 539 | /* |
| 540 | * Enable essential clock domains, modules and |
| 541 | * do some additional special settings needed |
| 542 | */ |
| 543 | static void enable_basic_clocks(void) |
| 544 | { |
| 545 | u32 i, max = 100, wait_for_enable = 1; |
| 546 | u32 *const clk_domains_essential[] = { |
| 547 | &prcm->cm_l4per_clkstctrl, |
| 548 | &prcm->cm_l3init_clkstctrl, |
| 549 | &prcm->cm_memif_clkstctrl, |
| 550 | &prcm->cm_l4cfg_clkstctrl, |
| 551 | 0 |
| 552 | }; |
| 553 | |
| 554 | u32 *const clk_modules_hw_auto_essential[] = { |
| 555 | &prcm->cm_wkup_gpio1_clkctrl, |
| 556 | &prcm->cm_l4per_gpio2_clkctrl, |
| 557 | &prcm->cm_l4per_gpio3_clkctrl, |
| 558 | &prcm->cm_l4per_gpio4_clkctrl, |
| 559 | &prcm->cm_l4per_gpio5_clkctrl, |
| 560 | &prcm->cm_l4per_gpio6_clkctrl, |
| 561 | &prcm->cm_memif_emif_1_clkctrl, |
| 562 | &prcm->cm_memif_emif_2_clkctrl, |
| 563 | &prcm->cm_l3init_hsusbotg_clkctrl, |
| 564 | &prcm->cm_l3init_usbphy_clkctrl, |
| 565 | &prcm->cm_l4cfg_l4_cfg_clkctrl, |
| 566 | 0 |
| 567 | }; |
| 568 | |
| 569 | u32 *const clk_modules_explicit_en_essential[] = { |
| 570 | &prcm->cm_l4per_gptimer2_clkctrl, |
| 571 | &prcm->cm_l3init_hsmmc1_clkctrl, |
| 572 | &prcm->cm_l3init_hsmmc2_clkctrl, |
| 573 | &prcm->cm_l4per_mcspi1_clkctrl, |
| 574 | &prcm->cm_wkup_gptimer1_clkctrl, |
| 575 | &prcm->cm_l4per_i2c1_clkctrl, |
| 576 | &prcm->cm_l4per_i2c2_clkctrl, |
| 577 | &prcm->cm_l4per_i2c3_clkctrl, |
| 578 | &prcm->cm_l4per_i2c4_clkctrl, |
| 579 | &prcm->cm_wkup_wdtimer2_clkctrl, |
| 580 | &prcm->cm_l4per_uart3_clkctrl, |
| 581 | 0 |
| 582 | }; |
| 583 | |
| 584 | /* Enable optional additional functional clock for GPIO4 */ |
| 585 | setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, |
| 586 | GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
| 587 | |
| 588 | /* Enable 96 MHz clock for MMC1 & MMC2 */ |
| 589 | setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, |
| 590 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 591 | setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, |
| 592 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 593 | |
| 594 | /* Select 32KHz clock as the source of GPTIMER1 */ |
| 595 | setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, |
| 596 | GPTIMER1_CLKCTRL_CLKSEL_MASK); |
| 597 | |
| 598 | /* Enable optional 48M functional clock for USB PHY */ |
| 599 | setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, |
| 600 | USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); |
| 601 | |
| 602 | /* Put the clock domains in SW_WKUP mode */ |
| 603 | for (i = 0; (i < max) && clk_domains_essential[i]; i++) { |
| 604 | enable_clock_domain(clk_domains_essential[i], |
| 605 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
| 606 | } |
| 607 | |
| 608 | /* Clock modules that need to be put in HW_AUTO */ |
| 609 | for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) { |
| 610 | enable_clock_module(clk_modules_hw_auto_essential[i], |
| 611 | MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
| 612 | wait_for_enable); |
| 613 | }; |
| 614 | |
| 615 | /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
| 616 | for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) { |
| 617 | enable_clock_module(clk_modules_explicit_en_essential[i], |
| 618 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
| 619 | wait_for_enable); |
| 620 | }; |
| 621 | |
| 622 | /* Put the clock domains in HW_AUTO mode now */ |
| 623 | for (i = 0; (i < max) && clk_domains_essential[i]; i++) { |
| 624 | enable_clock_domain(clk_domains_essential[i], |
| 625 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | /* |
| 630 | * Enable non-essential clock domains, modules and |
| 631 | * do some additional special settings needed |
| 632 | */ |
| 633 | static void enable_non_essential_clocks(void) |
| 634 | { |
| 635 | u32 i, max = 100, wait_for_enable = 0; |
| 636 | u32 *const clk_domains_non_essential[] = { |
| 637 | &prcm->cm_mpu_m3_clkstctrl, |
| 638 | &prcm->cm_ivahd_clkstctrl, |
| 639 | &prcm->cm_dsp_clkstctrl, |
| 640 | &prcm->cm_dss_clkstctrl, |
| 641 | &prcm->cm_sgx_clkstctrl, |
| 642 | &prcm->cm1_abe_clkstctrl, |
| 643 | &prcm->cm_c2c_clkstctrl, |
| 644 | &prcm->cm_cam_clkstctrl, |
| 645 | &prcm->cm_dss_clkstctrl, |
| 646 | &prcm->cm_sdma_clkstctrl, |
| 647 | 0 |
| 648 | }; |
| 649 | |
| 650 | u32 *const clk_modules_hw_auto_non_essential[] = { |
| 651 | &prcm->cm_mpu_m3_mpu_m3_clkctrl, |
| 652 | &prcm->cm_ivahd_ivahd_clkctrl, |
| 653 | &prcm->cm_ivahd_sl2_clkctrl, |
| 654 | &prcm->cm_dsp_dsp_clkctrl, |
| 655 | &prcm->cm_l3_2_gpmc_clkctrl, |
| 656 | &prcm->cm_l3instr_l3_3_clkctrl, |
| 657 | &prcm->cm_l3instr_l3_instr_clkctrl, |
| 658 | &prcm->cm_l3instr_intrconn_wp1_clkctrl, |
| 659 | &prcm->cm_l3init_hsi_clkctrl, |
| 660 | &prcm->cm_l3init_hsusbtll_clkctrl, |
| 661 | 0 |
| 662 | }; |
| 663 | |
| 664 | u32 *const clk_modules_explicit_en_non_essential[] = { |
| 665 | &prcm->cm1_abe_aess_clkctrl, |
| 666 | &prcm->cm1_abe_pdm_clkctrl, |
| 667 | &prcm->cm1_abe_dmic_clkctrl, |
| 668 | &prcm->cm1_abe_mcasp_clkctrl, |
| 669 | &prcm->cm1_abe_mcbsp1_clkctrl, |
| 670 | &prcm->cm1_abe_mcbsp2_clkctrl, |
| 671 | &prcm->cm1_abe_mcbsp3_clkctrl, |
| 672 | &prcm->cm1_abe_slimbus_clkctrl, |
| 673 | &prcm->cm1_abe_timer5_clkctrl, |
| 674 | &prcm->cm1_abe_timer6_clkctrl, |
| 675 | &prcm->cm1_abe_timer7_clkctrl, |
| 676 | &prcm->cm1_abe_timer8_clkctrl, |
| 677 | &prcm->cm1_abe_wdt3_clkctrl, |
| 678 | &prcm->cm_l4per_gptimer9_clkctrl, |
| 679 | &prcm->cm_l4per_gptimer10_clkctrl, |
| 680 | &prcm->cm_l4per_gptimer11_clkctrl, |
| 681 | &prcm->cm_l4per_gptimer3_clkctrl, |
| 682 | &prcm->cm_l4per_gptimer4_clkctrl, |
| 683 | &prcm->cm_l4per_hdq1w_clkctrl, |
| 684 | &prcm->cm_l4per_mcbsp4_clkctrl, |
| 685 | &prcm->cm_l4per_mcspi2_clkctrl, |
| 686 | &prcm->cm_l4per_mcspi3_clkctrl, |
| 687 | &prcm->cm_l4per_mcspi4_clkctrl, |
| 688 | &prcm->cm_l4per_mmcsd3_clkctrl, |
| 689 | &prcm->cm_l4per_mmcsd4_clkctrl, |
| 690 | &prcm->cm_l4per_mmcsd5_clkctrl, |
| 691 | &prcm->cm_l4per_uart1_clkctrl, |
| 692 | &prcm->cm_l4per_uart2_clkctrl, |
| 693 | &prcm->cm_l4per_uart4_clkctrl, |
| 694 | &prcm->cm_wkup_keyboard_clkctrl, |
| 695 | &prcm->cm_wkup_wdtimer2_clkctrl, |
| 696 | &prcm->cm_cam_iss_clkctrl, |
| 697 | &prcm->cm_cam_fdif_clkctrl, |
| 698 | &prcm->cm_dss_dss_clkctrl, |
| 699 | &prcm->cm_sgx_sgx_clkctrl, |
| 700 | &prcm->cm_l3init_hsusbhost_clkctrl, |
| 701 | &prcm->cm_l3init_fsusb_clkctrl, |
| 702 | 0 |
| 703 | }; |
| 704 | |
| 705 | /* Enable optional functional clock for ISS */ |
| 706 | setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); |
| 707 | |
| 708 | /* Enable all optional functional clocks of DSS */ |
| 709 | setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); |
| 710 | |
| 711 | |
| 712 | /* Put the clock domains in SW_WKUP mode */ |
| 713 | for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { |
| 714 | enable_clock_domain(clk_domains_non_essential[i], |
| 715 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
| 716 | } |
| 717 | |
| 718 | /* Clock modules that need to be put in HW_AUTO */ |
| 719 | for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { |
| 720 | enable_clock_module(clk_modules_hw_auto_non_essential[i], |
| 721 | MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
| 722 | wait_for_enable); |
| 723 | }; |
| 724 | |
| 725 | /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
| 726 | for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; |
| 727 | i++) { |
| 728 | enable_clock_module(clk_modules_explicit_en_non_essential[i], |
| 729 | MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
| 730 | wait_for_enable); |
| 731 | }; |
| 732 | |
| 733 | /* Put the clock domains in HW_AUTO mode now */ |
| 734 | for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { |
| 735 | enable_clock_domain(clk_domains_non_essential[i], |
| 736 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
| 737 | } |
| 738 | |
| 739 | /* Put camera module in no sleep mode */ |
| 740 | clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, |
| 741 | CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << |
| 742 | MODULE_CLKCTRL_MODULEMODE_SHIFT); |
| 743 | } |
| 744 | |
| 745 | |
| 746 | void freq_update_core(void) |
| 747 | { |
| 748 | u32 freq_config1 = 0; |
| 749 | const struct dpll_params *core_dpll_params; |
| 750 | |
| 751 | core_dpll_params = get_core_dpll_params(); |
| 752 | /* Put EMIF clock domain in sw wakeup mode */ |
| 753 | enable_clock_domain(&prcm->cm_memif_clkstctrl, |
| 754 | CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
| 755 | wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); |
| 756 | wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); |
| 757 | |
| 758 | freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | |
| 759 | SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; |
| 760 | |
| 761 | freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & |
| 762 | SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; |
| 763 | |
| 764 | freq_config1 |= (core_dpll_params->m2 << |
| 765 | SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & |
| 766 | SHADOW_FREQ_CONFIG1_M2_DIV_MASK; |
| 767 | |
| 768 | writel(freq_config1, &prcm->cm_shadow_freq_config1); |
| 769 | if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, |
| 770 | &prcm->cm_shadow_freq_config1, LDELAY)) { |
| 771 | puts("FREQ UPDATE procedure failed!!"); |
| 772 | hang(); |
| 773 | } |
| 774 | |
| 775 | /* Put EMIF clock domain back in hw auto mode */ |
| 776 | enable_clock_domain(&prcm->cm_memif_clkstctrl, |
| 777 | CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
| 778 | wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); |
| 779 | wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); |
| 780 | } |
| 781 | |
| 782 | void bypass_dpll(u32 *const base) |
| 783 | { |
| 784 | do_bypass_dpll(base); |
| 785 | wait_for_bypass(base); |
| 786 | } |
| 787 | |
| 788 | void lock_dpll(u32 *const base) |
| 789 | { |
| 790 | do_lock_dpll(base); |
| 791 | wait_for_lock(base); |
| 792 | } |
| 793 | |
| 794 | void prcm_init(void) |
| 795 | { |
| 796 | switch (omap4_hw_init_context()) { |
| 797 | case OMAP_INIT_CONTEXT_SPL: |
| 798 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 799 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 800 | scale_vcores(); |
| 801 | setup_dplls(); |
| 802 | enable_basic_clocks(); |
| 803 | setup_non_essential_dplls(); |
| 804 | enable_non_essential_clocks(); |
| 805 | break; |
| 806 | default: |
| 807 | break; |
| 808 | } |
| 809 | } |