Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | */ |
| 5 | |
Andreas Dannenberg | 7202af9 | 2019-04-29 12:56:44 -0500 | [diff] [blame] | 6 | #include <dt-bindings/pinctrl/k3.h> |
Grygorii Strashko | 736b6c3 | 2019-02-05 17:31:26 +0530 | [diff] [blame] | 7 | #include <dt-bindings/dma/k3-udma.h> |
Grygorii Strashko | 6f2929d | 2019-07-09 10:30:36 +0530 | [diff] [blame] | 8 | #include <dt-bindings/net/ti-dp83867.h> |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 9 | |
| 10 | / { |
| 11 | chosen { |
| 12 | stdout-path = "serial2:115200n8"; |
| 13 | }; |
| 14 | |
| 15 | aliases { |
| 16 | serial2 = &main_uart0; |
Grygorii Strashko | 5195c10 | 2019-07-09 10:30:35 +0530 | [diff] [blame] | 17 | ethernet0 = &cpsw_port1; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 18 | }; |
| 19 | }; |
| 20 | |
| 21 | &cbass_main{ |
| 22 | u-boot,dm-spl; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 23 | |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 24 | main_pmx1: pinmux@11c2e8 { |
| 25 | compatible = "pinctrl-single"; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 26 | reg = <0x0 0x11c2e8 0x0 0x24>; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 27 | #pinctrl-cells = <1>; |
| 28 | pinctrl-single,register-width = <32>; |
| 29 | pinctrl-single,function-mask = <0xffffffff>; |
| 30 | }; |
| 31 | |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 32 | sdhci1: sdhci@04FA0000 { |
Faiz Abbas | 3a1a0df | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 33 | compatible = "ti,am654-sdhci-5.1"; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 34 | reg = <0x0 0x4FA0000 0x0 0x1000>, |
| 35 | <0x0 0x4FB0000 0x0 0x400>; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 36 | clocks = <&k3_clks 48 1>; |
| 37 | power-domains = <&k3_pds 48>; |
| 38 | max-frequency = <25000000>; |
| 39 | }; |
| 40 | |
| 41 | }; |
| 42 | |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 43 | &cbass_mcu { |
| 44 | u-boot,dm-spl; |
| 45 | wkup_pmx0: pinmux@4301c000 { |
| 46 | compatible = "pinctrl-single"; |
| 47 | reg = <0x0 0x4301c000 0x0 0x118>; |
| 48 | #pinctrl-cells = <1>; |
| 49 | pinctrl-single,register-width = <32>; |
| 50 | pinctrl-single,function-mask = <0xffffffff>; |
| 51 | }; |
Grygorii Strashko | 736b6c3 | 2019-02-05 17:31:26 +0530 | [diff] [blame] | 52 | |
| 53 | navss_mcu: navss-mcu { |
| 54 | compatible = "simple-bus"; |
| 55 | #address-cells = <2>; |
| 56 | #size-cells = <2>; |
| 57 | ranges; |
| 58 | |
| 59 | ti,sci-dev-id = <119>; |
| 60 | |
| 61 | mcu_ringacc: ringacc@2b800000 { |
| 62 | compatible = "ti,am654-navss-ringacc"; |
| 63 | reg = <0x0 0x2b800000 0x0 0x400000>, |
| 64 | <0x0 0x2b000000 0x0 0x400000>, |
| 65 | <0x0 0x28590000 0x0 0x100>, |
| 66 | <0x0 0x2a500000 0x0 0x40000>; |
| 67 | reg-names = "rt", "fifos", |
| 68 | "proxy_gcfg", "proxy_target"; |
| 69 | ti,num-rings = <286>; |
| 70 | ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ |
| 71 | ti,dma-ring-reset-quirk; |
| 72 | ti,sci = <&dmsc>; |
| 73 | ti,sci-dev-id = <195>; |
| 74 | }; |
| 75 | |
| 76 | mcu_udmap: udmap@285c0000 { |
| 77 | compatible = "ti,k3-navss-udmap"; |
| 78 | reg = <0x0 0x285c0000 0x0 0x100>, |
| 79 | <0x0 0x2a800000 0x0 0x40000>, |
| 80 | <0x0 0x2aa00000 0x0 0x40000>; |
| 81 | reg-names = "gcfg", "rchanrt", "tchanrt"; |
| 82 | #dma-cells = <3>; |
| 83 | |
| 84 | ti,ringacc = <&mcu_ringacc>; |
| 85 | ti,psil-base = <0x6000>; |
| 86 | |
| 87 | ti,sci = <&dmsc>; |
| 88 | ti,sci-dev-id = <194>; |
| 89 | |
| 90 | ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ |
| 91 | <0x2>; /* TX_CHAN */ |
| 92 | ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ |
| 93 | <0x4>; /* RX_CHAN */ |
| 94 | ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ |
| 95 | dma-coherent; |
| 96 | }; |
| 97 | }; |
Grygorii Strashko | 5195c10 | 2019-07-09 10:30:35 +0530 | [diff] [blame] | 98 | |
| 99 | mcu_conf: scm_conf@40f00000 { |
| 100 | compatible = "syscon"; |
| 101 | reg = <0x0 0x40f00000 0x0 0x20000>; |
| 102 | }; |
| 103 | |
| 104 | mcu_cpsw: cpsw_nuss@046000000 { |
| 105 | compatible = "ti,am654-cpsw-nuss"; |
| 106 | #address-cells = <2>; |
| 107 | #size-cells = <2>; |
| 108 | reg = <0x0 0x46000000 0x0 0x200000>; |
| 109 | reg-names = "cpsw_nuss"; |
| 110 | ranges; |
| 111 | dma-coherent; |
| 112 | clocks = <&k3_clks 5 10>; |
| 113 | clock-names = "fck"; |
| 114 | power-domains = <&k3_pds 5>; |
| 115 | ti,psil-base = <0x7000>; |
| 116 | |
| 117 | dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>, |
| 118 | <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>, |
| 119 | <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>, |
| 120 | <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>, |
| 121 | <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>, |
| 122 | <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>, |
| 123 | <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>, |
| 124 | <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>, |
| 125 | <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>; |
| 126 | dma-names = "tx0", "tx1", "tx2", "tx3", |
| 127 | "tx4", "tx5", "tx6", "tx7", |
| 128 | "rx"; |
| 129 | |
| 130 | ports { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <0>; |
| 133 | host: host@0 { |
| 134 | reg = <0>; |
| 135 | ti,label = "host"; |
| 136 | }; |
| 137 | |
| 138 | cpsw_port1: port@1 { |
| 139 | reg = <1>; |
| 140 | ti,mac-only; |
| 141 | ti,label = "port1"; |
| 142 | ti,syscon-efuse = <&mcu_conf 0x200>; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | davinci_mdio: mdio { |
| 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; |
| 149 | bus_freq = <1000000>; |
| 150 | }; |
| 151 | |
| 152 | ti,psil-config0 { |
| 153 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 154 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 155 | ti,needs-epib; |
| 156 | ti,psd-size = <16>; |
| 157 | }; |
| 158 | |
| 159 | ti,psil-config1 { |
| 160 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 161 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 162 | ti,needs-epib; |
| 163 | ti,psd-size = <16>; |
| 164 | }; |
| 165 | |
| 166 | ti,psil-config2 { |
| 167 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 168 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 169 | ti,needs-epib; |
| 170 | ti,psd-size = <16>; |
| 171 | }; |
| 172 | |
| 173 | ti,psil-config3 { |
| 174 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 175 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 176 | ti,needs-epib; |
| 177 | ti,psd-size = <16>; |
| 178 | }; |
| 179 | |
| 180 | ti,psil-config4 { |
| 181 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 182 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 183 | ti,needs-epib; |
| 184 | ti,psd-size = <16>; |
| 185 | }; |
| 186 | |
| 187 | ti,psil-config5 { |
| 188 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 189 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 190 | ti,needs-epib; |
| 191 | ti,psd-size = <16>; |
| 192 | }; |
| 193 | |
| 194 | ti,psil-config6 { |
| 195 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 196 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 197 | ti,needs-epib; |
| 198 | ti,psd-size = <16>; |
| 199 | }; |
| 200 | |
| 201 | ti,psil-config7 { |
| 202 | linux,udma-mode = <UDMA_PKT_MODE>; |
| 203 | statictr-type = <PSIL_STATIC_TR_NONE>; |
| 204 | ti,needs-epib; |
| 205 | ti,psd-size = <16>; |
| 206 | }; |
| 207 | }; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | &cbass_wakeup { |
| 211 | u-boot,dm-spl; |
| 212 | }; |
| 213 | |
| 214 | &secure_proxy_main { |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 215 | u-boot,dm-spl; |
| 216 | }; |
| 217 | |
| 218 | &dmsc { |
| 219 | u-boot,dm-spl; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 220 | k3_sysreset: sysreset-controller { |
| 221 | compatible = "ti,sci-sysreset"; |
| 222 | u-boot,dm-spl; |
| 223 | }; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 224 | }; |
| 225 | |
| 226 | &k3_pds { |
| 227 | u-boot,dm-spl; |
| 228 | }; |
| 229 | |
| 230 | &k3_clks { |
| 231 | u-boot,dm-spl; |
| 232 | }; |
| 233 | |
| 234 | &k3_reset { |
| 235 | u-boot,dm-spl; |
| 236 | }; |
| 237 | |
| 238 | &main_pmx0 { |
| 239 | u-boot,dm-spl; |
| 240 | main_uart0_pins_default: main_uart0_pins_default { |
| 241 | pinctrl-single,pins = < |
Andreas Dannenberg | 7202af9 | 2019-04-29 12:56:44 -0500 | [diff] [blame] | 242 | AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ |
| 243 | AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ |
| 244 | AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ |
| 245 | AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 246 | >; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 247 | u-boot,dm-spl; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | main_mmc0_pins_default: main_mmc0_pins_default { |
| 251 | pinctrl-single,pins = < |
Andreas Dannenberg | 7202af9 | 2019-04-29 12:56:44 -0500 | [diff] [blame] | 252 | AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ |
| 253 | AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ |
| 254 | AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ |
| 255 | AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ |
| 256 | AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ |
| 257 | AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ |
| 258 | AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ |
| 259 | AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ |
| 260 | AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ |
| 261 | AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ |
Faiz Abbas | 3a1a0df | 2019-06-11 00:43:31 +0530 | [diff] [blame] | 262 | AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ |
| 263 | AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 264 | >; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 265 | u-boot,dm-spl; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | main_mmc1_pins_default: main_mmc1_pins_default { |
| 269 | pinctrl-single,pins = < |
Andreas Dannenberg | 7202af9 | 2019-04-29 12:56:44 -0500 | [diff] [blame] | 270 | AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ |
| 271 | AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ |
| 272 | AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ |
| 273 | AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ |
| 274 | AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ |
| 275 | AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ |
| 276 | AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ |
| 277 | AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 278 | >; |
Lokesh Vutla | 2d0eba3 | 2018-11-02 19:51:08 +0530 | [diff] [blame] | 279 | u-boot,dm-spl; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | }; |
| 283 | |
| 284 | &main_pmx1 { |
| 285 | u-boot,dm-spl; |
| 286 | }; |
| 287 | |
Grygorii Strashko | 6f2929d | 2019-07-09 10:30:36 +0530 | [diff] [blame] | 288 | &wkup_pmx0 { |
| 289 | mcu_cpsw_pins_default: mcu_cpsw_pins_default { |
| 290 | pinctrl-single,pins = < |
| 291 | AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ |
| 292 | AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ |
| 293 | AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ |
| 294 | AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ |
| 295 | AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ |
| 296 | AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ |
| 297 | AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ |
| 298 | AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ |
| 299 | AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ |
| 300 | AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ |
| 301 | AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ |
| 302 | AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ |
| 303 | >; |
| 304 | }; |
| 305 | |
| 306 | mcu_mdio_pins_default: mcu_mdio1_pins_default { |
| 307 | pinctrl-single,pins = < |
| 308 | AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ |
| 309 | AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ |
| 310 | >; |
| 311 | }; |
| 312 | }; |
| 313 | |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 314 | &main_uart0 { |
| 315 | u-boot,dm-spl; |
| 316 | pinctrl-names = "default"; |
| 317 | pinctrl-0 = <&main_uart0_pins_default>; |
| 318 | status = "okay"; |
| 319 | }; |
| 320 | |
| 321 | &sdhci0 { |
| 322 | u-boot,dm-spl; |
Lokesh Vutla | 853f7f5 | 2018-08-27 15:59:09 +0530 | [diff] [blame] | 323 | }; |
| 324 | |
| 325 | &sdhci1 { |
| 326 | u-boot,dm-spl; |
| 327 | status = "okay"; |
| 328 | pinctrl-names = "default"; |
| 329 | pinctrl-0 = <&main_mmc1_pins_default>; |
| 330 | sdhci-caps-mask = <0x7 0x0>; |
| 331 | }; |
Grygorii Strashko | 6f2929d | 2019-07-09 10:30:36 +0530 | [diff] [blame] | 332 | |
| 333 | &mcu_cpsw { |
| 334 | pinctrl-names = "default"; |
| 335 | pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; |
| 336 | }; |
| 337 | |
| 338 | &davinci_mdio { |
| 339 | phy0: ethernet-phy@0 { |
| 340 | reg = <0>; |
| 341 | /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */ |
| 342 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| 343 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| 344 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| 345 | }; |
| 346 | }; |
| 347 | |
| 348 | &cpsw_port1 { |
| 349 | phy-mode = "rgmii-id"; |
| 350 | phy-handle = <&phy0>; |
| 351 | }; |
| 352 | |
| 353 | &mcu_cpsw { |
| 354 | reg = <0x0 0x46000000 0x0 0x200000>, |
| 355 | <0x0 0x40f00200 0x0 0x2>; |
| 356 | reg-names = "cpsw_nuss", "mac_efuse"; |
| 357 | |
| 358 | cpsw-phy-sel@40f04040 { |
| 359 | compatible = "ti,am654-cpsw-phy-sel"; |
| 360 | reg= <0x0 0x40f04040 0x0 0x4>; |
| 361 | reg-names = "gmii-sel"; |
| 362 | }; |
| 363 | }; |