blob: 99d6be634f5fdc49f06332418d02f955738b5a66 [file] [log] [blame]
Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - u-boot.lds.S
3 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04004 * Copyright (c) 2005-2008 Analog Device Inc.
Aubrey Li65458982007-03-20 18:16:24 +08005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040029#include <asm/blackfin.h>
30#undef ALIGN
31
32/* If we don't actually load anything into L1 data, this will avoid
33 * a syntax error. If we do actually load something into L1 data,
34 * we'll get a linker memory load error (which is what we'd want).
35 * This is here in the first place so we can quickly test building
36 * for different CPU's which may lack non-cache L1 data.
37 */
38#ifndef L1_DATA_B_SRAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
Mike Frysinger9171fc82008-03-30 15:46:13 -040040# define L1_DATA_B_SRAM_SIZE 0
41#endif
Aubrey Li65458982007-03-20 18:16:24 +080042
43OUTPUT_ARCH(bfin)
Mike Frysinger9171fc82008-03-30 15:46:13 -040044
45/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
46MEMORY
47{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
Mike Frysinger9171fc82008-03-30 15:46:13 -040049 l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
50 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
51}
52
Aubrey Li65458982007-03-20 18:16:24 +080053SECTIONS
54{
Mike Frysinger9171fc82008-03-30 15:46:13 -040055 .text :
56 {
Mike Frysingerc23bff62008-10-11 20:47:58 -040057 cpu/blackfin/start.o (.text)
58
Mike Frysinger9171fc82008-03-30 15:46:13 -040059#ifdef ENV_IS_EMBEDDED
60 /* WARNING - the following is hand-optimized to fit within
61 * the sector before the environment sector. If it throws
62 * an error during compilation remove an object here to get
63 * it linked after the configuration sector.
64 */
Aubrey Li65458982007-03-20 18:16:24 +080065
Mike Frysinger9171fc82008-03-30 15:46:13 -040066 cpu/blackfin/traps.o (.text)
67 cpu/blackfin/interrupt.o (.text)
68 cpu/blackfin/serial.o (.text)
69 common/dlmalloc.o (.text)
70 lib_generic/crc32.o (.text)
71 lib_generic/zlib.o (.text)
72 board/bf561-ezkit/bf561-ezkit.o (.text)
Aubrey Li65458982007-03-20 18:16:24 +080073
Mike Frysinger9171fc82008-03-30 15:46:13 -040074 . = DEFINED(env_offset) ? env_offset : .;
Jean-Christophe PLAGNIOL-VILLARD0cf4fd32008-09-10 22:48:01 +020075 common/env_embedded.o (.text)
Mike Frysinger9171fc82008-03-30 15:46:13 -040076#endif
Aubrey Li65458982007-03-20 18:16:24 +080077
Mike Frysingerc23bff62008-10-11 20:47:58 -040078 __initcode_start = .;
79 cpu/blackfin/initcode.o (.text)
80 __initcode_end = .;
81
Mike Frysinger9171fc82008-03-30 15:46:13 -040082 *(.text .text.*)
83 } >ram
Aubrey Li65458982007-03-20 18:16:24 +080084
Mike Frysinger9171fc82008-03-30 15:46:13 -040085 .rodata :
86 {
87 . = ALIGN(4);
88 *(.rodata .rodata.*)
89 *(.rodata1)
90 *(.eh_frame)
91 . = ALIGN(4);
92 } >ram
Aubrey Li65458982007-03-20 18:16:24 +080093
Mike Frysinger9171fc82008-03-30 15:46:13 -040094 .data :
95 {
96 . = ALIGN(256);
97 *(.data .data.*)
98 *(.data1)
99 *(.sdata)
100 *(.sdata2)
101 *(.dynamic)
102 CONSTRUCTORS
103 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800104
Mike Frysinger9171fc82008-03-30 15:46:13 -0400105 .u_boot_cmd :
106 {
107 ___u_boot_cmd_start = .;
108 *(.u_boot_cmd)
109 ___u_boot_cmd_end = .;
110 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800111
Mike Frysinger9171fc82008-03-30 15:46:13 -0400112 .text_l1 :
113 {
114 . = ALIGN(4);
115 __stext_l1 = .;
116 *(.l1.text)
117 . = ALIGN(4);
118 __etext_l1 = .;
119 } >l1_code AT>ram
120 __stext_l1_lma = LOADADDR(.text_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800121
Mike Frysinger9171fc82008-03-30 15:46:13 -0400122 .data_l1 :
123 {
124 . = ALIGN(4);
125 __sdata_l1 = .;
126 *(.l1.data)
127 *(.l1.bss)
128 . = ALIGN(4);
129 __edata_l1 = .;
130 } >l1_data AT>ram
131 __sdata_l1_lma = LOADADDR(.data_l1);
Aubrey Li65458982007-03-20 18:16:24 +0800132
Mike Frysinger9171fc82008-03-30 15:46:13 -0400133 .bss :
134 {
135 . = ALIGN(4);
136 __bss_start = .;
137 *(.sbss) *(.scommon)
138 *(.dynbss)
139 *(.bss .bss.*)
140 *(COMMON)
141 __bss_end = .;
142 } >ram
Aubrey Li65458982007-03-20 18:16:24 +0800143}