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Kumar Gala3b558e22008-01-17 02:02:10 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020031 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
32 MAS3_SX | MAS3_SW | MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
35 CFG_INIT_RAM_ADDR + 4 * 1024,
36 MAS3_SX | MAS3_SW | MAS3_SR, 0,
37 0, 0, BOOKE_PAGESZ_4K, 0),
38 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
39 CFG_INIT_RAM_ADDR + 8 * 1024,
40 MAS3_SX | MAS3_SW | MAS3_SR, 0,
41 0, 0, BOOKE_PAGESZ_4K, 0),
42 SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
43 CFG_INIT_RAM_ADDR + 12 * 1024,
44 MAS3_SX | MAS3_SW | MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
Kumar Gala3b558e22008-01-17 02:02:10 -060046
47 /*
48 * TLB 0, 1: 128M Non-cacheable, guarded
49 * 0xf8000000 128M FLASH
50 * Out of reset this entry is only 4K.
51 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020052 SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
53 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
54 0, 1, BOOKE_PAGESZ_64M, 1),
55 SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
56 CFG_FLASH_BASE + 0x4000000,
57 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
58 0, 0, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060059
60 /*
61 * TLB 2: 256M Non-cacheable, guarded
62 * 0x80000000 256M PCI1 MEM First half
63 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020064 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
65 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
66 0, 2, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060067
68 /*
69 * TLB 3: 256M Non-cacheable, guarded
70 * 0x90000000 256M PCI1 MEM Second half
71 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020072 SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
73 CFG_PCI1_MEM_PHYS + 0x10000000,
74 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
75 0, 3, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060076
77 /*
78 * TLB 4: 256M Non-cacheable, guarded
79 * 0xc0000000 256M Rapid IO MEM First half
80 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020081 SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
82 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
83 0, 4, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060084
85 /*
86 * TLB 5: 256M Non-cacheable, guarded
87 * 0xd0000000 256M Rapid IO MEM Second half
88 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020089 SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
90 CFG_RIO_MEM_BASE + 0x10000000,
91 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
92 0, 5, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060093
94 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020095 * TLB 6: 64M Non-cacheable, guarded
96 * 0xe0000000 1M CCSRBAR
97 * 0xe2000000 16M PCI1 IO
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +020098 * 0xe3000000 16M CAN
Kumar Gala3b558e22008-01-17 02:02:10 -060099 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200100 SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
101 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
102 0, 6, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600103
104 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200105 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
106 * 0x00000000 512M DDR System memory
Kumar Gala3b558e22008-01-17 02:02:10 -0600107 * Without SPD EEPROM configured DDR, this must be setup manually.
108 * Make sure the TLB count at the top of this table is correct.
109 * Likely it needs to be increased by two for these entries.
110 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200111 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
112 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
113 0, 7, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600114
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200115 SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
116 CFG_DDR_SDRAM_BASE + 0x10000000,
117 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
118 0, 8, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600119};
120
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200121int num_tlb_entries = ARRAY_SIZE (tlb_table);