blob: 22040c67a8440e77fb169dbab38a3c2050df8803 [file] [log] [blame]
Yangbo Lufa33d202019-06-21 11:42:27 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13#include <config.h>
14#include <common.h>
15#include <command.h>
16#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070017#include <cpu_func.h>
Yangbo Lufa33d202019-06-21 11:42:27 +080018#include <errno.h>
19#include <hwconfig.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060020#include <log.h>
Yangbo Lufa33d202019-06-21 11:42:27 +080021#include <mmc.h>
22#include <part.h>
Simon Glass90526e92020-05-10 11:39:56 -060023#include <asm/cache.h>
Simon Glass336d4612020-02-03 07:36:16 -070024#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060025#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060026#include <linux/delay.h>
Simon Glass61b29b82020-02-03 07:36:15 -070027#include <linux/err.h>
Yangbo Lufa33d202019-06-21 11:42:27 +080028#include <power/regulator.h>
29#include <malloc.h>
30#include <fsl_esdhc_imx.h>
31#include <fdt_support.h>
32#include <asm/io.h>
33#include <dm.h>
34#include <asm-generic/gpio.h>
35#include <dm/pinctrl.h>
Walter Lozano23721772020-07-29 12:31:17 -030036#include <dt-structs.h>
37#include <mapmem.h>
38#include <dm/ofnode.h>
Haibo Chenf9c3a812020-09-01 15:34:06 +080039#include <linux/iopoll.h>
Yangbo Lufa33d202019-06-21 11:42:27 +080040
41#if !CONFIG_IS_ENABLED(BLK)
42#include "mmc_private.h"
43#endif
44
45DECLARE_GLOBAL_DATA_PTR;
46
47#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
48 IRQSTATEN_CINT | \
49 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
50 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
51 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
52 IRQSTATEN_DINT)
53#define MAX_TUNING_LOOP 40
54#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
55
56struct fsl_esdhc {
57 uint dsaddr; /* SDMA system address register */
58 uint blkattr; /* Block attributes register */
59 uint cmdarg; /* Command argument register */
60 uint xfertyp; /* Transfer type register */
61 uint cmdrsp0; /* Command response 0 register */
62 uint cmdrsp1; /* Command response 1 register */
63 uint cmdrsp2; /* Command response 2 register */
64 uint cmdrsp3; /* Command response 3 register */
65 uint datport; /* Buffer data port register */
66 uint prsstat; /* Present state register */
67 uint proctl; /* Protocol control register */
68 uint sysctl; /* System Control Register */
69 uint irqstat; /* Interrupt status register */
70 uint irqstaten; /* Interrupt status enable register */
71 uint irqsigen; /* Interrupt signal enable register */
72 uint autoc12err; /* Auto CMD error status register */
73 uint hostcapblt; /* Host controller capabilities register */
74 uint wml; /* Watermark level register */
75 uint mixctrl; /* For USDHC */
76 char reserved1[4]; /* reserved */
77 uint fevt; /* Force event register */
78 uint admaes; /* ADMA error status register */
79 uint adsaddr; /* ADMA system address register */
80 char reserved2[4];
81 uint dllctrl;
82 uint dllstat;
83 uint clktunectrlstatus;
84 char reserved3[4];
85 uint strobe_dllctrl;
86 uint strobe_dllstat;
87 char reserved4[72];
88 uint vendorspec;
89 uint mmcboot;
90 uint vendorspec2;
Giulio Benetti6a63a872020-01-10 15:51:46 +010091 uint tuning_ctrl; /* on i.MX6/7/8/RT */
Yangbo Lufa33d202019-06-21 11:42:27 +080092 char reserved5[44];
93 uint hostver; /* Host controller version register */
94 char reserved6[4]; /* reserved */
95 uint dmaerraddr; /* DMA error address register */
96 char reserved7[4]; /* reserved */
97 uint dmaerrattr; /* DMA error attribute register */
98 char reserved8[4]; /* reserved */
99 uint hostcapblt2; /* Host controller capabilities register 2 */
100 char reserved9[8]; /* reserved */
101 uint tcr; /* Tuning control register */
102 char reserved10[28]; /* reserved */
103 uint sddirctl; /* SD direction control register */
104 char reserved11[712];/* reserved */
105 uint scr; /* eSDHC control register */
106};
107
108struct fsl_esdhc_plat {
Walter Lozano23721772020-07-29 12:31:17 -0300109#if CONFIG_IS_ENABLED(OF_PLATDATA)
110 /* Put this first since driver model will copy the data here */
111 struct dtd_fsl_esdhc dtplat;
112#endif
113
Yangbo Lufa33d202019-06-21 11:42:27 +0800114 struct mmc_config cfg;
115 struct mmc mmc;
116};
117
118struct esdhc_soc_data {
119 u32 flags;
Yangbo Lufa33d202019-06-21 11:42:27 +0800120};
121
122/**
123 * struct fsl_esdhc_priv
124 *
125 * @esdhc_regs: registers of the sdhc controller
126 * @sdhc_clk: Current clk of the sdhc controller
127 * @bus_width: bus width, 1bit, 4bit or 8bit
128 * @cfg: mmc config
129 * @mmc: mmc
130 * Following is used when Driver Model is enabled for MMC
131 * @dev: pointer for the device
132 * @non_removable: 0: removable; 1: non-removable
Fabio Estevam29230f32020-01-06 20:11:27 -0300133 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
Yangbo Lufa33d202019-06-21 11:42:27 +0800134 * @wp_enable: 1: enable checking wp; 0: no check
135 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
136 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
137 * @caps: controller capabilities
138 * @tuning_step: tuning step setting in tuning_ctrl register
139 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
140 * @strobe_dll_delay_target: settings in strobe_dllctrl
141 * @signal_voltage: indicating the current voltage
142 * @cd_gpio: gpio for card detection
143 * @wp_gpio: gpio for write protection
144 */
145struct fsl_esdhc_priv {
146 struct fsl_esdhc *esdhc_regs;
147 unsigned int sdhc_clk;
148 struct clk per_clk;
149 unsigned int clock;
150 unsigned int mode;
151 unsigned int bus_width;
152#if !CONFIG_IS_ENABLED(BLK)
153 struct mmc *mmc;
154#endif
155 struct udevice *dev;
156 int non_removable;
Fabio Estevam29230f32020-01-06 20:11:27 -0300157 int broken_cd;
Yangbo Lufa33d202019-06-21 11:42:27 +0800158 int wp_enable;
159 int vs18_enable;
160 u32 flags;
161 u32 caps;
162 u32 tuning_step;
163 u32 tuning_start_tap;
164 u32 strobe_dll_delay_target;
165 u32 signal_voltage;
Ye Li82771712019-07-11 03:29:02 +0000166#if CONFIG_IS_ENABLED(DM_REGULATOR)
Yangbo Lufa33d202019-06-21 11:42:27 +0800167 struct udevice *vqmmc_dev;
168 struct udevice *vmmc_dev;
169#endif
Simon Glassbcee8d62019-12-06 21:41:35 -0700170#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lufa33d202019-06-21 11:42:27 +0800171 struct gpio_desc cd_gpio;
172 struct gpio_desc wp_gpio;
173#endif
174};
175
176/* Return the XFERTYP flags for a given command and data packet */
177static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
178{
179 uint xfertyp = 0;
180
181 if (data) {
182 xfertyp |= XFERTYP_DPSEL;
183#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
184 xfertyp |= XFERTYP_DMAEN;
185#endif
186 if (data->blocks > 1) {
187 xfertyp |= XFERTYP_MSBSEL;
188 xfertyp |= XFERTYP_BCEN;
189#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
190 xfertyp |= XFERTYP_AC12EN;
191#endif
192 }
193
194 if (data->flags & MMC_DATA_READ)
195 xfertyp |= XFERTYP_DTDSEL;
196 }
197
198 if (cmd->resp_type & MMC_RSP_CRC)
199 xfertyp |= XFERTYP_CCCEN;
200 if (cmd->resp_type & MMC_RSP_OPCODE)
201 xfertyp |= XFERTYP_CICEN;
202 if (cmd->resp_type & MMC_RSP_136)
203 xfertyp |= XFERTYP_RSPTYP_136;
204 else if (cmd->resp_type & MMC_RSP_BUSY)
205 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
206 else if (cmd->resp_type & MMC_RSP_PRESENT)
207 xfertyp |= XFERTYP_RSPTYP_48;
208
209 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
210 xfertyp |= XFERTYP_CMDTYP_ABORT;
211
212 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
213}
214
215#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
216/*
217 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
218 */
219static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
220 struct mmc_data *data)
221{
222 struct fsl_esdhc *regs = priv->esdhc_regs;
223 uint blocks;
224 char *buffer;
225 uint databuf;
226 uint size;
227 uint irqstat;
228 ulong start;
229
230 if (data->flags & MMC_DATA_READ) {
231 blocks = data->blocks;
232 buffer = data->dest;
233 while (blocks) {
234 start = get_timer(0);
235 size = data->blocksize;
236 irqstat = esdhc_read32(&regs->irqstat);
237 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
238 if (get_timer(start) > PIO_TIMEOUT) {
239 printf("\nData Read Failed in PIO Mode.");
240 return;
241 }
242 }
243 while (size && (!(irqstat & IRQSTAT_TC))) {
244 udelay(100); /* Wait before last byte transfer complete */
245 irqstat = esdhc_read32(&regs->irqstat);
246 databuf = in_le32(&regs->datport);
247 *((uint *)buffer) = databuf;
248 buffer += 4;
249 size -= 4;
250 }
251 blocks--;
252 }
253 } else {
254 blocks = data->blocks;
255 buffer = (char *)data->src;
256 while (blocks) {
257 start = get_timer(0);
258 size = data->blocksize;
259 irqstat = esdhc_read32(&regs->irqstat);
260 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
261 if (get_timer(start) > PIO_TIMEOUT) {
262 printf("\nData Write Failed in PIO Mode.");
263 return;
264 }
265 }
266 while (size && (!(irqstat & IRQSTAT_TC))) {
267 udelay(100); /* Wait before last byte transfer complete */
268 databuf = *((uint *)buffer);
269 buffer += 4;
270 size -= 4;
271 irqstat = esdhc_read32(&regs->irqstat);
272 out_le32(&regs->datport, databuf);
273 }
274 blocks--;
275 }
276 }
277}
278#endif
279
280static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
281 struct mmc_data *data)
282{
283 int timeout;
284 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu5053da22019-06-21 11:42:30 +0800285#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lufa33d202019-06-21 11:42:27 +0800286 dma_addr_t addr;
287#endif
288 uint wml_value;
289
290 wml_value = data->blocksize/4;
291
292 if (data->flags & MMC_DATA_READ) {
293 if (wml_value > WML_RD_WML_MAX)
294 wml_value = WML_RD_WML_MAX_VAL;
295
296 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
297#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Yangbo Lu5053da22019-06-21 11:42:30 +0800298#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lufa33d202019-06-21 11:42:27 +0800299 addr = virt_to_phys((void *)(data->dest));
300 if (upper_32_bits(addr))
301 printf("Error found for upper 32 bits\n");
302 else
303 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
304#else
305 esdhc_write32(&regs->dsaddr, (u32)data->dest);
306#endif
307#endif
308 } else {
309#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
310 flush_dcache_range((ulong)data->src,
311 (ulong)data->src+data->blocks
312 *data->blocksize);
313#endif
314 if (wml_value > WML_WR_WML_MAX)
315 wml_value = WML_WR_WML_MAX_VAL;
316 if (priv->wp_enable) {
317 if ((esdhc_read32(&regs->prsstat) &
318 PRSSTAT_WPSPL) == 0) {
319 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
320 return -ETIMEDOUT;
321 }
322 } else {
Simon Glassbcee8d62019-12-06 21:41:35 -0700323#if CONFIG_IS_ENABLED(DM_GPIO)
324 if (dm_gpio_is_valid(&priv->wp_gpio) &&
325 dm_gpio_get_value(&priv->wp_gpio)) {
Yangbo Lufa33d202019-06-21 11:42:27 +0800326 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
327 return -ETIMEDOUT;
328 }
329#endif
330 }
331
332 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
333 wml_value << 16);
334#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Yangbo Lu5053da22019-06-21 11:42:30 +0800335#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lufa33d202019-06-21 11:42:27 +0800336 addr = virt_to_phys((void *)(data->src));
337 if (upper_32_bits(addr))
338 printf("Error found for upper 32 bits\n");
339 else
340 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
341#else
342 esdhc_write32(&regs->dsaddr, (u32)data->src);
343#endif
344#endif
345 }
346
347 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
348
349 /* Calculate the timeout period for data transactions */
350 /*
351 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
352 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
353 * So, Number of SD Clock cycles for 0.25sec should be minimum
354 * (SD Clock/sec * 0.25 sec) SD Clock cycles
355 * = (mmc->clock * 1/4) SD Clock cycles
356 * As 1) >= 2)
357 * => (2^(timeout+13)) >= mmc->clock * 1/4
358 * Taking log2 both the sides
359 * => timeout + 13 >= log2(mmc->clock/4)
360 * Rounding up to next power of 2
361 * => timeout + 13 = log2(mmc->clock/4) + 1
362 * => timeout + 13 = fls(mmc->clock/4)
363 *
364 * However, the MMC spec "It is strongly recommended for hosts to
365 * implement more than 500ms timeout value even if the card
366 * indicates the 250ms maximum busy length." Even the previous
367 * value of 300ms is known to be insufficient for some cards.
368 * So, we use
369 * => timeout + 13 = fls(mmc->clock/2)
370 */
371 timeout = fls(mmc->clock/2);
372 timeout -= 13;
373
374 if (timeout > 14)
375 timeout = 14;
376
377 if (timeout < 0)
378 timeout = 0;
379
380#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
381 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
382 timeout++;
383#endif
384
385#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
386 timeout = 0xE;
387#endif
388 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
389
390 return 0;
391}
392
393static void check_and_invalidate_dcache_range
394 (struct mmc_cmd *cmd,
395 struct mmc_data *data) {
396 unsigned start = 0;
397 unsigned end = 0;
398 unsigned size = roundup(ARCH_DMA_MINALIGN,
399 data->blocks*data->blocksize);
Yangbo Lu5053da22019-06-21 11:42:30 +0800400#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lufa33d202019-06-21 11:42:27 +0800401 dma_addr_t addr;
402
403 addr = virt_to_phys((void *)(data->dest));
404 if (upper_32_bits(addr))
405 printf("Error found for upper 32 bits\n");
406 else
407 start = lower_32_bits(addr);
408#else
409 start = (unsigned)data->dest;
410#endif
411 end = start + size;
412 invalidate_dcache_range(start, end);
413}
414
415#ifdef CONFIG_MCF5441x
416/*
417 * Swaps 32-bit words to little-endian byte order.
418 */
419static inline void sd_swap_dma_buff(struct mmc_data *data)
420{
421 int i, size = data->blocksize >> 2;
422 u32 *buffer = (u32 *)data->dest;
423 u32 sw;
424
425 while (data->blocks--) {
426 for (i = 0; i < size; i++) {
427 sw = __sw32(*buffer);
428 *buffer++ = sw;
429 }
430 }
431}
432#endif
433
434/*
435 * Sends a command out on the bus. Takes the mmc pointer,
436 * a command pointer, and an optional data pointer.
437 */
438static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
439 struct mmc_cmd *cmd, struct mmc_data *data)
440{
441 int err = 0;
442 uint xfertyp;
443 uint irqstat;
444 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
445 struct fsl_esdhc *regs = priv->esdhc_regs;
446 unsigned long start;
447
448#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
449 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
450 return 0;
451#endif
452
453 esdhc_write32(&regs->irqstat, -1);
454
455 sync();
456
457 /* Wait for the bus to be idle */
458 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
459 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
460 ;
461
462 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
463 ;
464
Yangbo Lufa33d202019-06-21 11:42:27 +0800465 /* Set up for a data transfer if we have one */
466 if (data) {
467 err = esdhc_setup_data(priv, mmc, data);
468 if(err)
469 return err;
470
471 if (data->flags & MMC_DATA_READ)
472 check_and_invalidate_dcache_range(cmd, data);
473 }
474
475 /* Figure out the transfer arguments */
476 xfertyp = esdhc_xfertyp(cmd, data);
477
478 /* Mask all irqs */
479 esdhc_write32(&regs->irqsigen, 0);
480
481 /* Send the command */
482 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
483#if defined(CONFIG_FSL_USDHC)
484 esdhc_write32(&regs->mixctrl,
485 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
486 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
487 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
488#else
489 esdhc_write32(&regs->xfertyp, xfertyp);
490#endif
491
492 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
493 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
494 flags = IRQSTAT_BRR;
495
496 /* Wait for the command to complete */
497 start = get_timer(0);
498 while (!(esdhc_read32(&regs->irqstat) & flags)) {
499 if (get_timer(start) > 1000) {
500 err = -ETIMEDOUT;
501 goto out;
502 }
503 }
504
505 irqstat = esdhc_read32(&regs->irqstat);
506
507 if (irqstat & CMD_ERR) {
508 err = -ECOMM;
509 goto out;
510 }
511
512 if (irqstat & IRQSTAT_CTOE) {
513 err = -ETIMEDOUT;
514 goto out;
515 }
516
517 /* Switch voltage to 1.8V if CMD11 succeeded */
518 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
519 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
520
521 printf("Run CMD11 1.8V switch\n");
522 /* Sleep for 5 ms - max time for card to switch to 1.8V */
523 udelay(5000);
524 }
525
526 /* Workaround for ESDHC errata ENGcm03648 */
527 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Peng Fan356f7822019-07-10 09:35:30 +0000528 int timeout = 50000;
Yangbo Lufa33d202019-06-21 11:42:27 +0800529
Peng Fan356f7822019-07-10 09:35:30 +0000530 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
Yangbo Lufa33d202019-06-21 11:42:27 +0800531 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
532 PRSSTAT_DAT0)) {
533 udelay(100);
534 timeout--;
535 }
536
537 if (timeout <= 0) {
538 printf("Timeout waiting for DAT0 to go high!\n");
539 err = -ETIMEDOUT;
540 goto out;
541 }
542 }
543
544 /* Copy the response to the response buffer */
545 if (cmd->resp_type & MMC_RSP_136) {
546 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
547
548 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
549 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
550 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
551 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
552 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
553 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
554 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
555 cmd->response[3] = (cmdrsp0 << 8);
556 } else
557 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
558
559 /* Wait until all of the blocks are transferred */
560 if (data) {
561#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
562 esdhc_pio_read_write(priv, data);
563#else
564 flags = DATA_COMPLETE;
565 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
566 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
567 flags = IRQSTAT_BRR;
568 }
569
570 do {
571 irqstat = esdhc_read32(&regs->irqstat);
572
573 if (irqstat & IRQSTAT_DTOE) {
574 err = -ETIMEDOUT;
575 goto out;
576 }
577
578 if (irqstat & DATA_ERR) {
579 err = -ECOMM;
580 goto out;
581 }
582 } while ((irqstat & flags) != flags);
583
584 /*
585 * Need invalidate the dcache here again to avoid any
586 * cache-fill during the DMA operations such as the
587 * speculative pre-fetching etc.
588 */
589 if (data->flags & MMC_DATA_READ) {
590 check_and_invalidate_dcache_range(cmd, data);
591#ifdef CONFIG_MCF5441x
592 sd_swap_dma_buff(data);
593#endif
594 }
595#endif
596 }
597
598out:
599 /* Reset CMD and DATA portions on error */
600 if (err) {
601 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
602 SYSCTL_RSTC);
603 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
604 ;
605
606 if (data) {
607 esdhc_write32(&regs->sysctl,
608 esdhc_read32(&regs->sysctl) |
609 SYSCTL_RSTD);
610 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
611 ;
612 }
613
614 /* If this was CMD11, then notify that power cycle is needed */
615 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
616 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
617 }
618
619 esdhc_write32(&regs->irqstat, -1);
620
621 return err;
622}
623
624static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
625{
626 struct fsl_esdhc *regs = priv->esdhc_regs;
627 int div = 1;
Haibo Chenf9c3a812020-09-01 15:34:06 +0800628 u32 tmp;
629 int ret;
Yangbo Lufa33d202019-06-21 11:42:27 +0800630#ifdef ARCH_MXC
631#ifdef CONFIG_MX53
632 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
633 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
634#else
635 int pre_div = 1;
636#endif
637#else
638 int pre_div = 2;
639#endif
640 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
641 int sdhc_clk = priv->sdhc_clk;
642 uint clk;
643
Yangbo Lufa33d202019-06-21 11:42:27 +0800644 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
645 pre_div *= 2;
646
647 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
648 div++;
649
650 pre_div >>= 1;
651 div -= 1;
652
653 clk = (pre_div << 8) | (div << 4);
654
655#ifdef CONFIG_FSL_USDHC
656 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
657#else
658 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
659#endif
660
661 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
662
Haibo Chenf9c3a812020-09-01 15:34:06 +0800663 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
664 if (ret)
665 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
Yangbo Lufa33d202019-06-21 11:42:27 +0800666
667#ifdef CONFIG_FSL_USDHC
668 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
669#else
670 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
671#endif
672
673 priv->clock = clock;
674}
675
Yangbo Lufa33d202019-06-21 11:42:27 +0800676#ifdef MMC_SUPPORTS_TUNING
677static int esdhc_change_pinstate(struct udevice *dev)
678{
679 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
680 int ret;
681
682 switch (priv->mode) {
683 case UHS_SDR50:
684 case UHS_DDR50:
685 ret = pinctrl_select_state(dev, "state_100mhz");
686 break;
687 case UHS_SDR104:
688 case MMC_HS_200:
689 case MMC_HS_400:
Peng Fane9c22552019-07-10 09:35:26 +0000690 case MMC_HS_400_ES:
Yangbo Lufa33d202019-06-21 11:42:27 +0800691 ret = pinctrl_select_state(dev, "state_200mhz");
692 break;
693 default:
694 ret = pinctrl_select_state(dev, "default");
695 break;
696 }
697
698 if (ret)
699 printf("%s %d error\n", __func__, priv->mode);
700
701 return ret;
702}
703
704static void esdhc_reset_tuning(struct mmc *mmc)
705{
706 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
707 struct fsl_esdhc *regs = priv->esdhc_regs;
708
709 if (priv->flags & ESDHC_FLAG_USDHC) {
710 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
711 esdhc_clrbits32(&regs->autoc12err,
712 MIX_CTRL_SMPCLK_SEL |
713 MIX_CTRL_EXE_TUNE);
714 }
715 }
716}
717
718static void esdhc_set_strobe_dll(struct mmc *mmc)
719{
720 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
721 struct fsl_esdhc *regs = priv->esdhc_regs;
722 u32 val;
723
724 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
Haibo Chenc7f44182020-09-30 15:52:23 +0800725 esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
Yangbo Lufa33d202019-06-21 11:42:27 +0800726
727 /*
728 * enable strobe dll ctrl and adjust the delay target
729 * for the uSDHC loopback read clock
730 */
731 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
732 (priv->strobe_dll_delay_target <<
733 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
Haibo Chenc7f44182020-09-30 15:52:23 +0800734 esdhc_write32(&regs->strobe_dllctrl, val);
Yangbo Lufa33d202019-06-21 11:42:27 +0800735 /* wait 1us to make sure strobe dll status register stable */
736 mdelay(1);
Haibo Chenc7f44182020-09-30 15:52:23 +0800737 val = esdhc_read32(&regs->strobe_dllstat);
Yangbo Lufa33d202019-06-21 11:42:27 +0800738 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
739 pr_warn("HS400 strobe DLL status REF not lock!\n");
740 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
741 pr_warn("HS400 strobe DLL status SLV not lock!\n");
742 }
743}
744
745static int esdhc_set_timing(struct mmc *mmc)
746{
747 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
748 struct fsl_esdhc *regs = priv->esdhc_regs;
749 u32 mixctrl;
750
Haibo Chenc7f44182020-09-30 15:52:23 +0800751 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800752 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
753
754 switch (mmc->selected_mode) {
755 case MMC_LEGACY:
Yangbo Lufa33d202019-06-21 11:42:27 +0800756 esdhc_reset_tuning(mmc);
Haibo Chenc7f44182020-09-30 15:52:23 +0800757 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800758 break;
759 case MMC_HS_400:
Peng Fane9c22552019-07-10 09:35:26 +0000760 case MMC_HS_400_ES:
Yangbo Lufa33d202019-06-21 11:42:27 +0800761 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
Haibo Chenc7f44182020-09-30 15:52:23 +0800762 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800763 esdhc_set_strobe_dll(mmc);
764 break;
765 case MMC_HS:
766 case MMC_HS_52:
767 case MMC_HS_200:
768 case SD_HS:
769 case UHS_SDR12:
770 case UHS_SDR25:
771 case UHS_SDR50:
772 case UHS_SDR104:
Haibo Chenc7f44182020-09-30 15:52:23 +0800773 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800774 break;
775 case UHS_DDR50:
776 case MMC_DDR_52:
777 mixctrl |= MIX_CTRL_DDREN;
Haibo Chenc7f44182020-09-30 15:52:23 +0800778 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800779 break;
780 default:
781 printf("Not supported %d\n", mmc->selected_mode);
782 return -EINVAL;
783 }
784
785 priv->mode = mmc->selected_mode;
786
787 return esdhc_change_pinstate(mmc->dev);
788}
789
790static int esdhc_set_voltage(struct mmc *mmc)
791{
792 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
793 struct fsl_esdhc *regs = priv->esdhc_regs;
794 int ret;
795
796 priv->signal_voltage = mmc->signal_voltage;
797 switch (mmc->signal_voltage) {
798 case MMC_SIGNAL_VOLTAGE_330:
799 if (priv->vs18_enable)
Marek Vasut50a17a62020-05-22 18:28:33 +0200800 return -ENOTSUPP;
Yangbo Lufa33d202019-06-21 11:42:27 +0800801#if CONFIG_IS_ENABLED(DM_REGULATOR)
802 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
803 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
804 if (ret) {
805 printf("Setting to 3.3V error");
806 return -EIO;
807 }
808 /* Wait for 5ms */
809 mdelay(5);
810 }
811#endif
812
813 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
814 if (!(esdhc_read32(&regs->vendorspec) &
815 ESDHC_VENDORSPEC_VSELECT))
816 return 0;
817
818 return -EAGAIN;
819 case MMC_SIGNAL_VOLTAGE_180:
820#if CONFIG_IS_ENABLED(DM_REGULATOR)
821 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
822 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
823 if (ret) {
824 printf("Setting to 1.8V error");
825 return -EIO;
826 }
827 }
828#endif
829 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
830 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
831 return 0;
832
833 return -EAGAIN;
834 case MMC_SIGNAL_VOLTAGE_120:
835 return -ENOTSUPP;
836 default:
837 return 0;
838 }
839}
840
841static void esdhc_stop_tuning(struct mmc *mmc)
842{
843 struct mmc_cmd cmd;
844
845 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
846 cmd.cmdarg = 0;
847 cmd.resp_type = MMC_RSP_R1b;
848
849 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
850}
851
852static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
853{
854 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
855 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
856 struct fsl_esdhc *regs = priv->esdhc_regs;
857 struct mmc *mmc = &plat->mmc;
Haibo Chenc7f44182020-09-30 15:52:23 +0800858 u32 irqstaten = esdhc_read32(&regs->irqstaten);
859 u32 irqsigen = esdhc_read32(&regs->irqsigen);
Yangbo Lufa33d202019-06-21 11:42:27 +0800860 int i, ret = -ETIMEDOUT;
861 u32 val, mixctrl;
862
863 /* clock tuning is not needed for upto 52MHz */
864 if (mmc->clock <= 52000000)
865 return 0;
866
867 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
868 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chenc7f44182020-09-30 15:52:23 +0800869 val = esdhc_read32(&regs->autoc12err);
870 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800871 val &= ~MIX_CTRL_SMPCLK_SEL;
872 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
873
874 val |= MIX_CTRL_EXE_TUNE;
875 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
876
Haibo Chenc7f44182020-09-30 15:52:23 +0800877 esdhc_write32(&regs->autoc12err, val);
878 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800879 }
880
881 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
Haibo Chenc7f44182020-09-30 15:52:23 +0800882 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800883 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
Haibo Chenc7f44182020-09-30 15:52:23 +0800884 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800885
Haibo Chenc7f44182020-09-30 15:52:23 +0800886 esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
887 esdhc_write32(&regs->irqsigen, IRQSTATEN_BRR);
Yangbo Lufa33d202019-06-21 11:42:27 +0800888
889 /*
890 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
891 * of loops reaches 40 times.
892 */
893 for (i = 0; i < MAX_TUNING_LOOP; i++) {
894 u32 ctrl;
895
896 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
897 if (mmc->bus_width == 8)
Haibo Chenc7f44182020-09-30 15:52:23 +0800898 esdhc_write32(&regs->blkattr, 0x7080);
Yangbo Lufa33d202019-06-21 11:42:27 +0800899 else if (mmc->bus_width == 4)
Haibo Chenc7f44182020-09-30 15:52:23 +0800900 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lufa33d202019-06-21 11:42:27 +0800901 } else {
Haibo Chenc7f44182020-09-30 15:52:23 +0800902 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lufa33d202019-06-21 11:42:27 +0800903 }
904
905 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
Haibo Chenc7f44182020-09-30 15:52:23 +0800906 val = esdhc_read32(&regs->mixctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +0800907 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
Haibo Chenc7f44182020-09-30 15:52:23 +0800908 esdhc_write32(&regs->mixctrl, val);
Yangbo Lufa33d202019-06-21 11:42:27 +0800909
910 /* We are using STD tuning, no need to check return value */
911 mmc_send_tuning(mmc, opcode, NULL);
912
Haibo Chenc7f44182020-09-30 15:52:23 +0800913 ctrl = esdhc_read32(&regs->autoc12err);
Yangbo Lufa33d202019-06-21 11:42:27 +0800914 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
915 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
Yangbo Lufa33d202019-06-21 11:42:27 +0800916 ret = 0;
917 break;
918 }
Yangbo Lufa33d202019-06-21 11:42:27 +0800919 }
920
Haibo Chenc7f44182020-09-30 15:52:23 +0800921 esdhc_write32(&regs->irqstaten, irqstaten);
922 esdhc_write32(&regs->irqsigen, irqsigen);
Yangbo Lufa33d202019-06-21 11:42:27 +0800923
924 esdhc_stop_tuning(mmc);
925
926 return ret;
927}
928#endif
929
930static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
931{
932 struct fsl_esdhc *regs = priv->esdhc_regs;
933 int ret __maybe_unused;
Peng Fan1d01c982019-11-04 17:14:15 +0800934 u32 clock;
Yangbo Lufa33d202019-06-21 11:42:27 +0800935
Yangbo Lufa33d202019-06-21 11:42:27 +0800936 /* Set the clock speed */
Peng Fan1d01c982019-11-04 17:14:15 +0800937 clock = mmc->clock;
938 if (clock < mmc->cfg->f_min)
939 clock = mmc->cfg->f_min;
940
941 if (priv->clock != clock)
942 set_sysctl(priv, mmc, clock);
Yangbo Lufa33d202019-06-21 11:42:27 +0800943
944#ifdef MMC_SUPPORTS_TUNING
945 if (mmc->clk_disable) {
946#ifdef CONFIG_FSL_USDHC
947 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
948#else
949 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
950#endif
951 } else {
952#ifdef CONFIG_FSL_USDHC
953 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
954 VENDORSPEC_CKEN);
955#else
956 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
957#endif
958 }
959
960 if (priv->mode != mmc->selected_mode) {
961 ret = esdhc_set_timing(mmc);
962 if (ret) {
963 printf("esdhc_set_timing error %d\n", ret);
964 return ret;
965 }
966 }
967
968 if (priv->signal_voltage != mmc->signal_voltage) {
969 ret = esdhc_set_voltage(mmc);
970 if (ret) {
Marek Vasut50a17a62020-05-22 18:28:33 +0200971 if (ret != -ENOTSUPP)
972 printf("esdhc_set_voltage error %d\n", ret);
Yangbo Lufa33d202019-06-21 11:42:27 +0800973 return ret;
974 }
975 }
976#endif
977
978 /* Set the bus width */
979 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
980
981 if (mmc->bus_width == 4)
982 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
983 else if (mmc->bus_width == 8)
984 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
985
986 return 0;
987}
988
989static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
990{
991 struct fsl_esdhc *regs = priv->esdhc_regs;
992 ulong start;
993
994 /* Reset the entire host controller */
995 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
996
997 /* Wait until the controller is available */
998 start = get_timer(0);
999 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1000 if (get_timer(start) > 1000)
1001 return -ETIMEDOUT;
1002 }
1003
1004#if defined(CONFIG_FSL_USDHC)
1005 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1006 esdhc_write32(&regs->mmcboot, 0x0);
1007 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1008 esdhc_write32(&regs->mixctrl, 0x0);
1009 esdhc_write32(&regs->clktunectrlstatus, 0x0);
1010
1011 /* Put VEND_SPEC to default value */
1012 if (priv->vs18_enable)
1013 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
1014 ESDHC_VENDORSPEC_VSELECT));
1015 else
1016 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
1017
1018 /* Disable DLL_CTRL delay line */
1019 esdhc_write32(&regs->dllctrl, 0x0);
1020#endif
1021
1022#ifndef ARCH_MXC
1023 /* Enable cache snooping */
1024 esdhc_write32(&regs->scr, 0x00000040);
1025#endif
1026
1027#ifndef CONFIG_FSL_USDHC
1028 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1029#else
1030 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1031#endif
1032
1033 /* Set the initial clock speed */
1034 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1035
1036 /* Disable the BRR and BWR bits in IRQSTAT */
1037 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1038
1039#ifdef CONFIG_MCF5441x
1040 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1041#else
1042 /* Put the PROCTL reg back to the default */
1043 esdhc_write32(&regs->proctl, PROCTL_INIT);
1044#endif
1045
1046 /* Set timout to the maximum value */
1047 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1048
1049 return 0;
1050}
1051
1052static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1053{
1054 struct fsl_esdhc *regs = priv->esdhc_regs;
1055 int timeout = 1000;
1056
1057#ifdef CONFIG_ESDHC_DETECT_QUIRK
1058 if (CONFIG_ESDHC_DETECT_QUIRK)
1059 return 1;
1060#endif
1061
1062#if CONFIG_IS_ENABLED(DM_MMC)
1063 if (priv->non_removable)
1064 return 1;
Fabio Estevam29230f32020-01-06 20:11:27 -03001065
1066 if (priv->broken_cd)
1067 return 1;
Simon Glassbcee8d62019-12-06 21:41:35 -07001068#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lufa33d202019-06-21 11:42:27 +08001069 if (dm_gpio_is_valid(&priv->cd_gpio))
1070 return dm_gpio_get_value(&priv->cd_gpio);
1071#endif
1072#endif
1073
1074 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1075 udelay(1000);
1076
1077 return timeout > 0;
1078}
1079
1080static int esdhc_reset(struct fsl_esdhc *regs)
1081{
1082 ulong start;
1083
1084 /* reset the controller */
1085 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1086
1087 /* hardware clears the bit when it is done */
1088 start = get_timer(0);
1089 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1090 if (get_timer(start) > 100) {
1091 printf("MMC/SD: Reset never completed.\n");
1092 return -ETIMEDOUT;
1093 }
1094 }
1095
1096 return 0;
1097}
1098
1099#if !CONFIG_IS_ENABLED(DM_MMC)
1100static int esdhc_getcd(struct mmc *mmc)
1101{
1102 struct fsl_esdhc_priv *priv = mmc->priv;
1103
1104 return esdhc_getcd_common(priv);
1105}
1106
1107static int esdhc_init(struct mmc *mmc)
1108{
1109 struct fsl_esdhc_priv *priv = mmc->priv;
1110
1111 return esdhc_init_common(priv, mmc);
1112}
1113
1114static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1115 struct mmc_data *data)
1116{
1117 struct fsl_esdhc_priv *priv = mmc->priv;
1118
1119 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1120}
1121
1122static int esdhc_set_ios(struct mmc *mmc)
1123{
1124 struct fsl_esdhc_priv *priv = mmc->priv;
1125
1126 return esdhc_set_ios_common(priv, mmc);
1127}
1128
1129static const struct mmc_ops esdhc_ops = {
1130 .getcd = esdhc_getcd,
1131 .init = esdhc_init,
1132 .send_cmd = esdhc_send_cmd,
1133 .set_ios = esdhc_set_ios,
1134};
1135#endif
1136
1137static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1138 struct fsl_esdhc_plat *plat)
1139{
1140 struct mmc_config *cfg;
1141 struct fsl_esdhc *regs;
1142 u32 caps, voltage_caps;
1143 int ret;
1144
1145 if (!priv)
1146 return -EINVAL;
1147
1148 regs = priv->esdhc_regs;
1149
1150 /* First reset the eSDHC controller */
1151 ret = esdhc_reset(regs);
1152 if (ret)
1153 return ret;
1154
1155#ifdef CONFIG_MCF5441x
1156 /* ColdFire, using SDHC_DATA[3] for card detection */
1157 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1158#endif
1159
1160#ifndef CONFIG_FSL_USDHC
1161 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1162 | SYSCTL_IPGEN | SYSCTL_CKEN);
1163 /* Clearing tuning bits in case ROM has set it already */
1164 esdhc_write32(&regs->mixctrl, 0);
1165 esdhc_write32(&regs->autoc12err, 0);
1166 esdhc_write32(&regs->clktunectrlstatus, 0);
1167#else
1168 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1169 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1170#endif
1171
1172 if (priv->vs18_enable)
1173 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1174
Haibo Chenc7f44182020-09-30 15:52:23 +08001175 esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
Yangbo Lufa33d202019-06-21 11:42:27 +08001176 cfg = &plat->cfg;
1177#ifndef CONFIG_DM_MMC
1178 memset(cfg, '\0', sizeof(*cfg));
1179#endif
1180
1181 voltage_caps = 0;
1182 caps = esdhc_read32(&regs->hostcapblt);
1183
1184#ifdef CONFIG_MCF5441x
1185 /*
1186 * MCF5441x RM declares in more points that sdhc clock speed must
1187 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1188 * from host capabilities.
1189 */
1190 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1191#endif
1192
1193#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1194 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1195 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1196#endif
1197
1198/* T4240 host controller capabilities register should have VS33 bit */
1199#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1200 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1201#endif
1202
1203 if (caps & ESDHC_HOSTCAPBLT_VS18)
1204 voltage_caps |= MMC_VDD_165_195;
1205 if (caps & ESDHC_HOSTCAPBLT_VS30)
1206 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1207 if (caps & ESDHC_HOSTCAPBLT_VS33)
1208 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1209
1210 cfg->name = "FSL_SDHC";
1211#if !CONFIG_IS_ENABLED(DM_MMC)
1212 cfg->ops = &esdhc_ops;
1213#endif
1214#ifdef CONFIG_SYS_SD_VOLTAGE
1215 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1216#else
1217 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1218#endif
1219 if ((cfg->voltages & voltage_caps) == 0) {
1220 printf("voltage not supported by controller\n");
1221 return -1;
1222 }
1223
1224 if (priv->bus_width == 8)
1225 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1226 else if (priv->bus_width == 4)
1227 cfg->host_caps = MMC_MODE_4BIT;
1228
1229 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1230#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1231 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1232#endif
1233
1234 if (priv->bus_width > 0) {
1235 if (priv->bus_width < 8)
1236 cfg->host_caps &= ~MMC_MODE_8BIT;
1237 if (priv->bus_width < 4)
1238 cfg->host_caps &= ~MMC_MODE_4BIT;
1239 }
1240
1241 if (caps & ESDHC_HOSTCAPBLT_HSS)
1242 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1243
1244#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1245 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1246 cfg->host_caps &= ~MMC_MODE_8BIT;
1247#endif
1248
1249 cfg->host_caps |= priv->caps;
1250
1251 cfg->f_min = 400000;
1252 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1253
1254 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1255
Haibo Chenc7f44182020-09-30 15:52:23 +08001256 esdhc_write32(&regs->dllctrl, 0);
Yangbo Lufa33d202019-06-21 11:42:27 +08001257 if (priv->flags & ESDHC_FLAG_USDHC) {
1258 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chenc7f44182020-09-30 15:52:23 +08001259 u32 val = esdhc_read32(&regs->tuning_ctrl);
Yangbo Lufa33d202019-06-21 11:42:27 +08001260
1261 val |= ESDHC_STD_TUNING_EN;
1262 val &= ~ESDHC_TUNING_START_TAP_MASK;
1263 val |= priv->tuning_start_tap;
1264 val &= ~ESDHC_TUNING_STEP_MASK;
1265 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
Haibo Chenba616762020-06-22 19:38:04 +08001266
1267 /* Disable the CMD CRC check for tuning, if not, need to
1268 * add some delay after every tuning command, because
1269 * hardware standard tuning logic will directly go to next
1270 * step once it detect the CMD CRC error, will not wait for
1271 * the card side to finally send out the tuning data, trigger
1272 * the buffer read ready interrupt immediately. If usdhc send
1273 * the next tuning command some eMMC card will stuck, can't
1274 * response, block the tuning procedure or the first command
1275 * after the whole tuning procedure always can't get any response.
1276 */
1277 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
Haibo Chenc7f44182020-09-30 15:52:23 +08001278 esdhc_write32(&regs->tuning_ctrl, val);
Yangbo Lufa33d202019-06-21 11:42:27 +08001279 }
1280 }
1281
1282 return 0;
1283}
1284
1285#if !CONFIG_IS_ENABLED(DM_MMC)
1286static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1287 struct fsl_esdhc_priv *priv)
1288{
1289 if (!cfg || !priv)
1290 return -EINVAL;
1291
1292 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1293 priv->bus_width = cfg->max_bus_width;
1294 priv->sdhc_clk = cfg->sdhc_clk;
1295 priv->wp_enable = cfg->wp_enable;
1296 priv->vs18_enable = cfg->vs18_enable;
1297
1298 return 0;
1299};
1300
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001301int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
Yangbo Lufa33d202019-06-21 11:42:27 +08001302{
1303 struct fsl_esdhc_plat *plat;
1304 struct fsl_esdhc_priv *priv;
1305 struct mmc *mmc;
1306 int ret;
1307
1308 if (!cfg)
1309 return -EINVAL;
1310
1311 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1312 if (!priv)
1313 return -ENOMEM;
1314 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1315 if (!plat) {
1316 free(priv);
1317 return -ENOMEM;
1318 }
1319
1320 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1321 if (ret) {
1322 debug("%s xlate failure\n", __func__);
1323 free(plat);
1324 free(priv);
1325 return ret;
1326 }
1327
1328 ret = fsl_esdhc_init(priv, plat);
1329 if (ret) {
1330 debug("%s init failure\n", __func__);
1331 free(plat);
1332 free(priv);
1333 return ret;
1334 }
1335
1336 mmc = mmc_create(&plat->cfg, priv);
1337 if (!mmc)
1338 return -EIO;
1339
1340 priv->mmc = mmc;
1341
1342 return 0;
1343}
1344
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001345int fsl_esdhc_mmc_init(struct bd_info *bis)
Yangbo Lufa33d202019-06-21 11:42:27 +08001346{
1347 struct fsl_esdhc_cfg *cfg;
1348
1349 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1350 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1351 cfg->sdhc_clk = gd->arch.sdhc_clk;
1352 return fsl_esdhc_initialize(bis, cfg);
1353}
1354#endif
1355
Yangbo Lufa33d202019-06-21 11:42:27 +08001356#ifdef CONFIG_OF_LIBFDT
1357__weak int esdhc_status_fixup(void *blob, const char *compat)
1358{
1359#ifdef CONFIG_FSL_ESDHC_PIN_MUX
1360 if (!hwconfig("esdhc")) {
1361 do_fixup_by_compat(blob, compat, "status", "disabled",
1362 sizeof("disabled"), 1);
1363 return 1;
1364 }
1365#endif
1366 return 0;
1367}
1368
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001369void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
Yangbo Lufa33d202019-06-21 11:42:27 +08001370{
1371 const char *compat = "fsl,esdhc";
1372
1373 if (esdhc_status_fixup(blob, compat))
1374 return;
1375
Yangbo Lufa33d202019-06-21 11:42:27 +08001376 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1377 gd->arch.sdhc_clk, 1);
Yangbo Lufa33d202019-06-21 11:42:27 +08001378}
1379#endif
1380
1381#if CONFIG_IS_ENABLED(DM_MMC)
Yangbo Lufa33d202019-06-21 11:42:27 +08001382#include <asm/arch/clock.h>
Yangbo Lufa33d202019-06-21 11:42:27 +08001383__weak void init_clk_usdhc(u32 index)
1384{
1385}
1386
Walter Lozano23721772020-07-29 12:31:17 -03001387static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
Yangbo Lufa33d202019-06-21 11:42:27 +08001388{
Walter Lozano23721772020-07-29 12:31:17 -03001389#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Yangbo Lufa33d202019-06-21 11:42:27 +08001390 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
Yangbo Lufa33d202019-06-21 11:42:27 +08001391#if CONFIG_IS_ENABLED(DM_REGULATOR)
1392 struct udevice *vqmmc_dev;
Walter Lozano23721772020-07-29 12:31:17 -03001393 int ret;
Yangbo Lufa33d202019-06-21 11:42:27 +08001394#endif
Walter Lozano23721772020-07-29 12:31:17 -03001395 const void *fdt = gd->fdt_blob;
1396 int node = dev_of_offset(dev);
1397
Yangbo Lufa33d202019-06-21 11:42:27 +08001398 fdt_addr_t addr;
1399 unsigned int val;
Yangbo Lufa33d202019-06-21 11:42:27 +08001400
1401 addr = dev_read_addr(dev);
1402 if (addr == FDT_ADDR_T_NONE)
1403 return -EINVAL;
Yangbo Lufa33d202019-06-21 11:42:27 +08001404 priv->esdhc_regs = (struct fsl_esdhc *)addr;
Yangbo Lufa33d202019-06-21 11:42:27 +08001405 priv->dev = dev;
1406 priv->mode = -1;
Yangbo Lufa33d202019-06-21 11:42:27 +08001407
1408 val = dev_read_u32_default(dev, "bus-width", -1);
1409 if (val == 8)
1410 priv->bus_width = 8;
1411 else if (val == 4)
1412 priv->bus_width = 4;
1413 else
1414 priv->bus_width = 1;
1415
1416 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1417 priv->tuning_step = val;
1418 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1419 ESDHC_TUNING_START_TAP_DEFAULT);
1420 priv->tuning_start_tap = val;
1421 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1422 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1423 priv->strobe_dll_delay_target = val;
1424
Fabio Estevam29230f32020-01-06 20:11:27 -03001425 if (dev_read_bool(dev, "broken-cd"))
1426 priv->broken_cd = 1;
1427
Yangbo Lufa33d202019-06-21 11:42:27 +08001428 if (dev_read_bool(dev, "non-removable")) {
1429 priv->non_removable = 1;
1430 } else {
1431 priv->non_removable = 0;
Simon Glassbcee8d62019-12-06 21:41:35 -07001432#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lufa33d202019-06-21 11:42:27 +08001433 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1434 GPIOD_IS_IN);
1435#endif
1436 }
1437
1438 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1439 priv->wp_enable = 1;
1440 } else {
1441 priv->wp_enable = 0;
Simon Glassbcee8d62019-12-06 21:41:35 -07001442#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lufa33d202019-06-21 11:42:27 +08001443 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1444 GPIOD_IS_IN);
1445#endif
1446 }
1447
1448 priv->vs18_enable = 0;
1449
1450#if CONFIG_IS_ENABLED(DM_REGULATOR)
1451 /*
1452 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1453 * otherwise, emmc will work abnormally.
1454 */
1455 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1456 if (ret) {
1457 dev_dbg(dev, "no vqmmc-supply\n");
1458 } else {
Marek Vasut406df852020-05-22 18:19:08 +02001459 priv->vqmmc_dev = vqmmc_dev;
Yangbo Lufa33d202019-06-21 11:42:27 +08001460 ret = regulator_set_enable(vqmmc_dev, true);
1461 if (ret) {
1462 dev_err(dev, "fail to enable vqmmc-supply\n");
1463 return ret;
1464 }
1465
1466 if (regulator_get_value(vqmmc_dev) == 1800000)
1467 priv->vs18_enable = 1;
1468 }
1469#endif
Walter Lozano23721772020-07-29 12:31:17 -03001470#endif
1471 return 0;
1472}
1473
1474static int fsl_esdhc_probe(struct udevice *dev)
1475{
1476 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1477 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1478 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1479 struct esdhc_soc_data *data =
1480 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1481 struct mmc *mmc;
1482#if !CONFIG_IS_ENABLED(BLK)
1483 struct blk_desc *bdesc;
1484#endif
1485 int ret;
1486
1487#if CONFIG_IS_ENABLED(OF_PLATDATA)
1488 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1489 unsigned int val;
1490
1491 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1492 val = plat->dtplat.bus_width;
1493 if (val == 8)
1494 priv->bus_width = 8;
1495 else if (val == 4)
1496 priv->bus_width = 4;
1497 else
1498 priv->bus_width = 1;
Walter Lozano7142ff92020-07-29 12:31:19 -03001499
1500 if (dtplat->non_removable)
1501 priv->non_removable = 1;
1502 else
1503 priv->non_removable = 0;
1504
1505 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1506 struct udevice *gpiodev;
Walter Lozano7142ff92020-07-29 12:31:19 -03001507
Simon Glass8a38abf2020-10-03 11:31:40 -06001508 ret = device_get_by_driver_info_idx(dtplat->cd_gpios->idx,
1509 &gpiodev);
Walter Lozano7142ff92020-07-29 12:31:19 -03001510 if (ret)
1511 return ret;
1512
1513 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1514 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1515 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1516
1517 if (ret)
1518 return ret;
1519 }
Walter Lozano23721772020-07-29 12:31:17 -03001520#endif
1521
1522 if (data)
1523 priv->flags = data->flags;
Yangbo Lufa33d202019-06-21 11:42:27 +08001524
Yangbo Lufa33d202019-06-21 11:42:27 +08001525 /*
1526 * TODO:
1527 * Because lack of clk driver, if SDHC clk is not enabled,
1528 * need to enable it first before this driver is invoked.
1529 *
1530 * we use MXC_ESDHC_CLK to get clk freq.
1531 * If one would like to make this function work,
1532 * the aliases should be provided in dts as this:
1533 *
1534 * aliases {
1535 * mmc0 = &usdhc1;
1536 * mmc1 = &usdhc2;
1537 * mmc2 = &usdhc3;
1538 * mmc3 = &usdhc4;
1539 * };
1540 * Then if your board only supports mmc2 and mmc3, but we can
1541 * correctly get the seq as 2 and 3, then let mxc_get_clock
1542 * work as expected.
1543 */
1544
1545 init_clk_usdhc(dev->seq);
1546
Giulio Benettia820bed2020-01-10 15:51:45 +01001547#if CONFIG_IS_ENABLED(CLK)
1548 /* Assigned clock already set clock */
1549 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1550 if (ret) {
1551 printf("Failed to get per_clk\n");
1552 return ret;
Yangbo Lufa33d202019-06-21 11:42:27 +08001553 }
Giulio Benettia820bed2020-01-10 15:51:45 +01001554 ret = clk_enable(&priv->per_clk);
1555 if (ret) {
1556 printf("Failed to enable per_clk\n");
1557 return ret;
1558 }
1559
1560 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1561#else
1562 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1563 if (priv->sdhc_clk <= 0) {
1564 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1565 return -EINVAL;
1566 }
1567#endif
Yangbo Lufa33d202019-06-21 11:42:27 +08001568
1569 ret = fsl_esdhc_init(priv, plat);
1570 if (ret) {
1571 dev_err(dev, "fsl_esdhc_init failure\n");
1572 return ret;
1573 }
1574
Walter Lozano23721772020-07-29 12:31:17 -03001575#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Peng Fanb0155ac2019-07-10 09:35:24 +00001576 ret = mmc_of_parse(dev, &plat->cfg);
1577 if (ret)
1578 return ret;
Walter Lozano23721772020-07-29 12:31:17 -03001579#endif
Peng Fanb0155ac2019-07-10 09:35:24 +00001580
Yangbo Lufa33d202019-06-21 11:42:27 +08001581 mmc = &plat->mmc;
1582 mmc->cfg = &plat->cfg;
1583 mmc->dev = dev;
1584#if !CONFIG_IS_ENABLED(BLK)
1585 mmc->priv = priv;
1586
1587 /* Setup dsr related values */
1588 mmc->dsr_imp = 0;
1589 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1590 /* Setup the universal parts of the block interface just once */
1591 bdesc = mmc_get_blk_desc(mmc);
1592 bdesc->if_type = IF_TYPE_MMC;
1593 bdesc->removable = 1;
1594 bdesc->devnum = mmc_get_next_devnum();
1595 bdesc->block_read = mmc_bread;
1596 bdesc->block_write = mmc_bwrite;
1597 bdesc->block_erase = mmc_berase;
1598
1599 /* setup initial part type */
1600 bdesc->part_type = mmc->cfg->part_type;
1601 mmc_list_add(mmc);
1602#endif
1603
1604 upriv->mmc = mmc;
1605
1606 return esdhc_init_common(priv, mmc);
1607}
1608
1609#if CONFIG_IS_ENABLED(DM_MMC)
1610static int fsl_esdhc_get_cd(struct udevice *dev)
1611{
1612 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1613
1614 return esdhc_getcd_common(priv);
1615}
1616
1617static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1618 struct mmc_data *data)
1619{
1620 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1621 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1622
1623 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1624}
1625
1626static int fsl_esdhc_set_ios(struct udevice *dev)
1627{
1628 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1629 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1630
1631 return esdhc_set_ios_common(priv, &plat->mmc);
1632}
1633
Peng Fane9c22552019-07-10 09:35:26 +00001634#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1635static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1636{
1637 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1638 struct fsl_esdhc *regs = priv->esdhc_regs;
1639 u32 m;
1640
Haibo Chenc7f44182020-09-30 15:52:23 +08001641 m = esdhc_read32(&regs->mixctrl);
Peng Fane9c22552019-07-10 09:35:26 +00001642 m |= MIX_CTRL_HS400_ES;
Haibo Chenc7f44182020-09-30 15:52:23 +08001643 esdhc_write32(&regs->mixctrl, m);
Peng Fane9c22552019-07-10 09:35:26 +00001644
1645 return 0;
1646}
1647#endif
1648
Yangbo Lufa33d202019-06-21 11:42:27 +08001649static const struct dm_mmc_ops fsl_esdhc_ops = {
1650 .get_cd = fsl_esdhc_get_cd,
1651 .send_cmd = fsl_esdhc_send_cmd,
1652 .set_ios = fsl_esdhc_set_ios,
1653#ifdef MMC_SUPPORTS_TUNING
1654 .execute_tuning = fsl_esdhc_execute_tuning,
1655#endif
Peng Fane9c22552019-07-10 09:35:26 +00001656#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1657 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1658#endif
Yangbo Lufa33d202019-06-21 11:42:27 +08001659};
1660#endif
1661
1662static struct esdhc_soc_data usdhc_imx7d_data = {
1663 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1664 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1665 | ESDHC_FLAG_HS400,
Yangbo Lufa33d202019-06-21 11:42:27 +08001666};
1667
Peng Fan609ba122019-07-10 09:35:28 +00001668static struct esdhc_soc_data usdhc_imx8qm_data = {
1669 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1670 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1671 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1672};
1673
Yangbo Lufa33d202019-06-21 11:42:27 +08001674static const struct udevice_id fsl_esdhc_ids[] = {
1675 { .compatible = "fsl,imx53-esdhc", },
1676 { .compatible = "fsl,imx6ul-usdhc", },
1677 { .compatible = "fsl,imx6sx-usdhc", },
1678 { .compatible = "fsl,imx6sl-usdhc", },
1679 { .compatible = "fsl,imx6q-usdhc", },
1680 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1681 { .compatible = "fsl,imx7ulp-usdhc", },
Peng Fan609ba122019-07-10 09:35:28 +00001682 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Peng Fanf65d0842019-11-04 17:31:17 +08001683 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1684 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1685 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Giulio Benetti6a63a872020-01-10 15:51:46 +01001686 { .compatible = "fsl,imxrt-usdhc", },
Yangbo Lufa33d202019-06-21 11:42:27 +08001687 { .compatible = "fsl,esdhc", },
1688 { /* sentinel */ }
1689};
1690
1691#if CONFIG_IS_ENABLED(BLK)
1692static int fsl_esdhc_bind(struct udevice *dev)
1693{
1694 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1695
1696 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1697}
1698#endif
1699
1700U_BOOT_DRIVER(fsl_esdhc) = {
Walter Lozano45154f02020-07-29 12:31:16 -03001701 .name = "fsl_esdhc",
Yangbo Lufa33d202019-06-21 11:42:27 +08001702 .id = UCLASS_MMC,
1703 .of_match = fsl_esdhc_ids,
Walter Lozano23721772020-07-29 12:31:17 -03001704 .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
Yangbo Lufa33d202019-06-21 11:42:27 +08001705 .ops = &fsl_esdhc_ops,
1706#if CONFIG_IS_ENABLED(BLK)
1707 .bind = fsl_esdhc_bind,
1708#endif
1709 .probe = fsl_esdhc_probe,
1710 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1711 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1712};
Walter Lozano23721772020-07-29 12:31:17 -03001713
1714U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
Yangbo Lufa33d202019-06-21 11:42:27 +08001715#endif