Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 9eb7acef97d1a892d59c5928001dd9516bb592de / . / arch / arm / mach-uniphier / ph1-pro4 / pll_init.c
blob: 1db90f88a0e7c99badc3a089462929ce998fd191 [file] [log] [blame]
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]1/*
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sc-regs.h>
10#include <asm/arch/sg-regs.h>
11
12#undef DPLL_SSC_RATE_1PER
13
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]14static void dpll_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]15{
16 u32 tmp;
17
18 /*
19 * Set Frequency
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT ( DPLLCTRL.bit[29:20] )
22 */
23 tmp = readl(SC_DPLLCTRL);
24 tmp &= ~(0x000f0000);
25#if CONFIG_DDR_FREQ == 1600
26 tmp |= 0x000c0000;
27#elif CONFIG_DDR_FREQ == 1333
28 tmp |= 0x000d0000;
29#else
30# error "Unsupported frequency"
31#endif
32
33 /*
34 * Set Moduration rate
35 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
36 */
37#if defined(DPLL_SSC_RATE_1PER)
38 tmp &= ~0x00008000;
39#else
40 tmp |= 0x00008000;
41#endif
42 writel(tmp, SC_DPLLCTRL);
43
44 tmp = readl(SC_DPLLCTRL2);
45 tmp |= SC_DPLLCTRL2_NRSTDS;
46 writel(tmp, SC_DPLLCTRL2);
47}
48
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]49static void stop_mpll(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]50{
51 u32 tmp;
52
53 tmp = readl(SC_MPLLOSCCTL);
54
55 if (!(tmp & SC_MPLLOSCCTL_MPLLST))
56 return; /* already stopped */
57
58 tmp &= ~SC_MPLLOSCCTL_MPLLEN;
59 writel(tmp, SC_MPLLOSCCTL);
60
61 while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
62 ;
63}
64
Masahiro Yamadaec79c792015-01-21 15:06:06 +0900[diff] [blame]65static void vpll_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]66{
67 u32 tmp, clk_mode_axosel;
68
69 /* Set VPLL27A & VPLL27B */
70 tmp = readl(SG_PINMON0);
71 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
72
73#if defined(CONFIG_MACH_PH1_PRO4)
74 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
75 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
76 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
77 return;
78#endif
79
80 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
81 tmp = readl(SC_VPLL27ACTRL);
82 tmp |= 0x00000001;
83 writel(tmp, SC_VPLL27ACTRL);
84 tmp = readl(SC_VPLL27BCTRL);
85 tmp |= 0x00000001;
86 writel(tmp, SC_VPLL27BCTRL);
87
88 /* Unset VPLA_K_LD and VPLB_K_LD bit */
89 tmp = readl(SC_VPLL27ACTRL3);
90 tmp &= ~0x10000000;
91 writel(tmp, SC_VPLL27ACTRL3);
92 tmp = readl(SC_VPLL27BCTRL3);
93 tmp &= ~0x10000000;
94 writel(tmp, SC_VPLL27BCTRL3);
95
96 /* Set VPLA_M and VPLB_M to 0x20 */
97 tmp = readl(SC_VPLL27ACTRL2);
98 tmp &= ~0x0000007f;
99 tmp |= 0x00000020;
100 writel(tmp, SC_VPLL27ACTRL2);
101 tmp = readl(SC_VPLL27BCTRL2);
102 tmp &= ~0x0000007f;
103 tmp |= 0x00000020;
104 writel(tmp, SC_VPLL27BCTRL2);
105
106 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
107 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
108 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
109 tmp = readl(SC_VPLL27ACTRL3);
110 tmp &= ~0x000fffff;
111 tmp |= 0x00066666;
112 writel(tmp, SC_VPLL27ACTRL3);
113 tmp = readl(SC_VPLL27BCTRL3);
114 tmp &= ~0x000fffff;
115 tmp |= 0x00066666;
116 writel(tmp, SC_VPLL27BCTRL3);
117 } else {
118 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
119 tmp = readl(SC_VPLL27ACTRL3);
120 tmp &= ~0x000fffff;
121 tmp |= 0x000f5800;
122 writel(tmp, SC_VPLL27ACTRL3);
123 tmp = readl(SC_VPLL27BCTRL3);
124 tmp &= ~0x000fffff;
125 tmp |= 0x000f5800;
126 writel(tmp, SC_VPLL27BCTRL3);
127 }
128
129 /* wait 1 usec */
130 udelay(1);
131
132 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
133 tmp = readl(SC_VPLL27ACTRL3);
134 tmp |= 0x10000000;
135 writel(tmp, SC_VPLL27ACTRL3);
136 tmp = readl(SC_VPLL27BCTRL3);
137 tmp |= 0x10000000;
138 writel(tmp, SC_VPLL27BCTRL3);
139
140 /* Unset VPLA_SNRST and VPLB_SNRST bit */
141 tmp = readl(SC_VPLL27ACTRL2);
142 tmp |= 0x10000000;
143 writel(tmp, SC_VPLL27ACTRL2);
144 tmp = readl(SC_VPLL27BCTRL2);
145 tmp |= 0x10000000;
146 writel(tmp, SC_VPLL27BCTRL2);
147
148 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
149 tmp = readl(SC_VPLL27ACTRL);
150 tmp &= ~0x00000001;
151 writel(tmp, SC_VPLL27ACTRL);
152 tmp = readl(SC_VPLL27BCTRL);
153 tmp &= ~0x00000001;
154 writel(tmp, SC_VPLL27BCTRL);
155}
156
157void pll_init(void)
158{
159 dpll_init();
160 stop_mpll();
161 vpll_init();
162
163 /*
164 * Wait 500 usec until dpll get stable
165 * We wait 1 usec in vpll_init() so 1 usec can be saved here.
166 */
167 udelay(499);
168}