wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * David Mueller, ELSOFT AG, d.mueller@elsoft.ch |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* This code should work for both the S3C2400 and the S3C2410 |
| 9 | * as they seem to have the same I2C controller inside. |
| 10 | * The different address mapping is handled by the s3c24xx.h files below. |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 14 | #include <fdtdec.h> |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 15 | #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 16 | #include <asm/arch/clk.h> |
| 17 | #include <asm/arch/cpu.h> |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 18 | #include <asm/arch/pinmux.h> |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 19 | #else |
kevin.morfitt@fearnside-systems.co.uk | ac67804 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 20 | #include <asm/arch/s3c24x0_cpu.h> |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 21 | #endif |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 22 | #include <asm/io.h> |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 23 | #include <i2c.h> |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 24 | #include "s3c24x0_i2c.h" |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 25 | |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 26 | #define I2C_WRITE 0 |
| 27 | #define I2C_READ 1 |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 28 | |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 29 | #define I2C_OK 0 |
| 30 | #define I2C_NOK 1 |
| 31 | #define I2C_NACK 2 |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 32 | #define I2C_NOK_LA 3 /* Lost arbitration */ |
| 33 | #define I2C_NOK_TOUT 4 /* time out */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 34 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 35 | /* HSI2C specific register description */ |
| 36 | |
| 37 | /* I2C_CTL Register bits */ |
| 38 | #define HSI2C_FUNC_MODE_I2C (1u << 0) |
| 39 | #define HSI2C_MASTER (1u << 3) |
| 40 | #define HSI2C_RXCHON (1u << 6) /* Write/Send */ |
| 41 | #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ |
| 42 | #define HSI2C_SW_RST (1u << 31) |
| 43 | |
| 44 | /* I2C_FIFO_CTL Register bits */ |
| 45 | #define HSI2C_RXFIFO_EN (1u << 0) |
| 46 | #define HSI2C_TXFIFO_EN (1u << 1) |
| 47 | #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) |
| 48 | #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) |
| 49 | |
| 50 | /* I2C_TRAILING_CTL Register bits */ |
| 51 | #define HSI2C_TRAILING_COUNT (0xff) |
| 52 | |
| 53 | /* I2C_INT_EN Register bits */ |
| 54 | #define HSI2C_TX_UNDERRUN_EN (1u << 2) |
| 55 | #define HSI2C_TX_OVERRUN_EN (1u << 3) |
| 56 | #define HSI2C_RX_UNDERRUN_EN (1u << 4) |
| 57 | #define HSI2C_RX_OVERRUN_EN (1u << 5) |
| 58 | #define HSI2C_INT_TRAILING_EN (1u << 6) |
| 59 | #define HSI2C_INT_I2C_EN (1u << 9) |
| 60 | |
| 61 | #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ |
| 62 | HSI2C_TX_OVERRUN_EN |\ |
| 63 | HSI2C_RX_UNDERRUN_EN |\ |
| 64 | HSI2C_RX_OVERRUN_EN |\ |
| 65 | HSI2C_INT_TRAILING_EN) |
| 66 | |
| 67 | /* I2C_CONF Register bits */ |
| 68 | #define HSI2C_AUTO_MODE (1u << 31) |
| 69 | #define HSI2C_10BIT_ADDR_MODE (1u << 30) |
| 70 | #define HSI2C_HS_MODE (1u << 29) |
| 71 | |
| 72 | /* I2C_AUTO_CONF Register bits */ |
| 73 | #define HSI2C_READ_WRITE (1u << 16) |
| 74 | #define HSI2C_STOP_AFTER_TRANS (1u << 17) |
| 75 | #define HSI2C_MASTER_RUN (1u << 31) |
| 76 | |
| 77 | /* I2C_TIMEOUT Register bits */ |
| 78 | #define HSI2C_TIMEOUT_EN (1u << 31) |
| 79 | |
| 80 | /* I2C_TRANS_STATUS register bits */ |
| 81 | #define HSI2C_MASTER_BUSY (1u << 17) |
| 82 | #define HSI2C_SLAVE_BUSY (1u << 16) |
| 83 | #define HSI2C_TIMEOUT_AUTO (1u << 4) |
| 84 | #define HSI2C_NO_DEV (1u << 3) |
| 85 | #define HSI2C_NO_DEV_ACK (1u << 2) |
| 86 | #define HSI2C_TRANS_ABORT (1u << 1) |
| 87 | #define HSI2C_TRANS_SUCCESS (1u << 0) |
| 88 | #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ |
| 89 | HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ |
| 90 | HSI2C_TRANS_ABORT) |
| 91 | #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) |
| 92 | |
| 93 | |
| 94 | /* I2C_FIFO_STAT Register bits */ |
| 95 | #define HSI2C_RX_FIFO_EMPTY (1u << 24) |
| 96 | #define HSI2C_RX_FIFO_FULL (1u << 23) |
| 97 | #define HSI2C_TX_FIFO_EMPTY (1u << 8) |
| 98 | #define HSI2C_TX_FIFO_FULL (1u << 7) |
| 99 | #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) |
| 100 | #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) |
| 101 | |
| 102 | #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) |
| 103 | |
| 104 | /* S3C I2C Controller bits */ |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 105 | #define I2CSTAT_BSY 0x20 /* Busy bit */ |
| 106 | #define I2CSTAT_NACK 0x01 /* Nack bit */ |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 107 | #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 108 | #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ |
| 109 | #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ |
| 110 | #define I2C_MODE_MR 0x80 /* Master Receive Mode */ |
| 111 | #define I2C_START_STOP 0x20 /* START / STOP */ |
| 112 | #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 113 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 114 | #define I2C_TIMEOUT_MS 1000 /* 1 second */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 115 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 116 | #define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */ |
| 117 | |
| 118 | |
| 119 | /* To support VCMA9 boards and other who dont define max_i2c_num */ |
| 120 | #ifndef CONFIG_MAX_I2C_NUM |
| 121 | #define CONFIG_MAX_I2C_NUM 1 |
| 122 | #endif |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 123 | |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 124 | /* |
| 125 | * For SPL boot some boards need i2c before SDRAM is initialised so force |
| 126 | * variables to live in SRAM |
| 127 | */ |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 128 | static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] |
| 129 | __attribute__((section(".data"))); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 130 | |
| 131 | /** |
| 132 | * Get a pointer to the given bus index |
| 133 | * |
| 134 | * @bus_idx: Bus index to look up |
| 135 | * @return pointer to bus, or NULL if invalid or not available |
| 136 | */ |
| 137 | static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) |
| 138 | { |
| 139 | if (bus_idx < ARRAY_SIZE(i2c_bus)) { |
| 140 | struct s3c24x0_i2c_bus *bus; |
| 141 | |
| 142 | bus = &i2c_bus[bus_idx]; |
| 143 | if (bus->active) |
| 144 | return bus; |
| 145 | } |
| 146 | |
| 147 | debug("Undefined bus: %d\n", bus_idx); |
| 148 | return NULL; |
| 149 | } |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 150 | |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 151 | #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 152 | static int GetI2CSDA(void) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 153 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 154 | struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 155 | |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 156 | #ifdef CONFIG_S3C2410 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 157 | return (readl(&gpio->gpedat) & 0x8000) >> 15; |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 158 | #endif |
| 159 | #ifdef CONFIG_S3C2400 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 160 | return (readl(&gpio->pgdat) & 0x0020) >> 5; |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 161 | #endif |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 162 | } |
| 163 | |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 164 | static void SetI2CSCL(int x) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 165 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 166 | struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 167 | |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 168 | #ifdef CONFIG_S3C2410 |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 169 | writel((readl(&gpio->gpedat) & ~0x4000) | |
| 170 | (x & 1) << 14, &gpio->gpedat); |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 171 | #endif |
| 172 | #ifdef CONFIG_S3C2400 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 173 | writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 174 | #endif |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 175 | } |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 176 | #endif |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 177 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 178 | /* |
| 179 | * Wait til the byte transfer is completed. |
| 180 | * |
| 181 | * @param i2c- pointer to the appropriate i2c register bank. |
| 182 | * @return I2C_OK, if transmission was ACKED |
| 183 | * I2C_NACK, if transmission was NACKED |
| 184 | * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS |
| 185 | */ |
| 186 | |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 187 | static int WaitForXfer(struct s3c24x0_i2c *i2c) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 188 | { |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 189 | ulong start_time = get_timer(0); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 190 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 191 | do { |
| 192 | if (readl(&i2c->iiccon) & I2CCON_IRPND) |
| 193 | return (readl(&i2c->iicstat) & I2CSTAT_NACK) ? |
| 194 | I2C_NACK : I2C_OK; |
| 195 | } while (get_timer(start_time) < I2C_TIMEOUT_MS); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 196 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 197 | return I2C_NOK_TOUT; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 198 | } |
| 199 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 200 | /* |
| 201 | * Wait for transfer completion. |
| 202 | * |
| 203 | * This function reads the interrupt status register waiting for the INT_I2C |
| 204 | * bit to be set, which indicates copletion of a transaction. |
| 205 | * |
| 206 | * @param i2c: pointer to the appropriate register bank |
| 207 | * |
| 208 | * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case |
| 209 | * the status bits do not get set in time, or an approrpiate error |
| 210 | * value in case of transfer errors. |
| 211 | */ |
| 212 | static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) |
| 213 | { |
| 214 | int i = HSI2C_TIMEOUT_US; |
| 215 | |
| 216 | while (i-- > 0) { |
| 217 | u32 int_status = readl(&i2c->usi_int_stat); |
| 218 | |
| 219 | if (int_status & HSI2C_INT_I2C_EN) { |
| 220 | u32 trans_status = readl(&i2c->usi_trans_status); |
| 221 | |
| 222 | /* Deassert pending interrupt. */ |
| 223 | writel(int_status, &i2c->usi_int_stat); |
| 224 | |
| 225 | if (trans_status & HSI2C_NO_DEV_ACK) { |
| 226 | debug("%s: no ACK from device\n", __func__); |
| 227 | return I2C_NACK; |
| 228 | } |
| 229 | if (trans_status & HSI2C_NO_DEV) { |
| 230 | debug("%s: no device\n", __func__); |
| 231 | return I2C_NOK; |
| 232 | } |
| 233 | if (trans_status & HSI2C_TRANS_ABORT) { |
| 234 | debug("%s: arbitration lost\n", __func__); |
| 235 | return I2C_NOK_LA; |
| 236 | } |
| 237 | if (trans_status & HSI2C_TIMEOUT_AUTO) { |
| 238 | debug("%s: device timed out\n", __func__); |
| 239 | return I2C_NOK_TOUT; |
| 240 | } |
| 241 | return I2C_OK; |
| 242 | } |
| 243 | udelay(1); |
| 244 | } |
| 245 | debug("%s: transaction timeout!\n", __func__); |
| 246 | return I2C_NOK_TOUT; |
| 247 | } |
| 248 | |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 249 | static void ReadWriteByte(struct s3c24x0_i2c *i2c) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 250 | { |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 251 | writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 254 | static struct s3c24x0_i2c *get_base_i2c(int bus) |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 255 | { |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 256 | #ifdef CONFIG_EXYNOS4 |
| 257 | struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() |
| 258 | + (EXYNOS4_I2C_SPACING |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 259 | * bus)); |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 260 | return i2c; |
| 261 | #elif defined CONFIG_EXYNOS5 |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 262 | struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() |
| 263 | + (EXYNOS5_I2C_SPACING |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 264 | * bus)); |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 265 | return i2c; |
| 266 | #else |
| 267 | return s3c24x0_get_base_i2c(); |
| 268 | #endif |
| 269 | } |
| 270 | |
| 271 | static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) |
| 272 | { |
| 273 | ulong freq, pres = 16, div; |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 274 | #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 275 | freq = get_i2c_clk(); |
| 276 | #else |
| 277 | freq = get_PCLK(); |
| 278 | #endif |
| 279 | /* calculate prescaler and divisor values */ |
| 280 | if ((freq / pres / (16 + 1)) > speed) |
| 281 | /* set prescaler to 512 */ |
| 282 | pres = 512; |
| 283 | |
| 284 | div = 0; |
| 285 | while ((freq / pres / (div + 1)) > speed) |
| 286 | div++; |
| 287 | |
| 288 | /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ |
| 289 | writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); |
| 290 | |
| 291 | /* init to SLAVE REVEIVE and set slaveaddr */ |
| 292 | writel(0, &i2c->iicstat); |
| 293 | writel(slaveadd, &i2c->iicadd); |
| 294 | /* program Master Transmit (and implicit STOP) */ |
| 295 | writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); |
| 296 | } |
| 297 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 298 | static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) |
| 299 | { |
| 300 | struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; |
| 301 | ulong clkin; |
| 302 | unsigned int op_clk = i2c_bus->clock_frequency; |
| 303 | unsigned int i = 0, utemp0 = 0, utemp1 = 0; |
| 304 | unsigned int t_ftl_cycle; |
| 305 | |
| 306 | #if defined CONFIG_EXYNOS5 |
| 307 | clkin = get_i2c_clk(); |
| 308 | #endif |
| 309 | /* FPCLK / FI2C = |
| 310 | * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE |
| 311 | * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) |
| 312 | * uTemp1 = (TSCLK_L + TSCLK_H + 2) |
| 313 | * uTemp2 = TSCLK_L + TSCLK_H |
| 314 | */ |
| 315 | t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; |
| 316 | utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; |
| 317 | |
| 318 | /* CLK_DIV max is 256 */ |
| 319 | for (i = 0; i < 256; i++) { |
| 320 | utemp1 = utemp0 / (i + 1); |
| 321 | if ((utemp1 < 512) && (utemp1 > 4)) { |
| 322 | i2c_bus->clk_cycle = utemp1 - 2; |
| 323 | i2c_bus->clk_div = i; |
| 324 | return 0; |
| 325 | } |
| 326 | } |
| 327 | return -1; |
| 328 | } |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 329 | |
| 330 | static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) |
| 331 | { |
| 332 | struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; |
| 333 | unsigned int t_sr_release; |
| 334 | unsigned int n_clkdiv; |
| 335 | unsigned int t_start_su, t_start_hd; |
| 336 | unsigned int t_stop_su; |
| 337 | unsigned int t_data_su, t_data_hd; |
| 338 | unsigned int t_scl_l, t_scl_h; |
| 339 | u32 i2c_timing_s1; |
| 340 | u32 i2c_timing_s2; |
| 341 | u32 i2c_timing_s3; |
| 342 | u32 i2c_timing_sla; |
| 343 | |
| 344 | n_clkdiv = i2c_bus->clk_div; |
| 345 | t_scl_l = i2c_bus->clk_cycle / 2; |
| 346 | t_scl_h = i2c_bus->clk_cycle / 2; |
| 347 | t_start_su = t_scl_l; |
| 348 | t_start_hd = t_scl_l; |
| 349 | t_stop_su = t_scl_l; |
| 350 | t_data_su = t_scl_l / 2; |
| 351 | t_data_hd = t_scl_l / 2; |
| 352 | t_sr_release = i2c_bus->clk_cycle; |
| 353 | |
| 354 | i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; |
| 355 | i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; |
| 356 | i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; |
| 357 | i2c_timing_sla = t_data_hd << 0; |
| 358 | |
| 359 | writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); |
| 360 | |
| 361 | /* Clear to enable Timeout */ |
| 362 | clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); |
| 363 | |
| 364 | /* set AUTO mode */ |
| 365 | writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); |
| 366 | |
| 367 | /* Enable completion conditions' reporting. */ |
| 368 | writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); |
| 369 | |
| 370 | /* Enable FIFOs */ |
| 371 | writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); |
| 372 | |
| 373 | /* Currently operating in Fast speed mode. */ |
| 374 | writel(i2c_timing_s1, &hsregs->usi_timing_fs1); |
| 375 | writel(i2c_timing_s2, &hsregs->usi_timing_fs2); |
| 376 | writel(i2c_timing_s3, &hsregs->usi_timing_fs3); |
| 377 | writel(i2c_timing_sla, &hsregs->usi_timing_sla); |
| 378 | } |
| 379 | |
| 380 | /* SW reset for the high speed bus */ |
| 381 | static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) |
| 382 | { |
| 383 | struct exynos5_hsi2c *i2c = i2c_bus->hsregs; |
| 384 | u32 i2c_ctl; |
| 385 | |
| 386 | /* Set and clear the bit for reset */ |
| 387 | i2c_ctl = readl(&i2c->usi_ctl); |
| 388 | i2c_ctl |= HSI2C_SW_RST; |
| 389 | writel(i2c_ctl, &i2c->usi_ctl); |
| 390 | |
| 391 | i2c_ctl = readl(&i2c->usi_ctl); |
| 392 | i2c_ctl &= ~HSI2C_SW_RST; |
| 393 | writel(i2c_ctl, &i2c->usi_ctl); |
| 394 | |
| 395 | /* Initialize the configure registers */ |
| 396 | hsi2c_ch_init(i2c_bus); |
| 397 | } |
| 398 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 399 | static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 400 | { |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 401 | struct s3c24x0_i2c *i2c; |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 402 | struct s3c24x0_i2c_bus *bus; |
| 403 | |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 404 | #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 405 | struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 406 | #endif |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 407 | ulong start_time = get_timer(0); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 408 | |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 409 | /* By default i2c channel 0 is the current bus */ |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 410 | i2c = get_base_i2c(adap->hwadapnr); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 411 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 412 | /* |
| 413 | * In case the previous transfer is still going, wait to give it a |
| 414 | * chance to finish. |
| 415 | */ |
| 416 | while (readl(&i2c->iicstat) & I2CSTAT_BSY) { |
| 417 | if (get_timer(start_time) > I2C_TIMEOUT_MS) { |
| 418 | printf("%s: I2C bus busy for %p\n", __func__, |
| 419 | &i2c->iicstat); |
| 420 | return; |
| 421 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 422 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 423 | |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 424 | #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 425 | int i; |
| 426 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 427 | if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 428 | #ifdef CONFIG_S3C2410 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 429 | ulong old_gpecon = readl(&gpio->gpecon); |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 430 | #endif |
| 431 | #ifdef CONFIG_S3C2400 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 432 | ulong old_gpecon = readl(&gpio->pgcon); |
wdenk | 6dff552 | 2003-07-15 07:45:49 +0000 | [diff] [blame] | 433 | #endif |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 434 | /* bus still busy probably by (most) previously interrupted |
| 435 | transfer */ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 436 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 437 | #ifdef CONFIG_S3C2410 |
| 438 | /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 439 | writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, |
| 440 | &gpio->gpecon); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 441 | #endif |
| 442 | #ifdef CONFIG_S3C2400 |
| 443 | /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 444 | writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, |
| 445 | &gpio->pgcon); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 446 | #endif |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 447 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 448 | /* toggle I2CSCL until bus idle */ |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 449 | SetI2CSCL(0); |
| 450 | udelay(1000); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 451 | i = 10; |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 452 | while ((i > 0) && (GetI2CSDA() != 1)) { |
| 453 | SetI2CSCL(1); |
| 454 | udelay(1000); |
| 455 | SetI2CSCL(0); |
| 456 | udelay(1000); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 457 | i--; |
| 458 | } |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 459 | SetI2CSCL(1); |
| 460 | udelay(1000); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 461 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 462 | /* restore pin functions */ |
| 463 | #ifdef CONFIG_S3C2410 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 464 | writel(old_gpecon, &gpio->gpecon); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 465 | #endif |
| 466 | #ifdef CONFIG_S3C2400 |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 467 | writel(old_gpecon, &gpio->pgcon); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 468 | #endif |
| 469 | } |
Piotr Wilczek | c86d9ed | 2012-11-20 02:19:05 +0000 | [diff] [blame] | 470 | #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 471 | i2c_ch_init(i2c, speed, slaveadd); |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 472 | |
| 473 | bus = &i2c_bus[adap->hwadapnr]; |
| 474 | bus->active = true; |
| 475 | bus->regs = i2c; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | /* |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 479 | * Poll the appropriate bit of the fifo status register until the interface is |
| 480 | * ready to process the next byte or timeout expires. |
| 481 | * |
| 482 | * In addition to the FIFO status register this function also polls the |
| 483 | * interrupt status register to be able to detect unexpected transaction |
| 484 | * completion. |
| 485 | * |
| 486 | * When FIFO is ready to process the next byte, this function returns I2C_OK. |
| 487 | * If in course of polling the INT_I2C assertion is detected, the function |
| 488 | * returns I2C_NOK. If timeout happens before any of the above conditions is |
| 489 | * met - the function returns I2C_NOK_TOUT; |
| 490 | |
| 491 | * @param i2c: pointer to the appropriate i2c register bank. |
| 492 | * @param rx_transfer: set to True if the receive transaction is in progress. |
| 493 | * @return: as described above. |
| 494 | */ |
| 495 | static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) |
| 496 | { |
| 497 | u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; |
| 498 | int i = HSI2C_TIMEOUT_US; |
| 499 | |
| 500 | while (readl(&i2c->usi_fifo_stat) & fifo_bit) { |
| 501 | if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { |
| 502 | /* |
| 503 | * There is a chance that assertion of |
| 504 | * HSI2C_INT_I2C_EN and deassertion of |
| 505 | * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's |
| 506 | * give FIFO status priority and check it one more |
| 507 | * time before reporting interrupt. The interrupt will |
| 508 | * be reported next time this function is called. |
| 509 | */ |
| 510 | if (rx_transfer && |
| 511 | !(readl(&i2c->usi_fifo_stat) & fifo_bit)) |
| 512 | break; |
| 513 | return I2C_NOK; |
| 514 | } |
| 515 | if (!i--) { |
| 516 | debug("%s: FIFO polling timeout!\n", __func__); |
| 517 | return I2C_NOK_TOUT; |
| 518 | } |
| 519 | udelay(1); |
| 520 | } |
| 521 | return I2C_OK; |
| 522 | } |
| 523 | |
| 524 | /* |
| 525 | * Preapre hsi2c transaction, either read or write. |
| 526 | * |
| 527 | * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of |
| 528 | * the 5420 UM. |
| 529 | * |
| 530 | * @param i2c: pointer to the appropriate i2c register bank. |
| 531 | * @param chip: slave address on the i2c bus (with read/write bit exlcuded) |
| 532 | * @param len: number of bytes expected to be sent or received |
| 533 | * @param rx_transfer: set to true for receive transactions |
| 534 | * @param: issue_stop: set to true if i2c stop condition should be generated |
| 535 | * after this transaction. |
| 536 | * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, |
| 537 | * I2C_OK otherwise. |
| 538 | */ |
| 539 | static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, |
| 540 | u8 chip, |
| 541 | u16 len, |
| 542 | bool rx_transfer, |
| 543 | bool issue_stop) |
| 544 | { |
| 545 | u32 conf; |
| 546 | |
| 547 | conf = len | HSI2C_MASTER_RUN; |
| 548 | |
| 549 | if (issue_stop) |
| 550 | conf |= HSI2C_STOP_AFTER_TRANS; |
| 551 | |
| 552 | /* Clear to enable Timeout */ |
| 553 | writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); |
| 554 | |
| 555 | /* Set slave address */ |
| 556 | writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); |
| 557 | |
| 558 | if (rx_transfer) { |
| 559 | /* i2c master, read transaction */ |
| 560 | writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), |
| 561 | &i2c->usi_ctl); |
| 562 | |
| 563 | /* read up to len bytes, stop after transaction is finished */ |
| 564 | writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); |
| 565 | } else { |
| 566 | /* i2c master, write transaction */ |
| 567 | writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), |
| 568 | &i2c->usi_ctl); |
| 569 | |
| 570 | /* write up to len bytes, stop after transaction is finished */ |
| 571 | writel(conf, &i2c->usi_auto_conf); |
| 572 | } |
| 573 | |
| 574 | /* Reset all pending interrupt status bits we care about, if any */ |
| 575 | writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); |
| 576 | |
| 577 | return I2C_OK; |
| 578 | } |
| 579 | |
| 580 | /* |
| 581 | * Wait while i2c bus is settling down (mostly stop gets completed). |
| 582 | */ |
| 583 | static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) |
| 584 | { |
| 585 | int i = HSI2C_TIMEOUT_US; |
| 586 | |
| 587 | while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { |
| 588 | if (!i--) { |
| 589 | debug("%s: bus busy\n", __func__); |
| 590 | return I2C_NOK_TOUT; |
| 591 | } |
| 592 | udelay(1); |
| 593 | } |
| 594 | return I2C_OK; |
| 595 | } |
| 596 | |
| 597 | static int hsi2c_write(struct exynos5_hsi2c *i2c, |
| 598 | unsigned char chip, |
| 599 | unsigned char addr[], |
| 600 | unsigned char alen, |
| 601 | unsigned char data[], |
| 602 | unsigned short len, |
| 603 | bool issue_stop) |
| 604 | { |
| 605 | int i, rv = 0; |
| 606 | |
| 607 | if (!(len + alen)) { |
| 608 | /* Writes of zero length not supported in auto mode. */ |
| 609 | debug("%s: zero length writes not supported\n", __func__); |
| 610 | return I2C_NOK; |
| 611 | } |
| 612 | |
| 613 | rv = hsi2c_prepare_transaction |
| 614 | (i2c, chip, len + alen, false, issue_stop); |
| 615 | if (rv != I2C_OK) |
| 616 | return rv; |
| 617 | |
| 618 | /* Move address, if any, and the data, if any, into the FIFO. */ |
| 619 | for (i = 0; i < alen; i++) { |
| 620 | rv = hsi2c_poll_fifo(i2c, false); |
| 621 | if (rv != I2C_OK) { |
| 622 | debug("%s: address write failed\n", __func__); |
| 623 | goto write_error; |
| 624 | } |
| 625 | writel(addr[i], &i2c->usi_txdata); |
| 626 | } |
| 627 | |
| 628 | for (i = 0; i < len; i++) { |
| 629 | rv = hsi2c_poll_fifo(i2c, false); |
| 630 | if (rv != I2C_OK) { |
| 631 | debug("%s: data write failed\n", __func__); |
| 632 | goto write_error; |
| 633 | } |
| 634 | writel(data[i], &i2c->usi_txdata); |
| 635 | } |
| 636 | |
| 637 | rv = hsi2c_wait_for_trx(i2c); |
| 638 | |
| 639 | write_error: |
| 640 | if (issue_stop) { |
| 641 | int tmp_ret = hsi2c_wait_while_busy(i2c); |
| 642 | if (rv == I2C_OK) |
| 643 | rv = tmp_ret; |
| 644 | } |
| 645 | |
| 646 | writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ |
| 647 | return rv; |
| 648 | } |
| 649 | |
| 650 | static int hsi2c_read(struct exynos5_hsi2c *i2c, |
| 651 | unsigned char chip, |
| 652 | unsigned char addr[], |
| 653 | unsigned char alen, |
| 654 | unsigned char data[], |
| 655 | unsigned short len) |
| 656 | { |
| 657 | int i, rv, tmp_ret; |
| 658 | bool drop_data = false; |
| 659 | |
| 660 | if (!len) { |
| 661 | /* Reads of zero length not supported in auto mode. */ |
| 662 | debug("%s: zero length read adjusted\n", __func__); |
| 663 | drop_data = true; |
| 664 | len = 1; |
| 665 | } |
| 666 | |
| 667 | if (alen) { |
| 668 | /* Internal register adress needs to be written first. */ |
| 669 | rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); |
| 670 | if (rv != I2C_OK) |
| 671 | return rv; |
| 672 | } |
| 673 | |
| 674 | rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); |
| 675 | |
| 676 | if (rv != I2C_OK) |
| 677 | return rv; |
| 678 | |
| 679 | for (i = 0; i < len; i++) { |
| 680 | rv = hsi2c_poll_fifo(i2c, true); |
| 681 | if (rv != I2C_OK) |
| 682 | goto read_err; |
| 683 | if (drop_data) |
| 684 | continue; |
| 685 | data[i] = readl(&i2c->usi_rxdata); |
| 686 | } |
| 687 | |
| 688 | rv = hsi2c_wait_for_trx(i2c); |
| 689 | |
| 690 | read_err: |
| 691 | tmp_ret = hsi2c_wait_while_busy(i2c); |
| 692 | if (rv == I2C_OK) |
| 693 | rv = tmp_ret; |
| 694 | |
| 695 | writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ |
| 696 | return rv; |
| 697 | } |
| 698 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 699 | static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap, |
| 700 | unsigned int speed) |
| 701 | { |
| 702 | struct s3c24x0_i2c_bus *i2c_bus; |
| 703 | |
| 704 | i2c_bus = get_bus(adap->hwadapnr); |
| 705 | if (!i2c_bus) |
| 706 | return -1; |
| 707 | |
| 708 | i2c_bus->clock_frequency = speed; |
| 709 | |
| 710 | if (i2c_bus->is_highspeed) { |
| 711 | if (hsi2c_get_clk_details(i2c_bus)) |
| 712 | return -1; |
| 713 | hsi2c_ch_init(i2c_bus); |
| 714 | } else { |
| 715 | i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, |
| 716 | CONFIG_SYS_I2C_S3C24X0_SLAVE); |
| 717 | } |
| 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 722 | /* |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 723 | * cmd_type is 0 for write, 1 for read. |
| 724 | * |
| 725 | * addr_len can take any value from 0-255, it is only limited |
| 726 | * by the char, we could make it larger if needed. If it is |
| 727 | * 0 we skip the address write cycle. |
| 728 | */ |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 729 | static int i2c_transfer(struct s3c24x0_i2c *i2c, |
| 730 | unsigned char cmd_type, |
| 731 | unsigned char chip, |
| 732 | unsigned char addr[], |
| 733 | unsigned char addr_len, |
| 734 | unsigned char data[], |
| 735 | unsigned short data_len) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 736 | { |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 737 | int i = 0, result; |
| 738 | ulong start_time = get_timer(0); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 739 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 740 | if (data == 0 || data_len == 0) { |
| 741 | /*Don't support data transfer of no length or to address 0 */ |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 742 | debug("i2c_transfer: bad call\n"); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 743 | return I2C_NOK; |
| 744 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 745 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 746 | while (readl(&i2c->iicstat) & I2CSTAT_BSY) { |
| 747 | if (get_timer(start_time) > I2C_TIMEOUT_MS) |
| 748 | return I2C_NOK_TOUT; |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 749 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 750 | |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 751 | writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 752 | |
| 753 | /* Get the slave chip address going */ |
| 754 | writel(chip, &i2c->iicds); |
| 755 | if ((cmd_type == I2C_WRITE) || (addr && addr_len)) |
| 756 | writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, |
| 757 | &i2c->iicstat); |
| 758 | else |
| 759 | writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, |
| 760 | &i2c->iicstat); |
| 761 | |
| 762 | /* Wait for chip address to transmit. */ |
| 763 | result = WaitForXfer(i2c); |
| 764 | if (result != I2C_OK) |
| 765 | goto bailout; |
| 766 | |
| 767 | /* If register address needs to be transmitted - do it now. */ |
| 768 | if (addr && addr_len) { |
| 769 | while ((i < addr_len) && (result == I2C_OK)) { |
| 770 | writel(addr[i++], &i2c->iicds); |
| 771 | ReadWriteByte(i2c); |
| 772 | result = WaitForXfer(i2c); |
| 773 | } |
| 774 | i = 0; |
| 775 | if (result != I2C_OK) |
| 776 | goto bailout; |
| 777 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 778 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 779 | switch (cmd_type) { |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 780 | case I2C_WRITE: |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 781 | while ((i < data_len) && (result == I2C_OK)) { |
| 782 | writel(data[i++], &i2c->iicds); |
| 783 | ReadWriteByte(i2c); |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 784 | result = WaitForXfer(i2c); |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 785 | } |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 786 | break; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 787 | |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 788 | case I2C_READ: |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 789 | if (addr && addr_len) { |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 790 | /* |
| 791 | * Register address has been sent, now send slave chip |
| 792 | * address again to start the actual read transaction. |
| 793 | */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 794 | writel(chip, &i2c->iicds); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 795 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 796 | /* Generate a re-START. */ |
Rajeshwari Shinde | cb466c0 | 2013-02-19 02:19:45 +0000 | [diff] [blame] | 797 | writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, |
| 798 | &i2c->iicstat); |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 799 | ReadWriteByte(i2c); |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 800 | result = WaitForXfer(i2c); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 801 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 802 | if (result != I2C_OK) |
| 803 | goto bailout; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 804 | } |
| 805 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 806 | while ((i < data_len) && (result == I2C_OK)) { |
| 807 | /* disable ACK for final READ */ |
| 808 | if (i == data_len - 1) |
| 809 | writel(readl(&i2c->iiccon) |
| 810 | & ~I2CCON_ACKGEN, |
| 811 | &i2c->iiccon); |
| 812 | ReadWriteByte(i2c); |
| 813 | result = WaitForXfer(i2c); |
| 814 | data[i++] = readl(&i2c->iicds); |
| 815 | } |
| 816 | if (result == I2C_NACK) |
| 817 | result = I2C_OK; /* Normal terminated read. */ |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 818 | break; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 819 | |
| 820 | default: |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 821 | debug("i2c_transfer: bad call\n"); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 822 | result = I2C_NOK; |
| 823 | break; |
| 824 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 825 | |
Naveen Krishna Ch | e4e2402 | 2013-10-15 16:01:43 +0530 | [diff] [blame] | 826 | bailout: |
| 827 | /* Send STOP. */ |
| 828 | writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); |
| 829 | ReadWriteByte(i2c); |
| 830 | |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 831 | return result; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 832 | } |
| 833 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 834 | static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 835 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 836 | struct s3c24x0_i2c_bus *i2c_bus; |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 837 | uchar buf[1]; |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 838 | int ret; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 839 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 840 | i2c_bus = get_bus(adap->hwadapnr); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 841 | if (!i2c_bus) |
| 842 | return -1; |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 843 | buf[0] = 0; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 844 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 845 | /* |
| 846 | * What is needed is to send the chip address and verify that the |
| 847 | * address was <ACK>ed (i.e. there was a chip at that address which |
| 848 | * drove the data line low). |
| 849 | */ |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 850 | if (i2c_bus->is_highspeed) { |
| 851 | ret = hsi2c_read(i2c_bus->hsregs, |
| 852 | chip, 0, 0, buf, 1); |
| 853 | } else { |
| 854 | ret = i2c_transfer(i2c_bus->regs, |
| 855 | I2C_READ, chip << 1, 0, 0, buf, 1); |
| 856 | } |
| 857 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 858 | return ret != I2C_OK; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 859 | } |
| 860 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 861 | static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
| 862 | int alen, uchar *buffer, int len) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 863 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 864 | struct s3c24x0_i2c_bus *i2c_bus; |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 865 | uchar xaddr[4]; |
| 866 | int ret; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 867 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 868 | if (alen > 4) { |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 869 | debug("I2C read: addr len %d not supported\n", alen); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 870 | return 1; |
| 871 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 872 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 873 | if (alen > 0) { |
| 874 | xaddr[0] = (addr >> 24) & 0xFF; |
| 875 | xaddr[1] = (addr >> 16) & 0xFF; |
| 876 | xaddr[2] = (addr >> 8) & 0xFF; |
| 877 | xaddr[3] = addr & 0xFF; |
| 878 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 879 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 880 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 881 | /* |
| 882 | * EEPROM chips that implement "address overflow" are ones |
| 883 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 884 | * address and the extra bits end up in the "chip address" |
| 885 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 886 | * four 256 byte chips. |
| 887 | * |
| 888 | * Note that we consider the length of the address field to |
| 889 | * still be one byte because the extra address bits are |
| 890 | * hidden in the chip address. |
| 891 | */ |
| 892 | if (alen > 0) |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 893 | chip |= ((addr >> (alen * 8)) & |
| 894 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 895 | #endif |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 896 | i2c_bus = get_bus(adap->hwadapnr); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 897 | if (!i2c_bus) |
| 898 | return -1; |
| 899 | |
| 900 | if (i2c_bus->is_highspeed) |
| 901 | ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen], |
| 902 | alen, buffer, len); |
| 903 | else |
| 904 | ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, |
| 905 | &xaddr[4 - alen], alen, buffer, len); |
| 906 | |
| 907 | if (ret) { |
| 908 | if (i2c_bus->is_highspeed) |
| 909 | exynos5_i2c_reset(i2c_bus); |
| 910 | debug("I2c read failed %d\n", ret); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 911 | return 1; |
| 912 | } |
| 913 | return 0; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 914 | } |
| 915 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 916 | static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
| 917 | int alen, uchar *buffer, int len) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 918 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 919 | struct s3c24x0_i2c_bus *i2c_bus; |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 920 | uchar xaddr[4]; |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 921 | int ret; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 922 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 923 | if (alen > 4) { |
Rajeshwari Shinde | ab7e52b | 2012-07-23 21:23:53 +0000 | [diff] [blame] | 924 | debug("I2C write: addr len %d not supported\n", alen); |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 925 | return 1; |
| 926 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 927 | |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 928 | if (alen > 0) { |
| 929 | xaddr[0] = (addr >> 24) & 0xFF; |
| 930 | xaddr[1] = (addr >> 16) & 0xFF; |
| 931 | xaddr[2] = (addr >> 8) & 0xFF; |
| 932 | xaddr[3] = addr & 0xFF; |
| 933 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 934 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
wdenk | fc3e216 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 935 | /* |
| 936 | * EEPROM chips that implement "address overflow" are ones |
| 937 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 938 | * address and the extra bits end up in the "chip address" |
| 939 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 940 | * four 256 byte chips. |
| 941 | * |
| 942 | * Note that we consider the length of the address field to |
| 943 | * still be one byte because the extra address bits are |
| 944 | * hidden in the chip address. |
| 945 | */ |
| 946 | if (alen > 0) |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 947 | chip |= ((addr >> (alen * 8)) & |
| 948 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 949 | #endif |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 950 | i2c_bus = get_bus(adap->hwadapnr); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 951 | if (!i2c_bus) |
| 952 | return -1; |
| 953 | |
| 954 | if (i2c_bus->is_highspeed) |
| 955 | ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen], |
| 956 | alen, buffer, len, true); |
| 957 | else |
| 958 | ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1, |
| 959 | &xaddr[4 - alen], alen, buffer, len); |
| 960 | |
| 961 | if (ret != 0) { |
| 962 | if (i2c_bus->is_highspeed) |
| 963 | exynos5_i2c_reset(i2c_bus); |
| 964 | return 1; |
| 965 | } else { |
| 966 | return 0; |
| 967 | } |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 968 | } |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 969 | |
Amar | 1ae76d4 | 2013-07-10 10:42:29 +0530 | [diff] [blame] | 970 | #ifdef CONFIG_OF_CONTROL |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 971 | static void process_nodes(const void *blob, int node_list[], int count, |
| 972 | int is_highspeed) |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 973 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 974 | struct s3c24x0_i2c_bus *bus; |
Amar | 2c07bb9 | 2013-04-04 02:27:06 -0400 | [diff] [blame] | 975 | int i; |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 976 | |
| 977 | for (i = 0; i < count; i++) { |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 978 | int node = node_list[i]; |
| 979 | |
| 980 | if (node <= 0) |
| 981 | continue; |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 982 | |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 983 | bus = &i2c_bus[i]; |
Simon Glass | 940dd16 | 2013-10-15 16:02:10 +0530 | [diff] [blame] | 984 | bus->active = true; |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 985 | bus->is_highspeed = is_highspeed; |
| 986 | |
| 987 | if (is_highspeed) |
| 988 | bus->hsregs = (struct exynos5_hsi2c *) |
| 989 | fdtdec_get_addr(blob, node, "reg"); |
| 990 | else |
| 991 | bus->regs = (struct s3c24x0_i2c *) |
| 992 | fdtdec_get_addr(blob, node, "reg"); |
| 993 | |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 994 | bus->id = pinmux_decode_periph_id(blob, node); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 995 | bus->clock_frequency = fdtdec_get_int(blob, node, |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 996 | "clock-frequency", |
| 997 | CONFIG_SYS_I2C_S3C24X0_SPEED); |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 998 | bus->node = node; |
Simon Glass | 940dd16 | 2013-10-15 16:02:10 +0530 | [diff] [blame] | 999 | bus->bus_num = i; |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1000 | exynos_pinmux_config(bus->id, 0); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1001 | |
| 1002 | /* Mark position as used */ |
| 1003 | node_list[i] = -1; |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1004 | } |
| 1005 | } |
| 1006 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1007 | void board_i2c_init(const void *blob) |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1008 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1009 | int node_list[CONFIG_MAX_I2C_NUM]; |
| 1010 | int count; |
Simon Glass | 940dd16 | 2013-10-15 16:02:10 +0530 | [diff] [blame] | 1011 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1012 | /* First get the normal i2c ports */ |
| 1013 | count = fdtdec_find_aliases_for_id(blob, "i2c", |
| 1014 | COMPAT_SAMSUNG_S3C2440_I2C, node_list, |
| 1015 | CONFIG_MAX_I2C_NUM); |
| 1016 | process_nodes(blob, node_list, count, 0); |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1017 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1018 | /* Now look for high speed i2c ports */ |
| 1019 | count = fdtdec_find_aliases_for_id(blob, "i2c", |
| 1020 | COMPAT_SAMSUNG_EXYNOS5_I2C, node_list, |
| 1021 | CONFIG_MAX_I2C_NUM); |
| 1022 | process_nodes(blob, node_list, count, 1); |
| 1023 | |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1024 | } |
| 1025 | |
| 1026 | int i2c_get_bus_num_fdt(int node) |
| 1027 | { |
| 1028 | int i; |
| 1029 | |
Simon Glass | 940dd16 | 2013-10-15 16:02:10 +0530 | [diff] [blame] | 1030 | for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1031 | if (node == i2c_bus[i].node) |
| 1032 | return i; |
| 1033 | } |
| 1034 | |
| 1035 | debug("%s: Can't find any matched I2C bus\n", __func__); |
| 1036 | return -1; |
| 1037 | } |
| 1038 | |
| 1039 | int i2c_reset_port_fdt(const void *blob, int node) |
| 1040 | { |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1041 | struct s3c24x0_i2c_bus *i2c_bus; |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1042 | int bus; |
| 1043 | |
| 1044 | bus = i2c_get_bus_num_fdt(node); |
| 1045 | if (bus < 0) { |
| 1046 | debug("could not get bus for node %d\n", node); |
| 1047 | return -1; |
| 1048 | } |
| 1049 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1050 | i2c_bus = get_bus(bus); |
| 1051 | if (!i2c_bus) { |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1052 | debug("get_bus() failed for node node %d\n", node); |
| 1053 | return -1; |
| 1054 | } |
| 1055 | |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1056 | if (i2c_bus->is_highspeed) { |
| 1057 | if (hsi2c_get_clk_details(i2c_bus)) |
| 1058 | return -1; |
| 1059 | hsi2c_ch_init(i2c_bus); |
| 1060 | } else { |
| 1061 | i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 1062 | CONFIG_SYS_I2C_S3C24X0_SLAVE); |
Naveen Krishna Ch | 296a461 | 2013-10-15 16:02:44 +0530 | [diff] [blame] | 1063 | } |
Rajeshwari Shinde | a9d2ae7 | 2012-12-26 20:03:12 +0000 | [diff] [blame] | 1064 | |
| 1065 | return 0; |
| 1066 | } |
| 1067 | #endif |
| 1068 | |
Piotr Wilczek | 2d8f1e2 | 2013-11-20 10:43:49 +0100 | [diff] [blame^] | 1069 | /* |
| 1070 | * Register s3c24x0 i2c adapters |
| 1071 | */ |
| 1072 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1073 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1074 | s3c24x0_i2c_set_bus_speed, |
| 1075 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1076 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1077 | 0) |
| 1078 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1079 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1080 | s3c24x0_i2c_set_bus_speed, |
| 1081 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1082 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1083 | 1) |
| 1084 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1085 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1086 | s3c24x0_i2c_set_bus_speed, |
| 1087 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1088 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1089 | 2) |
| 1090 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1091 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1092 | s3c24x0_i2c_set_bus_speed, |
| 1093 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1094 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1095 | 3) |
| 1096 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1097 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1098 | s3c24x0_i2c_set_bus_speed, |
| 1099 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1100 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1101 | 4) |
| 1102 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1103 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1104 | s3c24x0_i2c_set_bus_speed, |
| 1105 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1106 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1107 | 5) |
| 1108 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1109 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1110 | s3c24x0_i2c_set_bus_speed, |
| 1111 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1112 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1113 | 6) |
| 1114 | U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe, |
| 1115 | s3c24x0_i2c_read, s3c24x0_i2c_write, |
| 1116 | s3c24x0_i2c_set_bus_speed, |
| 1117 | CONFIG_SYS_I2C_S3C24X0_SPEED, |
| 1118 | CONFIG_SYS_I2C_S3C24X0_SLAVE, |
| 1119 | 7) |