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Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09001/*
2 * SuperH SCIF device driver.
Nobuhiro Iwamatsuac331da2008-01-17 15:53:52 +09003 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
Wolfgang Denk61fb15c52007-12-27 01:52:50 +01004 *
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09005 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <common.h>
21#include <asm/processor.h>
22
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090023#if defined(CONFIG_CONS_SCIF0)
24# define SCIF_BASE SCIF0_BASE
25#elif defined(CONFIG_CONS_SCIF1)
26# define SCIF_BASE SCIF1_BASE
27#elif defined(CONFIG_CONS_SCIF2)
28# define SCIF_BASE SCIF2_BASE
29#elif defined(CONFIG_CONS_SCIF3)
30# define SCIF_BASE SCIF3_BASE
31#elif defined(CONFIG_CONS_SCIF4)
32# define SCIF_BASE SCIF4_BASE
33#elif defined(CONFIG_CONS_SCIF5)
34# define SCIF_BASE SCIF5_BASE
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090035#else
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090036# error "Default SCIF doesn't set....."
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090037#endif
38
Nobuhiro Iwamatsu76e49aa2008-01-15 23:25:25 +090039/* Base register */
40#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
41#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
42#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
43#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
44#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090045#if defined(CONFIG_CPU_SH7720) || \
46 (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090047# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090048# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
49# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
Yoshihiro Shimoda7c10c572008-01-09 14:30:02 +090050#else
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090051# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090052# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090053# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
Yoshihiro Shimoda7c10c572008-01-09 14:30:02 +090054#endif
55
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090056#if defined(CONFIG_CPU_SH7780) || \
Yusuke Godab55523e2008-03-05 14:23:26 +090057 defined(CONFIG_CPU_SH7785)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090058# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
59# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020060# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090061# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
62# define LSR_ORER 1
63# define FIFOLEVEL_MASK 0xFF
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090064#elif defined(CONFIG_CPU_SH7763)
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090065# if defined(CONFIG_CONS_SCIF2)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090066# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
67# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
68# define LSR_ORER 1
69# define FIFOLEVEL_MASK 0x1F
70# else
71# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
72# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
73# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
74# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
75# define LSR_ORER 1
76# define FIFOLEVEL_MASK 0xFF
77# endif
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090078#elif defined(CONFIG_CPU_SH7723)
79# if defined(CONIFG_SCIF_A)
80# define SCLSR SCFSR
81# define LSR_ORER 0x0200
82# define FIFOLEVEL_MASK 0x3F
83#else
84# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
85# define LSR_ORER 1
86# define FIFOLEVEL_MASK 0x1F
87#endif
Yusuke Godab55523e2008-03-05 14:23:26 +090088#elif defined(CONFIG_CPU_SH7750) || \
Nobuhiro Iwamatsu56693322008-03-12 12:10:28 +090089 defined(CONFIG_CPU_SH7751) || \
Nobuhiro Iwamatsu6ede7532008-07-03 23:11:02 +090090 defined(CONFIG_CPU_SH7722) || \
91 defined(CONFIG_CPU_SH7203)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020092# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090093# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090094# define LSR_ORER 1
95# define FIFOLEVEL_MASK 0x1F
Yusuke Godab55523e2008-03-05 14:23:26 +090096#elif defined(CONFIG_CPU_SH7720)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +090097# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +090098# define LSR_ORER 0x0200
99# define FIFOLEVEL_MASK 0x1F
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900100#elif defined(CONFIG_CPU_SH7710) || \
Yusuke Godab55523e2008-03-05 14:23:26 +0900101 defined(CONFIG_CPU_SH7712)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900102# define SCLSR SCFSR /* SCSSR */
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +0900103# define LSR_ORER 1
104# define FIFOLEVEL_MASK 0x1F
Nobuhiro Iwamatsuac331da2008-01-17 15:53:52 +0900105#endif
Nobuhiro Iwamatsuac331da2008-01-17 15:53:52 +0900106
Yusuke Godab55523e2008-03-05 14:23:26 +0900107/* SCBRR register value setting */
Nobuhiro Iwamatsuac331da2008-01-17 15:53:52 +0900108#if defined(CONFIG_CPU_SH7720)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +0900109# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +0900110#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
111/* SH7723 SCIFA use bus clock. So clock *2 */
112# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900113#else /* Generic SuperH */
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +0900114# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900115#endif
116
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900117#define SCR_RE (1 << 4)
118#define SCR_TE (1 << 5)
119#define FCR_RFRST (1 << 1) /* RFCL */
120#define FCR_TFRST (1 << 2) /* TFCL */
121#define FSR_DR (1 << 0)
122#define FSR_RDF (1 << 1)
123#define FSR_FER (1 << 3)
124#define FSR_BRK (1 << 4)
125#define FSR_FER (1 << 3)
126#define FSR_TEND (1 << 6)
127#define FSR_ER (1 << 7)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900128
129/*----------------------------------------------------------------------*/
130
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900131void serial_setbrg(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900132{
133 DECLARE_GLOBAL_DATA_PTR;
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900134 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900135}
136
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900137int serial_init(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900138{
139 *SCSCR = (SCR_RE | SCR_TE);
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900140 *SCSMR = 0;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900141 *SCSMR = 0;
142 *SCFCR = (FCR_RFRST | FCR_TFRST);
143 *SCFCR;
144 *SCFCR = 0;
145
146 serial_setbrg();
147 return 0;
148}
149
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900150static int serial_rx_fifo_level(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900151{
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900152#if defined(SCRFDR)
Nobuhiro Iwamatsu3ecff1d2008-03-06 14:05:53 +0900153 return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
154#else
155 return (*SCFDR >> 0) & FIFOLEVEL_MASK;
156#endif
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900157}
158
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900159void serial_raw_putc(const char c)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900160{
161 unsigned int fsr_bits_to_clear;
162
163 while (1) {
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900164 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900165 fsr_bits_to_clear = FSR_TEND;
166 break;
167 }
168 }
169
170 *SCFTDR = c;
171 if (fsr_bits_to_clear != 0)
172 *SCFSR &= ~fsr_bits_to_clear;
173}
174
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900175void serial_putc(const char c)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900176{
177 if (c == '\n')
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900178 serial_raw_putc('\r');
179 serial_raw_putc(c);
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900180}
181
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900182void serial_puts(const char *s)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900183{
184 char c;
185 while ((c = *s++) != 0)
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900186 serial_putc(c);
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900187}
188
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900189int serial_tstc(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900190{
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +0900191 return serial_rx_fifo_level() ? 1 : 0;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900192}
193
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900194#define FSR_ERR_CLEAR 0x0063
195#define RDRF_CLEAR 0x00fc
196void handle_error(void)
197{
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900198
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900199 (void)*SCFSR;
200 *SCFSR = FSR_ERR_CLEAR;
201 (void)*SCLSR;
202 *SCLSR = 0x00;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900203}
204
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900205int serial_getc_check(void)
206{
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900207 unsigned short status;
208
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900209 status = *SCFSR;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900210
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900211 if (status & (FSR_FER | FSR_ER | FSR_BRK))
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900212 handle_error();
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900213 if (*SCLSR & LSR_ORER)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900214 handle_error();
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +0900215 return status & (FSR_DR | FSR_RDF);
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900216}
217
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900218int serial_getc(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900219{
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900220 unsigned short status;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900221 char ch;
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +0900222
223 while (!serial_getc_check())
224 ;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900225
226 ch = *SCFRDR;
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900227 status = *SCFSR;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900228
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900229 *SCFSR = RDRF_CLEAR;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900230
231 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
232 handle_error();
233
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900234 if (*SCLSR & LSR_ORER)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900235 handle_error();
236
Nobuhiro Iwamatsu08c5fab2008-06-06 16:16:08 +0900237 return ch;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +0900238}