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Ian Campbellcba69ee2014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some board init for the Allwinner A10-evb board.
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
Hans de Goedee79c7c82014-10-02 21:13:54 +020015#include <mmc.h>
Hans de Goede24289202014-06-13 22:55:51 +020016#ifdef CONFIG_AXP152_POWER
17#include <axp152.h>
18#endif
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +020019#ifdef CONFIG_AXP209_POWER
20#include <axp209.h>
21#endif
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +020022#ifdef CONFIG_AXP221_POWER
23#include <axp221.h>
24#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +010025#include <asm/arch/clock.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020026#include <asm/arch/cpu.h>
Luc Verhaegen2d7a0842014-08-13 07:55:07 +020027#include <asm/arch/display.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010028#include <asm/arch/dram.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010029#include <asm/arch/gpio.h>
30#include <asm/arch/mmc.h>
Hans de Goede2aacc422015-04-27 15:05:10 +020031#include <asm/arch/usb_phy.h>
Hans de Goede4f7e01c2015-04-23 23:23:50 +020032#include <asm/gpio.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020033#include <asm/io.h>
Hans de Goede1a800f72015-01-11 17:17:00 +010034#include <linux/usb/musb.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020035#include <net.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010036
Hans de Goede55410082015-02-16 17:23:25 +010037#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39int soft_i2c_gpio_sda;
40int soft_i2c_gpio_scl;
Hans de Goede4f7e01c2015-04-23 23:23:50 +020041
42static int soft_i2c_board_init(void)
43{
44 int ret;
45
46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
47 if (soft_i2c_gpio_sda < 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
50 return soft_i2c_gpio_sda;
51 }
52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
53 if (ret) {
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
56 return ret;
57 }
58
59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
60 if (soft_i2c_gpio_scl < 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
63 return soft_i2c_gpio_scl;
64 }
65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
66 if (ret) {
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
69 return ret;
70 }
71
72 return 0;
73}
74#else
75static int soft_i2c_board_init(void) { return 0; }
Hans de Goede55410082015-02-16 17:23:25 +010076#endif
77
Ian Campbellcba69ee2014-05-05 11:52:26 +010078DECLARE_GLOBAL_DATA_PTR;
79
80/* add board specific code here */
81int board_init(void)
82{
Hans de Goede2fcf0332015-04-25 17:25:14 +020083 int id_pfr1, ret;
Ian Campbellcba69ee2014-05-05 11:52:26 +010084
85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
86
87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
88 debug("id_pfr1: 0x%08x\n", id_pfr1);
89 /* Generic Timer Extension available? */
90 if ((id_pfr1 >> 16) & 0xf) {
91 debug("Setting CNTFRQ\n");
92 /* CNTFRQ == 24 MHz */
93 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
94 }
95
Hans de Goede2fcf0332015-04-25 17:25:14 +020096 ret = axp_gpio_init();
97 if (ret)
98 return ret;
99
Hans de Goede4f7e01c2015-04-23 23:23:50 +0200100 /* Uses dm gpio code so do this here and not in i2c_init_board() */
101 return soft_i2c_board_init();
Ian Campbellcba69ee2014-05-05 11:52:26 +0100102}
103
104int dram_init(void)
105{
106 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
107
108 return 0;
109}
110
Ian Campbelle24ea552014-05-05 14:42:31 +0100111#ifdef CONFIG_GENERIC_MMC
112static void mmc_pinmux_setup(int sdc)
113{
114 unsigned int pin;
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100115 __maybe_unused int pins;
Ian Campbelle24ea552014-05-05 14:42:31 +0100116
117 switch (sdc) {
118 case 0:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100119 /* SDC0: PF0-PF5 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100120 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100121 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100122 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
123 sunxi_gpio_set_drv(pin, 2);
124 }
125 break;
126
127 case 1:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100128 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
129
130#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
131 if (pins == SUNXI_GPIO_H) {
132 /* SDC1: PH22-PH-27 */
133 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
134 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
135 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
136 sunxi_gpio_set_drv(pin, 2);
137 }
138 } else {
139 /* SDC1: PG0-PG5 */
140 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
141 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
142 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
143 sunxi_gpio_set_drv(pin, 2);
144 }
145 }
146#elif defined(CONFIG_MACH_SUN5I)
147 /* SDC1: PG3-PG8 */
Hans de Goedebbff84b2014-10-03 16:44:57 +0200148 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100149 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
Ian Campbelle24ea552014-05-05 14:42:31 +0100150 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
151 sunxi_gpio_set_drv(pin, 2);
152 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100153#elif defined(CONFIG_MACH_SUN6I)
154 /* SDC1: PG0-PG5 */
155 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
156 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
157 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
158 sunxi_gpio_set_drv(pin, 2);
159 }
160#elif defined(CONFIG_MACH_SUN8I)
161 if (pins == SUNXI_GPIO_D) {
162 /* SDC1: PD2-PD7 */
163 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
164 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
165 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
166 sunxi_gpio_set_drv(pin, 2);
167 }
168 } else {
169 /* SDC1: PG0-PG5 */
170 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
171 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
172 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
173 sunxi_gpio_set_drv(pin, 2);
174 }
175 }
176#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100177 break;
178
179 case 2:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100180 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
181
182#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
183 /* SDC2: PC6-PC11 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100184 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100185 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100186 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
187 sunxi_gpio_set_drv(pin, 2);
188 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100189#elif defined(CONFIG_MACH_SUN5I)
190 if (pins == SUNXI_GPIO_E) {
191 /* SDC2: PE4-PE9 */
192 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
193 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
194 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
195 sunxi_gpio_set_drv(pin, 2);
196 }
197 } else {
198 /* SDC2: PC6-PC15 */
199 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
200 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
201 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
202 sunxi_gpio_set_drv(pin, 2);
203 }
204 }
205#elif defined(CONFIG_MACH_SUN6I)
206 if (pins == SUNXI_GPIO_A) {
207 /* SDC2: PA9-PA14 */
208 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
209 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
210 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
211 sunxi_gpio_set_drv(pin, 2);
212 }
213 } else {
214 /* SDC2: PC6-PC15, PC24 */
215 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
216 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
217 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
218 sunxi_gpio_set_drv(pin, 2);
219 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100220
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100221 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
222 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
223 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
224 }
225#elif defined(CONFIG_MACH_SUN8I)
226 /* SDC2: PC5-PC6, PC8-PC16 */
227 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
228 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100229 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
230 sunxi_gpio_set_drv(pin, 2);
231 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100232
233 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
234 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
235 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
236 sunxi_gpio_set_drv(pin, 2);
237 }
238#endif
239 break;
240
241 case 3:
242 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
243
244#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
245 /* SDC3: PI4-PI9 */
246 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
247 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
248 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
249 sunxi_gpio_set_drv(pin, 2);
250 }
251#elif defined(CONFIG_MACH_SUN6I)
252 if (pins == SUNXI_GPIO_A) {
253 /* SDC3: PA9-PA14 */
254 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
255 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
256 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
257 sunxi_gpio_set_drv(pin, 2);
258 }
259 } else {
260 /* SDC3: PC6-PC15, PC24 */
261 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
262 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
263 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
264 sunxi_gpio_set_drv(pin, 2);
265 }
266
267 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
268 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
269 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
270 }
271#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100272 break;
273
274 default:
275 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
276 break;
277 }
278}
279
280int board_mmc_init(bd_t *bis)
281{
Hans de Goedee79c7c82014-10-02 21:13:54 +0200282 __maybe_unused struct mmc *mmc0, *mmc1;
283 __maybe_unused char buf[512];
284
Ian Campbelle24ea552014-05-05 14:42:31 +0100285 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200286 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
287 if (!mmc0)
288 return -1;
289
Hans de Goede2ccfac02014-10-02 20:43:50 +0200290#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
Ian Campbelle24ea552014-05-05 14:42:31 +0100291 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200292 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
293 if (!mmc1)
294 return -1;
295#endif
296
297#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
298 /*
299 * Both mmc0 and mmc2 are bootable, figure out where we're booting
300 * from. Try mmc0 first, just like the brom does.
301 */
302 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
303 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
304 buf[12] = 0;
305 if (strcmp(&buf[4], "eGON.BT0") == 0)
306 return 0;
307 }
308
309 /* no bootable card in mmc0, so we must be booting from mmc2, swap */
310 mmc0->block_dev.dev = 1;
311 mmc1->block_dev.dev = 0;
Ian Campbelle24ea552014-05-05 14:42:31 +0100312#endif
313
314 return 0;
315}
316#endif
317
Hans de Goede66203772014-06-13 22:55:49 +0200318void i2c_init_board(void)
319{
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200320#ifdef CONFIG_I2C0_ENABLE
321#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
322 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
323 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
Hans de Goede66203772014-06-13 22:55:49 +0200324 clock_twi_onoff(0, 1);
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200325#elif defined(CONFIG_MACH_SUN6I)
326 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
327 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
328 clock_twi_onoff(0, 1);
329#elif defined(CONFIG_MACH_SUN8I)
330 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
331 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
332 clock_twi_onoff(0, 1);
333#endif
334#endif
335
336#ifdef CONFIG_I2C1_ENABLE
337#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
338 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
339 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
340 clock_twi_onoff(1, 1);
341#elif defined(CONFIG_MACH_SUN5I)
342 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
343 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
344 clock_twi_onoff(1, 1);
345#elif defined(CONFIG_MACH_SUN6I)
346 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
347 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
348 clock_twi_onoff(1, 1);
349#elif defined(CONFIG_MACH_SUN8I)
350 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
351 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
352 clock_twi_onoff(1, 1);
353#endif
354#endif
355
356#ifdef CONFIG_I2C2_ENABLE
357#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
358 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
359 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
360 clock_twi_onoff(2, 1);
361#elif defined(CONFIG_MACH_SUN5I)
362 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
363 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
364 clock_twi_onoff(2, 1);
365#elif defined(CONFIG_MACH_SUN6I)
366 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
367 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
368 clock_twi_onoff(2, 1);
369#elif defined(CONFIG_MACH_SUN8I)
370 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
371 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
372 clock_twi_onoff(2, 1);
373#endif
374#endif
375
376#ifdef CONFIG_I2C3_ENABLE
377#if defined(CONFIG_MACH_SUN6I)
378 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
379 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
380 clock_twi_onoff(3, 1);
381#elif defined(CONFIG_MACH_SUN7I)
382 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
383 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
384 clock_twi_onoff(3, 1);
385#endif
386#endif
387
388#ifdef CONFIG_I2C4_ENABLE
389#if defined(CONFIG_MACH_SUN7I)
390 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
391 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
392 clock_twi_onoff(4, 1);
393#endif
394#endif
Hans de Goede66203772014-06-13 22:55:49 +0200395}
396
Ian Campbellcba69ee2014-05-05 11:52:26 +0100397#ifdef CONFIG_SPL_BUILD
398void sunxi_board_init(void)
399{
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200400 int power_failed = 0;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100401 unsigned long ramsize;
402
Hans de Goede24289202014-06-13 22:55:51 +0200403#ifdef CONFIG_AXP152_POWER
404 power_failed = axp152_init();
405 power_failed |= axp152_set_dcdc2(1400);
406 power_failed |= axp152_set_dcdc3(1500);
407 power_failed |= axp152_set_dcdc4(1250);
408 power_failed |= axp152_set_ldo2(3000);
409#endif
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200410#ifdef CONFIG_AXP209_POWER
411 power_failed |= axp209_init();
412 power_failed |= axp209_set_dcdc2(1400);
413 power_failed |= axp209_set_dcdc3(1250);
414 power_failed |= axp209_set_ldo2(3000);
415 power_failed |= axp209_set_ldo3(2800);
416 power_failed |= axp209_set_ldo4(2800);
417#endif
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200418#ifdef CONFIG_AXP221_POWER
419 power_failed = axp221_init();
Hans de Goede1262a852014-12-13 14:12:06 +0100420 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
Hans de Goeded3a96f72014-12-13 14:20:09 +0100421 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
422 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
423#ifdef CONFIG_MACH_SUN6I
424 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
425#else
426 power_failed |= axp221_set_dcdc4(0); /* A23:unused */
427#endif
428 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200429 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200430 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200431 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200432 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200433 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
Siarhei Siamashka6906df12015-01-19 05:23:30 +0200434 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200435#endif
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200436
Ian Campbellcba69ee2014-05-05 11:52:26 +0100437 printf("DRAM:");
438 ramsize = sunxi_dram_init();
439 printf(" %lu MiB\n", ramsize >> 20);
440 if (!ramsize)
441 hang();
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200442
443 /*
444 * Only clock up the CPU to full speed if we are reasonably
445 * assured it's being powered with suitable core voltage
446 */
447 if (!power_failed)
Iain Patone71b4222015-03-28 10:26:38 +0000448 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200449 else
450 printf("Failed to set core voltage! Can't set CPU frequency\n");
Ian Campbellcba69ee2014-05-05 11:52:26 +0100451}
452#endif
Jonathan Liub41d7d02014-06-14 08:59:09 +0200453
Hans de Goede1a800f72015-01-11 17:17:00 +0100454#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
Hans de Goede7b798652015-04-27 14:54:47 +0200455extern const struct musb_platform_ops sunxi_musb_ops;
456
Hans de Goede1a800f72015-01-11 17:17:00 +0100457static struct musb_hdrc_config musb_config = {
458 .multipoint = 1,
459 .dyn_fifo = 1,
460 .num_eps = 6,
461 .ram_bits = 11,
462};
463
464static struct musb_hdrc_platform_data musb_plat = {
465#if defined(CONFIG_MUSB_HOST)
466 .mode = MUSB_HOST,
467#else
468 .mode = MUSB_PERIPHERAL,
469#endif
470 .config = &musb_config,
471 .power = 250,
472 .platform_ops = &sunxi_musb_ops,
473};
474#endif
475
Paul Kocialkowskif1df7582015-03-22 18:07:13 +0100476#ifdef CONFIG_USB_GADGET
477int g_dnl_board_usb_cable_connected(void)
478{
479 return sunxi_usbc_vbus_detect(0);
480}
481#endif
482
Jonathan Liub41d7d02014-06-14 08:59:09 +0200483#ifdef CONFIG_MISC_INIT_R
484int misc_init_r(void)
485{
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100486 char serial_string[17] = { 0 };
Hans de Goedecac5b1c2014-11-26 00:04:24 +0100487 unsigned int sid[4];
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100488 uint8_t mac_addr[6];
489 int ret;
Jonathan Liub41d7d02014-06-14 08:59:09 +0200490
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100491 ret = sunxi_get_sid(sid);
492 if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
493 if (!getenv("ethaddr")) {
494 /* Non OUI / registered MAC address */
495 mac_addr[0] = 0x02;
496 mac_addr[1] = (sid[0] >> 0) & 0xff;
497 mac_addr[2] = (sid[3] >> 24) & 0xff;
498 mac_addr[3] = (sid[3] >> 16) & 0xff;
499 mac_addr[4] = (sid[3] >> 8) & 0xff;
500 mac_addr[5] = (sid[3] >> 0) & 0xff;
Jonathan Liub41d7d02014-06-14 08:59:09 +0200501
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100502 eth_setenv_enetaddr("ethaddr", mac_addr);
503 }
Jonathan Liub41d7d02014-06-14 08:59:09 +0200504
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100505 if (!getenv("serial#")) {
506 snprintf(serial_string, sizeof(serial_string),
507 "%08x%08x", sid[0], sid[3]);
508
509 setenv("serial#", serial_string);
510 }
Jonathan Liub41d7d02014-06-14 08:59:09 +0200511 }
512
Hans de Goedee13afee2015-04-27 16:50:04 +0200513 ret = sunxi_usb_phy_probe();
514 if (ret)
515 return ret;
516
Hans de Goede1a800f72015-01-11 17:17:00 +0100517#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
518 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
519#endif
Jonathan Liub41d7d02014-06-14 08:59:09 +0200520 return 0;
521}
522#endif
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200523
524#ifdef CONFIG_OF_BOARD_SETUP
525int ft_board_setup(void *blob, bd_t *bd)
526{
527#ifdef CONFIG_VIDEO_DT_SIMPLEFB
528 return sunxi_simplefb_setup(blob);
529#endif
530}
531#endif /* CONFIG_OF_BOARD_SETUP */