Stefan Roese | 8b7d1f0 | 2007-01-31 16:37:34 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * pf5200.c - main board support/init for the esd pf5200. |
| 29 | */ |
| 30 | |
| 31 | #include <common.h> |
| 32 | #include <mpc5xxx.h> |
| 33 | #include <pci.h> |
| 34 | #include <command.h> |
| 35 | |
| 36 | #include "mt46v16m16-75.h" |
| 37 | |
| 38 | void init_power_switch(void); |
| 39 | |
| 40 | static void sdram_start(int hi_addr) |
| 41 | { |
| 42 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 43 | |
| 44 | /* unlock mode register */ |
| 45 | *(vu_long *) MPC5XXX_SDRAM_CTRL = |
| 46 | SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
| 47 | __asm__ volatile ("sync"); |
| 48 | |
| 49 | /* precharge all banks */ |
| 50 | *(vu_long *) MPC5XXX_SDRAM_CTRL = |
| 51 | SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 52 | __asm__ volatile ("sync"); |
| 53 | |
| 54 | /* set mode register: extended mode */ |
| 55 | *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
| 56 | __asm__ volatile ("sync"); |
| 57 | |
| 58 | /* set mode register: reset DLL */ |
| 59 | *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
| 60 | __asm__ volatile ("sync"); |
| 61 | |
| 62 | /* precharge all banks */ |
| 63 | *(vu_long *) MPC5XXX_SDRAM_CTRL = |
| 64 | SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
| 65 | __asm__ volatile ("sync"); |
| 66 | |
| 67 | /* auto refresh */ |
| 68 | *(vu_long *) MPC5XXX_SDRAM_CTRL = |
| 69 | SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
| 70 | __asm__ volatile ("sync"); |
| 71 | |
| 72 | /* set mode register */ |
| 73 | *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
| 74 | __asm__ volatile ("sync"); |
| 75 | |
| 76 | /* normal operation */ |
| 77 | *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
| 78 | __asm__ volatile ("sync"); |
| 79 | } |
| 80 | |
| 81 | /* |
| 82 | * ATTENTION: Although partially referenced initdram does NOT make real use |
| 83 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
| 84 | * is something else than 0x00000000. |
| 85 | */ |
| 86 | |
| 87 | long int initdram(int board_type) |
| 88 | { |
| 89 | ulong dramsize = 0; |
| 90 | ulong test1, test2; |
| 91 | |
| 92 | /* setup SDRAM chip selects */ |
| 93 | *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ |
| 94 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |
| 95 | __asm__ volatile ("sync"); |
| 96 | |
| 97 | /* setup config registers */ |
| 98 | *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
| 99 | *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
| 100 | __asm__ volatile ("sync"); |
| 101 | |
| 102 | /* set tap delay */ |
| 103 | *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
| 104 | __asm__ volatile ("sync"); |
| 105 | |
| 106 | /* find RAM size using SDRAM CS0 only */ |
| 107 | sdram_start(0); |
| 108 | test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); |
| 109 | sdram_start(1); |
| 110 | test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); |
| 111 | |
| 112 | if (test1 > test2) { |
| 113 | sdram_start(0); |
| 114 | dramsize = test1; |
| 115 | } else { |
| 116 | dramsize = test2; |
| 117 | } |
| 118 | |
| 119 | /* memory smaller than 1MB is impossible */ |
| 120 | if (dramsize < (1 << 20)) |
| 121 | dramsize = 0; |
| 122 | |
| 123 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 124 | if (dramsize > 0) { |
| 125 | *(vu_long *) MPC5XXX_SDRAM_CS0CFG = |
| 126 | 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
| 127 | /* let SDRAM CS1 start right after CS0 */ |
| 128 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ |
| 129 | } else { |
| 130 | #if 0 |
| 131 | *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
| 132 | /* let SDRAM CS1 start right after CS0 */ |
| 133 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ |
| 134 | #else |
| 135 | *(vu_long *) MPC5XXX_SDRAM_CS0CFG = |
| 136 | 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; |
| 137 | /* let SDRAM CS1 start right after CS0 */ |
| 138 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ |
| 139 | #endif |
| 140 | } |
| 141 | |
| 142 | #if 0 |
| 143 | /* find RAM size using SDRAM CS1 only */ |
| 144 | sdram_start(0); |
| 145 | get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); |
| 146 | sdram_start(1); |
| 147 | get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); |
| 148 | sdram_start(0); |
| 149 | #endif |
| 150 | /* set SDRAM CS1 size according to the amount of RAM found */ |
| 151 | |
| 152 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
| 153 | |
| 154 | init_power_switch(); |
| 155 | return (dramsize); |
| 156 | } |
| 157 | |
| 158 | int checkboard(void) |
| 159 | { |
| 160 | puts("Board: esd CPX CPU5200 (mecp5200)\n"); |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | void flash_preinit(void) |
| 165 | { |
| 166 | /* |
| 167 | * Now, when we are in RAM, enable flash write |
| 168 | * access for detection process. |
| 169 | * Note that CS_BOOT cannot be cleared when |
| 170 | * executing in flash. |
| 171 | */ |
| 172 | *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
| 173 | } |
| 174 | |
| 175 | void flash_afterinit(ulong size) |
| 176 | { |
| 177 | if (size == CFG_FLASH_SIZE) { |
| 178 | /* adjust mapping */ |
| 179 | *(vu_long *) MPC5XXX_BOOTCS_START = |
| 180 | *(vu_long *) MPC5XXX_CS0_START = |
| 181 | START_REG(CFG_BOOTCS_START | size); |
| 182 | *(vu_long *) MPC5XXX_BOOTCS_STOP = |
| 183 | *(vu_long *) MPC5XXX_CS0_STOP = |
| 184 | STOP_REG(CFG_BOOTCS_START | size, size); |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | #ifdef CONFIG_PCI |
| 189 | static struct pci_controller hose; |
| 190 | |
| 191 | extern void pci_mpc5xxx_init(struct pci_controller *); |
| 192 | |
| 193 | void pci_init_board(void) |
| 194 | { |
| 195 | pci_mpc5xxx_init(&hose); |
| 196 | } |
| 197 | #endif |
| 198 | |
Jon Loeliger | 77a3185 | 2007-07-10 10:39:10 -0500 | [diff] [blame] | 199 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
Stefan Roese | 8b7d1f0 | 2007-01-31 16:37:34 +0100 | [diff] [blame] | 200 | |
| 201 | #define GPIO_PSC1_4 0x01000000UL |
| 202 | |
| 203 | void init_ide_reset(void) |
| 204 | { |
| 205 | debug("init_ide_reset\n"); |
| 206 | |
| 207 | /* Configure PSC1_4 as GPIO output for ATA reset */ |
| 208 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
| 209 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
| 210 | } |
| 211 | |
| 212 | void ide_set_reset(int idereset) |
| 213 | { |
| 214 | debug("ide_reset(%d)\n", idereset); |
| 215 | |
| 216 | if (idereset) |
| 217 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
| 218 | else |
| 219 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
| 220 | } |
Jon Loeliger | 77a3185 | 2007-07-10 10:39:10 -0500 | [diff] [blame] | 221 | #endif |
Stefan Roese | 8b7d1f0 | 2007-01-31 16:37:34 +0100 | [diff] [blame] | 222 | |
| 223 | #define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) |
| 224 | #define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) |
| 225 | #define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) |
| 226 | #define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) |
| 227 | |
| 228 | #define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) |
| 229 | #define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) |
| 230 | #define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) |
| 231 | #define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) |
| 232 | |
| 233 | #define GPIO_WU6 0x40000000UL |
| 234 | #define GPIO_USB0 0x00010000UL |
| 235 | #define GPIO_USB9 0x08000000UL |
| 236 | #define GPIO_USB9S 0x00080000UL |
| 237 | |
| 238 | void init_power_switch(void) |
| 239 | { |
| 240 | debug("init_power_switch\n"); |
| 241 | |
| 242 | /* Configure GPIO_WU6 as GPIO output for ATA reset */ |
| 243 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; |
| 244 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; |
| 245 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; |
| 246 | __asm__ volatile ("sync"); |
| 247 | |
| 248 | *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; |
| 249 | *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; |
| 250 | *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; |
| 251 | __asm__ volatile ("sync"); |
| 252 | |
| 253 | *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; |
| 254 | *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; |
| 255 | __asm__ volatile ("sync"); |
| 256 | |
| 257 | if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { |
| 258 | *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; |
| 259 | __asm__ volatile ("sync"); |
| 260 | } |
| 261 | } |