blob: b99f383ec1e58681986b6a9cc9171ded16281f9f [file] [log] [blame]
Poonam Aggrwal728ece32009-08-05 13:29:24 +05301/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020033#ifdef CONFIG_P1011RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050034#define CONFIG_P1011
35#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020036#ifdef CONFIG_P1020RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050037#define CONFIG_P1020
38#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020039#ifdef CONFIG_P2010RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050040#define CONFIG_P2010
41#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020042#ifdef CONFIG_P2020RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050043#define CONFIG_P2020
44#endif
45
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020046#ifdef CONFIG_NAND
Dipen Dudhatf7780ec2009-10-08 13:33:18 +053047#define CONFIG_NAND_U_BOOT 1
48#define CONFIG_RAMBOOT_NAND 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020049#define CONFIG_SYS_TEXT_BASE 0xf8f82000
Dipen Dudhatf7780ec2009-10-08 13:33:18 +053050#endif
51
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020052#ifdef CONFIG_SDCARD
Dipen Dudhatfad15092009-10-08 13:33:29 +053053#define CONFIG_RAMBOOT_SDCARD 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Dipen Dudhatfad15092009-10-08 13:33:29 +053055#endif
56
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020057#ifdef CONFIG_SPIFLASH
Dipen Dudhatfad15092009-10-08 13:33:29 +053058#define CONFIG_RAMBOOT_SPIFLASH 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020059#define CONFIG_SYS_TEXT_BASE 0xf8f80000
60#endif
61
62#ifndef CONFIG_SYS_TEXT_BASE
63#define CONFIG_SYS_TEXT_BASE 0xeff80000
Dipen Dudhatfad15092009-10-08 13:33:29 +053064#endif
65
Poonam Aggrwal728ece32009-08-05 13:29:24 +053066/* High Level Configuration Options */
67#define CONFIG_BOOKE 1 /* BOOKE */
68#define CONFIG_E500 1 /* BOOKE e500 family */
69#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
70#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
Poonam Aggrwal33f3f342009-08-21 07:29:58 +053071#define CONFIG_PCI 1 /* Enable PCI/PCIE */
72#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
73#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
74#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
75#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
76#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Poonam Aggrwal728ece32009-08-05 13:29:24 +053077#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
78#define CONFIG_TSEC_ENET /* tsec ethernet support */
79#define CONFIG_ENV_OVERWRITE
80
Poonam Aggrwalddac6f02010-07-01 14:24:36 +053081#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
Poonam Aggrwal728ece32009-08-05 13:29:24 +053082#ifndef __ASSEMBLY__
83extern unsigned long get_board_sys_clk(unsigned long dummy);
84#endif
85#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
86#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
87
88#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
89#define CONFIG_MP
90#endif
91
Poonam Aggrwal525f6c32010-06-23 19:38:06 +053092#define CONFIG_HWCONFIG
93
Poonam Aggrwal728ece32009-08-05 13:29:24 +053094/*
95 * These can be toggled for performance analysis, otherwise use default.
96 */
97#define CONFIG_L2_CACHE /* toggle L2 cache */
98#define CONFIG_BTB /* toggle branch predition */
99
100#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
101
102#define CONFIG_ENABLE_36BIT_PHYS 1
103
104#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
105#define CONFIG_SYS_MEMTEST_END 0x1fffffff
106#define CONFIG_PANIC_HANG /* do not reset board on panic */
107
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530108 /*
109 * Config the L2 Cache as L2 SRAM
110 */
111#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
112#ifdef CONFIG_PHYS_64BIT
113#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
114#else
115#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
116#endif
117#define CONFIG_SYS_L2_SIZE (512 << 10)
118#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
119
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530120/*
121 * Base addresses -- Note these are effective addresses where the
122 * actual resources get mapped (not physical addresses)
123 */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530124#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
125#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
126 /* CCSRBAR */
127#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
128 /* CONFIG_SYS_IMMR */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530129
130#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
131#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
132#else
133#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
134#endif
135
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530136/* DDR Setup */
137#define CONFIG_FSL_DDR2
138#undef CONFIG_FSL_DDR_INTERACTIVE
139#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
140#undef CONFIG_DDR_DLL
141
142#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
143
144#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
145#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
147
148#define CONFIG_NUM_DDR_CONTROLLERS 1
149#define CONFIG_DIMM_SLOTS_PER_CTLR 1
150#define CONFIG_CHIP_SELECTS_PER_CTRL 1
151
152#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
153#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
154#define CONFIG_SYS_DDR_SBE 0x00FF0000
155
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530156/*
157 * Memory map
158 *
159 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
160 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
161 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
162 *
163 * Localbus cacheable (TBD)
164 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
165 *
166 * Localbus non-cacheable
167 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
168 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
169 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
170 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
171 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
172 */
173
174/*
175 * Local Bus Definitions
176 */
177#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
178
179#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
180
181#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
182 BR_PS_16 | BR_V)
183#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
184
185#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
186#define CONFIG_SYS_FLASH_QUIET_TEST
187#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
188
189#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
190#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
191#undef CONFIG_SYS_FLASH_CHECKSUM
192#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
194
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530196
Dipen Dudhatfad15092009-10-08 13:33:29 +0530197#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
198 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530199#define CONFIG_SYS_RAMBOOT
200#else
201#undef CONFIG_SYS_RAMBOOT
202#endif
203
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530204#define CONFIG_FLASH_CFI_DRIVER
205#define CONFIG_SYS_FLASH_CFI
206#define CONFIG_SYS_FLASH_EMPTY_INFO
207#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
208
209#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
Vivek Mahajan66e821e2010-01-07 14:27:14 +0530210#define CONFIG_HWCONFIG
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530211
212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200214#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530215
Wolfgang Denk553f0982010-10-26 13:32:32 +0200216#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200217 - GENERATED_GBL_DATA_SIZE)
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
219
220#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
221#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
222
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530223#ifndef CONFIG_NAND_SPL
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530224#define CONFIG_SYS_NAND_BASE 0xffa00000
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530225#else
226#define CONFIG_SYS_NAND_BASE 0xfff00000
227#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530228#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
229#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
230#define CONFIG_SYS_MAX_NAND_DEVICE 1
231#define NAND_MAX_CHIPS 1
232#define CONFIG_MTD_NAND_VERIFY_WRITE
233#define CONFIG_CMD_NAND 1
234#define CONFIG_NAND_FSL_ELBC 1
235#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
236
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530237/* NAND boot: 4K NAND loader config */
238#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
239#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
240#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
241#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
242#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
243#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
244#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
245
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530246/* NAND flash config */
247#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
248 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
249 | BR_PS_8 /* Port Size = 8 bit */ \
250 | BR_MS_FCM /* MSEL = FCM */ \
251 | BR_V) /* valid */
252
253#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
254 | OR_FCM_CSCT \
255 | OR_FCM_CST \
256 | OR_FCM_CHT \
257 | OR_FCM_SCY_1 \
258 | OR_FCM_TRLX \
259 | OR_FCM_EHTR)
260
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530261#ifdef CONFIG_RAMBOOT_NAND
262#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
263#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
264#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
265#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
266#else
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530267#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
268#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
269#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
270#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530271#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530272
273#define CONFIG_SYS_VSC7385_BASE 0xffb00000
274
275#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
276
277#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
278#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
279 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
280 OR_GPCM_EHTR | OR_GPCM_EAD)
281
282/* Serial Port - controlled on board with jumper J8
283 * open - index 2
284 * shorted - index 1
285 */
286#define CONFIG_CONS_INDEX 1
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530287#define CONFIG_SYS_NS16550
288#define CONFIG_SYS_NS16550_SERIAL
289#define CONFIG_SYS_NS16550_REG_SIZE 1
290#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500291#ifdef CONFIG_NAND_SPL
292#define CONFIG_NS16550_MIN_FUNCTIONS
293#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530294
295#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
296#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
297
298#define CONFIG_SYS_BAUDRATE_TABLE \
299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
300
301#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
302#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
303
304/* Use the HUSH parser */
305#define CONFIG_SYS_HUSH_PARSER
306#ifdef CONFIG_SYS_HUSH_PARSER
307#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
308#endif
309
310/*
311 * Pass open firmware flat tree
312 */
313#define CONFIG_OF_LIBFDT 1
314#define CONFIG_OF_BOARD_SETUP 1
315#define CONFIG_OF_STDOUT_VIA_ALIAS 1
316
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530317/* new uImage format support */
318#define CONFIG_FIT 1
319#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
320
321/* I2C */
322#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
323#define CONFIG_HARD_I2C /* I2C with hardware support */
324#undef CONFIG_SOFT_I2C /* I2C bit-banged */
325#define CONFIG_I2C_MULTI_BUS
326#define CONFIG_I2C_CMD_TREE
327#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
328#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
329#define CONFIG_SYS_I2C_SLAVE 0x7F
330#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
331#define CONFIG_SYS_I2C_OFFSET 0x3000
332#define CONFIG_SYS_I2C2_OFFSET 0x3100
333
334/*
335 * I2C2 EEPROM
336 */
337#define CONFIG_ID_EEPROM
338#ifdef CONFIG_ID_EEPROM
339#define CONFIG_SYS_I2C_EEPROM_NXID
340#endif
341#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
342#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
343#define CONFIG_SYS_EEPROM_BUS_NUM 1
344
345#define CONFIG_RTC_DS1337
346#define CONFIG_SYS_I2C_RTC_ADDR 0x68
347/*
348 * General PCI
349 * Memory space is mapped 1-1, but I/O space must start from 0.
350 */
351
352/* controller 2, Slot 2, tgtid 2, Base address 9000 */
353#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
354#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
355#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
356#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
357#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
358#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
359#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
360#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
361
362/* controller 1, Slot 1, tgtid 1, Base address a000 */
363#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
364#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
365#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
366#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
367#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
368#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
369#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
370#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
371
372#if defined(CONFIG_PCI)
373#define CONFIG_NET_MULTI
374#define CONFIG_PCI_PNP /* do pci plug-and-play */
375
376#undef CONFIG_EEPRO100
377#undef CONFIG_TULIP
378#undef CONFIG_RTL8139
379
380#ifdef CONFIG_RTL8139
381/* This macro is used by RTL8139 but not defined in PPC architecture */
382#define KSEG1ADDR(x) (x)
383#define _IO_BASE 0x00000000
384#endif
385
386
387#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
388#define CONFIG_DOS_PARTITION
389
390#endif /* CONFIG_PCI */
391
392#if defined(CONFIG_TSEC_ENET)
393#ifndef CONFIG_NET_MULTI
394#define CONFIG_NET_MULTI 1
395#endif
396
397#define CONFIG_MII 1 /* MII PHY management */
398#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
399#define CONFIG_TSEC1 1
400#define CONFIG_TSEC1_NAME "eTSEC1"
401#define CONFIG_TSEC2 1
402#define CONFIG_TSEC2_NAME "eTSEC2"
403#define CONFIG_TSEC3 1
404#define CONFIG_TSEC3_NAME "eTSEC3"
405
406#define TSEC1_PHY_ADDR 2
407#define TSEC2_PHY_ADDR 0
408#define TSEC3_PHY_ADDR 1
409
410#define CONFIG_VSC7385_ENET
411
412#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
414#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
415
416#define TSEC1_PHYIDX 0
417#define TSEC2_PHYIDX 0
418#define TSEC3_PHYIDX 0
419
420/* Vitesse 7385 */
421
422#ifdef CONFIG_VSC7385_ENET
423/* The size of the VSC7385 firmware image */
424#define CONFIG_VSC7385_IMAGE_SIZE 8192
425#endif
426
427#define CONFIG_ETHPRIME "eTSEC1"
428
429#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Felix Radensky90b5bf22010-06-28 01:57:39 +0300430
431/* TBI PHY configuration for SGMII mode */
432#define CONFIG_TSEC_TBICR_SETTINGS ( \
433 TBICR_PHY_RESET \
434 | TBICR_ANEG_ENABLE \
435 | TBICR_FULL_DUPLEX \
436 | TBICR_SPEED1_SET \
437 )
438
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530439#endif /* CONFIG_TSEC_ENET */
440
441/*
442 * Environment
443 */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530444#if defined(CONFIG_SYS_RAMBOOT)
445#if defined(CONFIG_RAMBOOT_NAND)
446 #define CONFIG_ENV_IS_IN_NAND 1
447 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
448 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Dipen Dudhatfad15092009-10-08 13:33:29 +0530449#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
450 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
452 #define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530453#endif
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530454#else
455 #define CONFIG_ENV_IS_IN_FLASH 1
456 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
457 #define CONFIG_ENV_ADDR 0xfff80000
458 #else
459 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
460 #endif
461 #define CONFIG_ENV_SIZE 0x2000
462 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
463#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530464
465#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
466#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
467
468/*
469 * Command line configuration.
470 */
471#include <config_cmd_default.h>
472
473#define CONFIG_CMD_DATE
474#define CONFIG_CMD_ELF
475#define CONFIG_CMD_I2C
476#define CONFIG_CMD_IRQ
477#define CONFIG_CMD_MII
478#define CONFIG_CMD_PING
479#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500480#define CONFIG_CMD_REGINFO
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530481
482#if defined(CONFIG_PCI)
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530483#define CONFIG_CMD_NET
484#define CONFIG_CMD_PCI
485#endif
486
487#undef CONFIG_WATCHDOG /* watchdog disabled */
488
489#define CONFIG_MMC 1
490
491#ifdef CONFIG_MMC
492#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
493#define CONFIG_CMD_MMC
494#define CONFIG_DOS_PARTITION
495#define CONFIG_FSL_ESDHC
496#define CONFIG_GENERIC_MMC
497#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
498#ifdef CONFIG_P2020
499#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
500#endif
501#endif
502
503#define CONFIG_USB_EHCI
504
505#ifdef CONFIG_USB_EHCI
506#define CONFIG_CMD_USB
507#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
508#define CONFIG_USB_EHCI_FSL
509#define CONFIG_USB_STORAGE
510#endif
511
512#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
513#define CONFIG_CMD_EXT2
514#define CONFIG_CMD_FAT
515#define CONFIG_DOS_PARTITION
516#endif
517
518/*
519 * Miscellaneous configurable options
520 */
521#define CONFIG_SYS_LONGHELP /* undef to save memory */
522#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500523#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530524#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
525#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
526#if defined(CONFIG_CMD_KGDB)
527#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
528#else
529#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
530#endif
531#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
532 /* Print Buffer Size */
533#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
534#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
535#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
536
537/*
538 * For booting Linux, the board info and command line data
539 * have to be in the first 16 MB of memory, since this is
540 * the maximum mapped by the Linux kernel during initialization.
541 */
542#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
543
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530544#if defined(CONFIG_CMD_KGDB)
545#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
546#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
547#endif
548
549/*
550 * Environment Configuration
551 */
552
553#if defined(CONFIG_TSEC_ENET)
554#define CONFIG_HAS_ETH0
555#define CONFIG_HAS_ETH1
556#define CONFIG_HAS_ETH2
557#endif
558
559#define CONFIG_HOSTNAME P2020RDB
560#define CONFIG_ROOTPATH /opt/nfsroot
561#define CONFIG_BOOTFILE uImage
562#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
563
564/* default location for tftp and bootm */
565#define CONFIG_LOADADDR 1000000
566
567#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
568#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
569
570#define CONFIG_BAUDRATE 115200
571
572#define CONFIG_EXTRA_ENV_SETTINGS \
573 "netdev=eth0\0" \
574 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
575 "loadaddr=1000000\0" \
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530576 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200577 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
578 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
579 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
580 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
581 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530582 "consoledev=ttyS0\0" \
583 "ramdiskaddr=2000000\0" \
584 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
585 "fdtaddr=c00000\0" \
586 "fdtfile=p2020rdb.dtb\0" \
587 "bdev=sda1\0" \
588 "jffs2nor=mtdblock3\0" \
589 "norbootaddr=ef080000\0" \
590 "norfdtaddr=ef040000\0" \
591 "jffs2nand=mtdblock9\0" \
592 "nandbootaddr=100000\0" \
593 "nandfdtaddr=80000\0" \
594 "nandimgsize=400000\0" \
595 "nandfdtsize=80000\0" \
596 "usb_phy_type=ulpi\0" \
597 "vscfw_addr=ef000000\0" \
598 "othbootargs=ramdisk_size=600000\0" \
599 "usbfatboot=setenv bootargs root=/dev/ram rw " \
600 "console=$consoledev,$baudrate $othbootargs; " \
601 "usb start;" \
602 "fatload usb 0:2 $loadaddr $bootfile;" \
603 "fatload usb 0:2 $fdtaddr $fdtfile;" \
604 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
606 "usbext2boot=setenv bootargs root=/dev/ram rw " \
607 "console=$consoledev,$baudrate $othbootargs; " \
608 "usb start;" \
609 "ext2load usb 0:4 $loadaddr $bootfile;" \
610 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
611 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
612 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
613 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
614 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
615 "bootm $norbootaddr - $norfdtaddr\0" \
616 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
617 "console=$consoledev,$baudrate $othbootargs;" \
618 "nand read 2000000 $nandbootaddr $nandimgsize;" \
619 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
620 "bootm 2000000 - 3000000;\0"
621
622#define CONFIG_NFSBOOTCOMMAND \
623 "setenv bootargs root=/dev/nfs rw " \
624 "nfsroot=$serverip:$rootpath " \
625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $loadaddr $bootfile;" \
628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr - $fdtaddr"
630
631#define CONFIG_HDBOOT \
632 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "usb start;" \
635 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
636 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
637 "bootm $loadaddr - $fdtaddr"
638
639#define CONFIG_RAMBOOTCOMMAND \
640 "setenv bootargs root=/dev/ram rw " \
641 "console=$consoledev,$baudrate $othbootargs; " \
642 "tftp $ramdiskaddr $ramdiskfile;" \
643 "tftp $loadaddr $bootfile;" \
644 "tftp $fdtaddr $fdtfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr"
646
647#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
648
649#endif /* __CONFIG_H */