Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 1 | /* |
Enric Balletbò i Serra | dc7a9e6 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 2 | * Common configuration settings for IGEP technology based boards |
| 3 | * |
| 4 | * (C) Copyright 2012 |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 5 | * ISEE 2007 SL, <www.iseebcn.com> |
| 6 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 8 | */ |
| 9 | |
Enric Balletbò i Serra | dc7a9e6 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 10 | #ifndef __IGEP00X0_H |
| 11 | #define __IGEP00X0_H |
| 12 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 13 | #ifdef CONFIG_BOOT_NAND |
| 14 | #define CONFIG_NAND |
| 15 | #endif |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 16 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 17 | #define CONFIG_NR_DRAM_BANKS 2 |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 18 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 19 | #include <configs/ti_omap3_common.h> |
Enric Balletbo i Serra | aa127df | 2013-02-07 00:40:05 +0000 | [diff] [blame] | 20 | #include <asm/mach-types.h> |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * Display CPU and Board information |
| 24 | */ |
| 25 | #define CONFIG_DISPLAY_CPUINFO 1 |
| 26 | #define CONFIG_DISPLAY_BOARDINFO 1 |
| 27 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 28 | #define CONFIG_MISC_INIT_R |
| 29 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 30 | #define CONFIG_REVISION_TAG 1 |
| 31 | |
Enric Balletbo i Serra | 50bb94c | 2015-02-24 19:27:15 +0100 | [diff] [blame] | 32 | /* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */ |
| 33 | #if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032) |
Enric Balletbo i Serra | f3b4bc4 | 2015-01-28 15:01:32 +0100 | [diff] [blame] | 34 | #define CONFIG_STATUS_LED |
| 35 | #define CONFIG_BOARD_SPECIFIC_LED |
| 36 | #define CONFIG_GPIO_LED |
| 37 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) |
| 38 | #define RED_LED_GPIO 27 |
Enric Balletbo i Serra | 50bb94c | 2015-02-24 19:27:15 +0100 | [diff] [blame] | 39 | #elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) |
Enric Balletbo i Serra | f3b4bc4 | 2015-01-28 15:01:32 +0100 | [diff] [blame] | 40 | #define RED_LED_GPIO 16 |
Enric Balletbo i Serra | 50bb94c | 2015-02-24 19:27:15 +0100 | [diff] [blame] | 41 | #else |
| 42 | #error "status LED not defined for this machine." |
Enric Balletbo i Serra | f3b4bc4 | 2015-01-28 15:01:32 +0100 | [diff] [blame] | 43 | #endif |
| 44 | #define RED_LED_DEV 0 |
| 45 | #define STATUS_LED_BIT RED_LED_GPIO |
| 46 | #define STATUS_LED_STATE STATUS_LED_ON |
| 47 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
| 48 | #define STATUS_LED_BOOT RED_LED_DEV |
Enric Balletbo i Serra | 50bb94c | 2015-02-24 19:27:15 +0100 | [diff] [blame] | 49 | #endif |
Javier Martinez Canillas | 9d4f542 | 2012-12-27 03:36:01 +0000 | [diff] [blame] | 50 | |
Enric Balletbo i Serra | dd1e858 | 2014-01-25 22:52:22 +0100 | [diff] [blame] | 51 | /* GPIO banks */ |
| 52 | #define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ |
| 53 | #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ |
| 54 | #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ |
| 55 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 56 | /* USB */ |
| 57 | #define CONFIG_MUSB_UDC 1 |
| 58 | #define CONFIG_USB_OMAP3 1 |
| 59 | #define CONFIG_TWL4030_USB 1 |
| 60 | |
| 61 | /* USB device configuration */ |
| 62 | #define CONFIG_USB_DEVICE 1 |
| 63 | #define CONFIG_USB_TTY 1 |
| 64 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
| 65 | |
| 66 | /* Change these to suit your needs */ |
| 67 | #define CONFIG_USBD_VENDORID 0x0451 |
| 68 | #define CONFIG_USBD_PRODUCTID 0x5678 |
| 69 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
| 70 | #define CONFIG_USBD_PRODUCT_NAME "IGEP" |
| 71 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 72 | #define CONFIG_CMD_CACHE |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 73 | #ifdef CONFIG_BOOT_ONENAND |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 74 | #define CONFIG_CMD_ONENAND /* ONENAND support */ |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 75 | #endif |
Enric Balletbo i Serra | d9aacf4 | 2013-02-07 00:40:06 +0000 | [diff] [blame] | 76 | #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ |
| 77 | (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) |
Javier Martinez Canillas | 77eea28 | 2012-12-27 01:35:56 +0000 | [diff] [blame] | 78 | #endif |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 79 | #define CONFIG_CMD_DHCP |
| 80 | #define CONFIG_CMD_PING |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 81 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 82 | /*#undef CONFIG_ENV_IS_NOWHERE*/ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 83 | |
| 84 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 85 | "usbtty=cdc_acm\0" \ |
| 86 | "loadaddr=0x82000000\0" \ |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 87 | "dtbaddr=0x81600000\0" \ |
| 88 | "bootdir=/boot\0" \ |
| 89 | "bootfile=zImage\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 90 | "usbtty=cdc_acm\0" \ |
Javier Martinez Canillas | e5e73c1 | 2012-06-29 02:45:40 +0000 | [diff] [blame] | 91 | "console=ttyO2,115200n8\0" \ |
Enric Balletbo i Serra | f1e445c | 2012-04-25 02:34:31 +0000 | [diff] [blame] | 92 | "mpurate=auto\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 93 | "vram=12M\0" \ |
| 94 | "dvimode=1024x768MR-16@60\0" \ |
| 95 | "defaultdisplay=dvi\0" \ |
| 96 | "mmcdev=0\0" \ |
| 97 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
Javier Martinez Canillas | b4ebeb8 | 2012-06-29 02:45:41 +0000 | [diff] [blame] | 98 | "mmcrootfstype=ext4 rootwait\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 99 | "nandroot=/dev/mtdblock4 rw\0" \ |
| 100 | "nandrootfstype=jffs2\0" \ |
| 101 | "mmcargs=setenv bootargs console=${console} " \ |
| 102 | "mpurate=${mpurate} " \ |
| 103 | "vram=${vram} " \ |
| 104 | "omapfb.mode=dvi:${dvimode} " \ |
| 105 | "omapfb.debug=y " \ |
| 106 | "omapdss.def_disp=${defaultdisplay} " \ |
| 107 | "root=${mmcroot} " \ |
| 108 | "rootfstype=${mmcrootfstype}\0" \ |
| 109 | "nandargs=setenv bootargs console=${console} " \ |
| 110 | "mpurate=${mpurate} " \ |
| 111 | "vram=${vram} " \ |
| 112 | "omapfb.mode=dvi:${dvimode} " \ |
| 113 | "omapfb.debug=y " \ |
| 114 | "omapdss.def_disp=${defaultdisplay} " \ |
| 115 | "root=${nandroot} " \ |
| 116 | "rootfstype=${nandrootfstype}\0" \ |
Enric Balletbo i Serra | 2be6bed | 2013-08-07 17:53:18 +0200 | [diff] [blame] | 117 | "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ |
Enric Balletbo i Serra | 1b8ec01 | 2012-04-25 02:33:50 +0000 | [diff] [blame] | 118 | "importbootenv=echo Importing environment from mmc ...; " \ |
| 119 | "env import -t $loadaddr $filesize\0" \ |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 120 | "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ |
| 121 | "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 122 | "mmcboot=echo Booting from mmc ...; " \ |
| 123 | "run mmcargs; " \ |
Enric Balletbo i Serra | 2be6bed | 2013-08-07 17:53:18 +0200 | [diff] [blame] | 124 | "bootz ${loadaddr}\0" \ |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 125 | "mmcbootfdt=echo Booting with DT from mmc ...; " \ |
| 126 | "bootz ${loadaddr} - ${dtbaddr}\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 127 | "nandboot=echo Booting from onenand ...; " \ |
| 128 | "run nandargs; " \ |
| 129 | "onenand read ${loadaddr} 280000 400000; " \ |
Enric Balletbo i Serra | 2be6bed | 2013-08-07 17:53:18 +0200 | [diff] [blame] | 130 | "bootz ${loadaddr}\0" \ |
Enric Balletbo i Serra | 304a46c | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 131 | |
| 132 | #define CONFIG_BOOTCOMMAND \ |
Andrew Bradford | 6696811 | 2012-10-01 05:06:52 +0000 | [diff] [blame] | 133 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
Enric Balletbo i Serra | 1b8ec01 | 2012-04-25 02:33:50 +0000 | [diff] [blame] | 134 | "echo SD/MMC found on device ${mmcdev};" \ |
| 135 | "if run loadbootenv; then " \ |
| 136 | "run importbootenv;" \ |
| 137 | "fi;" \ |
| 138 | "if test -n $uenvcmd; then " \ |
| 139 | "echo Running uenvcmd ...;" \ |
| 140 | "run uenvcmd;" \ |
| 141 | "fi;" \ |
Enric Balletbo i Serra | 2be6bed | 2013-08-07 17:53:18 +0200 | [diff] [blame] | 142 | "if run loadzimage; then " \ |
Javier Martinez Canillas | a2fa28b | 2013-08-07 17:53:19 +0200 | [diff] [blame] | 143 | "if test -n $dtbfile; then " \ |
| 144 | "if run loadfdt; then " \ |
| 145 | "run mmcbootfdt;" \ |
| 146 | "fi;" \ |
| 147 | "fi;" \ |
Enric Balletbo i Serra | 1b8ec01 | 2012-04-25 02:33:50 +0000 | [diff] [blame] | 148 | "run mmcboot;" \ |
| 149 | "fi;" \ |
| 150 | "fi;" \ |
| 151 | "run nandboot;" \ |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 152 | |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 153 | /* |
| 154 | * FLASH and environment organization |
| 155 | */ |
| 156 | |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 157 | #ifdef CONFIG_BOOT_ONENAND |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 158 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
| 159 | |
| 160 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
| 161 | |
| 162 | #define CONFIG_ENV_IS_IN_ONENAND 1 |
| 163 | #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ |
| 164 | #define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 165 | #endif |
| 166 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 167 | #ifdef CONFIG_NAND |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 168 | #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ |
| 169 | #define CONFIG_ENV_IS_IN_NAND 1 |
| 170 | #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ |
| 171 | #define CONFIG_ENV_ADDR NAND_ENV_OFFSET |
Javier Martinez Canillas | ca511cf | 2012-07-28 01:19:32 +0000 | [diff] [blame] | 172 | #endif |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 173 | |
| 174 | /* |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 175 | * SMSC911x Ethernet |
| 176 | */ |
| 177 | #if defined(CONFIG_CMD_NET) |
Enric Balletbo i Serra | 8a3f6bb | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 178 | #define CONFIG_SMC911X |
| 179 | #define CONFIG_SMC911X_32_BIT |
| 180 | #define CONFIG_SMC911X_BASE 0x2C000000 |
| 181 | #endif /* (CONFIG_CMD_NET) */ |
| 182 | |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 183 | /* OneNAND boot config */ |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 184 | #ifdef CONFIG_BOOT_ONENAND |
| 185 | #define CONFIG_SPL_ONENAND_SUPPORT |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 186 | #define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 |
| 187 | #define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 |
| 188 | #define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 |
| 189 | #define CONFIG_SPL_ONENAND_LOAD_SIZE \ |
| 190 | (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) |
| 191 | |
| 192 | #endif |
| 193 | |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 194 | /* NAND boot config */ |
Enric Balletbò i Serra | e37e954 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 195 | #ifdef CONFIG_NAND |
pekon gupta | b80a660 | 2014-05-06 00:46:19 +0530 | [diff] [blame] | 196 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 197 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 198 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 199 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 200 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 201 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) |
| 202 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
| 203 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ |
| 204 | 10, 11, 12, 13} |
| 205 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
| 206 | #define CONFIG_SYS_NAND_ECCBYTES 3 |
pekon gupta | 3f71906 | 2013-11-18 19:03:01 +0530 | [diff] [blame] | 207 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
pekon gupta | 434f2cf | 2014-07-18 17:59:42 +0530 | [diff] [blame] | 208 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
| 209 | /* NAND: SPL falcon mode configs */ |
| 210 | #ifdef CONFIG_SPL_OS_BOOT |
| 211 | #define CONFIG_CMD_SPL_NAND_OFS 0x240000 |
| 212 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 |
| 213 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 |
| 214 | #endif |
Javier Martinez Canillas | d271a61 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 215 | #endif |
| 216 | |
Enric Balletbò i Serra | dc7a9e6 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 217 | #endif /* __IGEP00X0_H */ |