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Matthias Fuchs15a08bc2008-01-17 10:52:30 +01001/*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <asm/processor.h>
23#include <asm/io.h>
24#include <asm/bitops.h>
25#include <command.h>
26#include <i2c.h>
27#include <ppc440.h>
28#include "du440.h"
29
30DECLARE_GLOBAL_DATA_PTR;
31
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010033extern ulong flash_get_size (ulong base, int banknum);
34
35int usbhub_init(void);
36int dvi_init(void);
37int eeprom_write_enable (unsigned dev_addr, int state);
38int board_revision(void);
39
40static int du440_post_errors;
41
42int board_early_init_f(void)
43{
44 u32 sdr0_cust0;
45 u32 sdr0_pfc1, sdr0_pfc2;
46 u32 reg;
47
Stefan Roesed1c3b272009-09-09 16:25:29 +020048 mtdcr(EBC0_CFGADDR, EBC0_CFG);
49 mtdcr(EBC0_CFGDATA, 0xb8400000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010050
51 /*
52 * Setup the GPIO pins
53 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
55 out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010056 out_be32((void*)GPIO0_OSRL, 0x50055400);
Matthias Fuchs6a133d62008-10-07 13:13:08 +020057 out_be32((void*)GPIO0_OSRH, 0x55005000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010058 out_be32((void*)GPIO0_TSRL, 0x50055400);
59 out_be32((void*)GPIO0_TSRH, 0x55005000);
60 out_be32((void*)GPIO0_ISR1L, 0x50000000);
61 out_be32((void*)GPIO0_ISR1H, 0x00000000);
62 out_be32((void*)GPIO0_ISR2L, 0x00000000);
Matthias Fuchs6a133d62008-10-07 13:13:08 +020063 out_be32((void*)GPIO0_ISR2H, 0x00000000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010064 out_be32((void*)GPIO0_ISR3L, 0x00000000);
65 out_be32((void*)GPIO0_ISR3H, 0x00000000);
66
67 out_be32((void*)GPIO1_OR, 0x00000000);
68 out_be32((void*)GPIO1_TCR, 0xc2000000 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 CONFIG_SYS_GPIO1_IORSTN |
70 CONFIG_SYS_GPIO1_IORST2N |
71 CONFIG_SYS_GPIO1_LEDUSR1 |
72 CONFIG_SYS_GPIO1_LEDUSR2 |
73 CONFIG_SYS_GPIO1_LEDPOST |
74 CONFIG_SYS_GPIO1_LEDDU);
75 out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
Matthias Fuchs6a133d62008-10-07 13:13:08 +020076 out_be32((void*)GPIO1_OSRL, 0x0c280000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010077 out_be32((void*)GPIO1_OSRH, 0x00000000);
Matthias Fuchs6a133d62008-10-07 13:13:08 +020078 out_be32((void*)GPIO1_TSRL, 0xcc000000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +010079 out_be32((void*)GPIO1_TSRH, 0x00000000);
80 out_be32((void*)GPIO1_ISR1L, 0x00005550);
81 out_be32((void*)GPIO1_ISR1H, 0x00000000);
82 out_be32((void*)GPIO1_ISR2L, 0x00050000);
83 out_be32((void*)GPIO1_ISR2H, 0x00000000);
84 out_be32((void*)GPIO1_ISR3L, 0x01400000);
85 out_be32((void*)GPIO1_ISR3H, 0x00000000);
86
87 /*
88 * Setup the interrupt controller polarities, triggers, etc.
89 */
90 mtdcr(uic0sr, 0xffffffff); /* clear all */
91 mtdcr(uic0er, 0x00000000); /* disable all */
92 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
93 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
94 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
95 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
96 mtdcr(uic0sr, 0xffffffff); /* clear all */
97
98 /*
99 * UIC1:
100 * bit30: ext. Irq 1: PLD : int 32+30
101 */
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xfffffffd);
106 mtdcr(uic1tr, 0x00000000);
107 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
109
110 /*
111 * UIC2
112 * bit3: ext. Irq 2: DCF77 : int 64+3
113 */
114 mtdcr(uic2sr, 0xffffffff); /* clear all */
115 mtdcr(uic2er, 0x00000000); /* disable all */
116 mtdcr(uic2cr, 0x00000000); /* all non-critical */
117 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
118 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
119 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
120 mtdcr(uic2sr, 0xffffffff); /* clear all */
121
122 /* select Ethernet pins */
123 mfsdr(SDR0_PFC1, sdr0_pfc1);
124 mfsdr(SDR0_PFC2, sdr0_pfc2);
125
126 /* setup EMAC bridge interface */
127 if (board_revision() == 0) {
128 /* 1 x MII */
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
130 SDR0_PFC1_SELECT_CONFIG_1_2;
131 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
132 SDR0_PFC2_SELECT_CONFIG_1_2;
133 } else {
134 /* 2 x SMII */
135 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
136 SDR0_PFC1_SELECT_CONFIG_6;
137 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
138 SDR0_PFC2_SELECT_CONFIG_6;
139 }
140
141 /* enable 2nd IIC */
142 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
143
144 mtsdr(SDR0_PFC2, sdr0_pfc2);
145 mtsdr(SDR0_PFC1, sdr0_pfc1);
146
147 /* PCI arbiter enabled */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200148 mfsdr(SDR0_PCI0, reg);
149 mtsdr(SDR0_PCI0, 0x80000000 | reg);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100150
151 /* setup NAND FLASH */
152 mfsdr(SDR0_CUST0, sdr0_cust0);
153 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
154 SDR0_CUST0_NDFC_ENABLE |
155 SDR0_CUST0_NDFC_BW_8_BIT |
156 SDR0_CUST0_NDFC_ARE_MASK |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
158 (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100159 mtsdr(SDR0_CUST0, sdr0_cust0);
160
161 return 0;
162}
163
164int misc_init_r(void)
165{
166 uint pbcr;
167 int size_val = 0;
168 u32 reg;
169 unsigned long usb2d0cr = 0;
170 unsigned long usb2phy0cr, usb2h0cr = 0;
171 unsigned long sdr0_pfc1;
Matthias Fuchs542b3852008-10-07 13:13:10 +0200172 unsigned long sdr0_srst0, sdr0_srst1;
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100173 int i, j;
174
175 /* adjust flash start and offset */
176 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
177 gd->bd->bi_flashoffset = 0;
178
Stefan Roesed1c3b272009-09-09 16:25:29 +0200179 mtdcr(EBC0_CFGADDR, PB0CR);
180 pbcr = mfdcr(EBC0_CFGDATA);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100181 size_val = ffs(gd->bd->bi_flashsize) - 21;
182 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200183 mtdcr(EBC0_CFGADDR, PB0CR);
184 mtdcr(EBC0_CFGDATA, pbcr);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100185
186 /*
187 * Re-check to get correct base address
188 */
189 flash_get_size(gd->bd->bi_flashstart, 0);
190
191 /*
192 * USB suff...
193 */
194 /* SDR Setting */
195 mfsdr(SDR0_PFC1, sdr0_pfc1);
196 mfsdr(SDR0_USB0, usb2d0cr);
197 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
198 mfsdr(SDR0_USB2H0CR, usb2h0cr);
199
200 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
201 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
202 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
203 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
204 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
205 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
210
211 /* An 8-bit/60MHz interface is the only possible alternative
212 when connecting the Device to the PHY */
213 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
214 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
215
216 /* To enable the USB 2.0 Device function through the UTMI interface */
217 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
218
219 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
220 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
221
222 mtsdr(SDR0_PFC1, sdr0_pfc1);
223 mtsdr(SDR0_USB0, usb2d0cr);
224 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
225 mtsdr(SDR0_USB2H0CR, usb2h0cr);
226
Matthias Fuchs542b3852008-10-07 13:13:10 +0200227 /*
228 * Take USB out of reset:
229 * -Initial status = all cores are in reset
230 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
231 * -wait 1 ms
232 * -deassert reset to PHY
233 * -wait 1 ms
234 * -deassert reset to HOST
235 * -wait 4 ms
236 * -deassert all other resets
237 */
238 mfsdr(SDR0_SRST1, sdr0_srst1);
239 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
240 SDR0_SRST1_P4OPB0 | \
241 SDR0_SRST1_OPBA2 | \
242 SDR0_SRST1_PLB42OPB1 | \
243 SDR0_SRST1_OPB2PLB40);
244 mtsdr(SDR0_SRST1, sdr0_srst1);
245 udelay(1000);
246
247 mfsdr(SDR0_SRST1, sdr0_srst1);
248 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
249 mtsdr(SDR0_SRST1, sdr0_srst1);
250 udelay(1000);
251
252 mfsdr(SDR0_SRST0, sdr0_srst0);
253 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
254 mtsdr(SDR0_SRST0, sdr0_srst0);
255 udelay(4000);
256
257 /* finally all the other resets */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100258 mtsdr(SDR0_SRST1, 0x00000000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100259 mtsdr(SDR0_SRST0, 0x00000000);
260
261 printf("USB: Host(int phy)\n");
262
263 /*
264 * Clear PLB4A0_ACR[WRP]
265 * This fix will make the MAL burst disabling patch for the Linux
266 * EMAC driver obsolete.
267 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200268 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
269 mtdcr(PLB4_ACR, reg);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100270
271 /*
272 * release IO-RST#
273 * We have to wait at least 560ms until we may call usbhub_init
274 */
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200275 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100277
278 /*
279 * flash USR1/2 LEDs (600ms)
280 * This results in the necessary delay from IORST# until
281 * calling usbhub_init will succeed
282 */
283 for (j = 0; j < 3; j++) {
284 out_be32((void*)GPIO1_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
286 CONFIG_SYS_GPIO1_LEDUSR1);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100287
288 for (i = 0; i < 100; i++)
289 udelay(1000);
290
291 out_be32((void*)GPIO1_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
293 CONFIG_SYS_GPIO1_LEDUSR2);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100294
295 for (i = 0; i < 100; i++)
296 udelay(1000);
297 }
298
299 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100301
302 if (usbhub_init())
303 du440_post_errors++;
304
305 if (dvi_init())
306 du440_post_errors++;
307
308 return 0;
309}
310
311int pld_revision(void)
312{
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100313 out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
314 return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100315}
316
317int board_revision(void)
318{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319 int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
320 >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100321
322 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
323 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
324}
325
326#if defined(CONFIG_SHOW_ACTIVITY)
327void board_show_activity (ulong timestamp)
328{
329 if ((timestamp % 100) == 0)
330 out_be32((void*)GPIO1_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100332}
333
334void show_activity(int arg)
335{
336}
337#endif /* CONFIG_SHOW_ACTIVITY */
338
339int du440_phy_addr(int devnum)
340{
341 if (board_revision() == 0)
342 return devnum;
343
344 return devnum + 1;
345}
346
347int checkboard(void)
348{
349 char serno[32];
350
351 puts("Board: DU440");
352
353 if (getenv_r("serial#", serno, sizeof(serno)) > 0) {
354 puts(", serial# ");
355 puts(serno);
356 }
357
358 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
359 board_revision(), pld_revision());
360 return (0);
361}
362
363/*
364 * pci_pre_init
365 *
366 * This routine is called just prior to registering the hose and gives
367 * the board the opportunity to check things. Returning a value of zero
368 * indicates that things are bad & PCI initialization should be aborted.
369 *
370 * Different boards may wish to customize the pci controller structure
371 * (add regions, override default access routines, etc) or perform
372 * certain pre-initialization actions.
373 */
374#if defined(CONFIG_PCI)
375int pci_pre_init(struct pci_controller *hose)
376{
377 unsigned long addr;
378
379 /*
380 * Set priority for all PLB3 devices to 0.
381 * Set PLB3 arbiter to fair mode.
382 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200383 mfsdr(SD0_AMP1, addr);
384 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
385 addr = mfdcr(PLB3_ACR);
386 mtdcr(PLB3_ACR, addr | 0x80000000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100387
388 /*
389 * Set priority for all PLB4 devices to 0.
390 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200391 mfsdr(SD0_AMP0, addr);
392 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
393 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
394 mtdcr(PLB4_ACR, addr);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100395
396 /*
397 * Set Nebula PLB4 arbiter to fair mode.
398 */
399 /* Segment0 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200400 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
401 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
402 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
403 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
404 mtdcr(PLB0_ACR, addr);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100405
406 /* Segment1 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200407 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
408 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
409 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
410 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
411 mtdcr(PLB1_ACR, addr);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100412
413 return 1;
414}
415#endif /* defined(CONFIG_PCI) */
416
417/*
418 * pci_target_init
419 *
420 * The bootstrap configuration provides default settings for the pci
421 * inbound map (PIM). But the bootstrap config choices are limited and
422 * may not be sufficient for a given board.
423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100425void pci_target_init(struct pci_controller *hose)
426{
427 /*
428 * Set up Direct MMIO registers
429 */
430 /*
431 * PowerPC440EPX PCI Master configuration.
432 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
433 * PLB address 0xA0000000-0xDFFFFFFF
434 * ==> PCI address 0xA0000000-0xDFFFFFFF
435 * Use byte reversed out routines to handle endianess.
436 * Make this region non-prefetchable.
437 */
438 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
439 /* - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440 out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
441 out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100442 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
443 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
444 /* and enable region */
445
446 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
447 /* - disabled b4 setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448 out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
449 out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100450 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
451 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
452 /* and enable region */
453
454 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
455 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
456 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
457 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
458
459 /*
460 * Set up Configuration registers
461 */
462
463 /* Program the board's subsystem id/vendor id */
464 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
465 PCI_VENDOR_ID_ESDGMBH);
466 pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
467
468 pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
469
470 /* Configure command register as bus master */
471 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
472
473 /* 240nS PCI clock */
474 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
475
476 /* No error reporting */
477 pci_write_config_word(0, PCI_ERREN, 0);
478
479 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
480
481}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100483
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100485void pci_master_init(struct pci_controller *hose)
486{
487 unsigned short temp_short;
488
489 /*
490 * Write the PowerPC440 EP PCI Configuration regs.
491 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
492 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
493 */
494 pci_read_config_word(0, PCI_COMMAND, &temp_short);
495 pci_write_config_word(0, PCI_COMMAND,
496 temp_short | PCI_COMMAND_MASTER |
497 PCI_COMMAND_MEMORY);
498}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100500
501/*
502 * is_pci_host
503 *
504 * This routine is called to determine if a pci scan should be
505 * performed. With various hardware environments (especially cPCI and
506 * PPMC) it's insufficient to depend on the state of the arbiter enable
507 * bit in the strap register, or generic host/adapter assumptions.
508 *
509 * Rather than hard-code a bad assumption in the general 440 code, the
510 * 440 pci code requires the board to decide at runtime.
511 *
512 * Return 0 for adapter mode, non-zero for host (monarch) mode.
513 */
514#if defined(CONFIG_PCI)
515int is_pci_host(struct pci_controller *hose)
516{
517 /* always configured as host. */
518 return (1);
519}
520#endif /* defined(CONFIG_PCI) */
521
522int last_stage_init(void)
523{
524 int e, i;
525
526 /* everyting is ok: turn on POST-LED */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100528
529 /* slowly blink on errors and finally keep LED off */
530 for (e = 0; e < du440_post_errors; e++) {
531 out_be32((void*)GPIO1_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100533
534 for (i = 0; i < 500; i++)
535 udelay(1000);
536
537 out_be32((void*)GPIO1_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100539
540 for (i = 0; i < 500; i++)
541 udelay(1000);
542 }
543
544 return 0;
545}
546
547#if defined(CONFIG_I2C_MULTI_BUS)
548/*
549 * read field strength from I2C ADC
550 */
551int dcf77_status(void)
552{
553 unsigned int oldbus;
554 uchar u[2];
555 int mv;
556
557 oldbus = I2C_GET_BUS();
558 I2C_SET_BUS(1);
559
560 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
561 I2C_SET_BUS(oldbus);
562 return -1;
563 }
564
565 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
566
567 I2C_SET_BUS(oldbus);
568 return mv;
569}
570
571int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
572{
573 int mv;
574 u32 pin, pinold;
575 unsigned long long t1, t2;
576 bd_t *bd = gd->bd;
577
578 printf("DCF77: ");
579 mv = dcf77_status();
580 if (mv > 0)
581 printf("signal=%d mV\n", mv);
582 else
583 printf("ERROR - no signal\n");
584
585 t1 = t2 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586 pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100587 while (!ctrlc()) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588 pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100589 if (pin && !pinold) { /* bit start */
590 t1 = get_ticks();
591 if (t2 && ((unsigned int)(t1 - t2) /
592 (bd->bi_procfreq / 1000) >= 1800))
593 printf("Start of minute\n");
594
595 t2 = t1;
596 }
597 if (t1 && !pin && pinold) { /* bit end */
598 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
599 (bd->bi_procfreq / 1000));
600 }
601 pinold = pin;
602 }
603
604 printf("Abort\n");
605 return 0;
606}
607U_BOOT_CMD(
608 dcf77, 1, 1, do_dcf77,
Peter Tyser2fb26042009-01-27 18:03:12 -0600609 "Check DCF77 receiver",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200610 ""
611);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100612
613/*
614 * initialize USB hub via I2C1
615 */
616int usbhub_init(void)
617{
618 int reg;
619 int ret = 0;
620 unsigned int oldbus;
621 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
622 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
623 0x32};
624 uchar stcd;
625
626 printf("Hub: ");
627
628 oldbus = I2C_GET_BUS();
629 I2C_SET_BUS(1);
630
631 for (reg = 0; reg < sizeof(u); reg++)
632 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
633 ret = -1;
634 break;
635 }
636
637 if (ret == 0) {
638 stcd = 0x03;
639 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
640 ret = -1;
641 }
642
643 if (ret == 0)
644 printf("initialized\n");
645 else
646 printf("failed - cannot initialize USB hub\n");
647
648 I2C_SET_BUS(oldbus);
649 return ret;
650}
651
652int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
653{
654 usbhub_init();
655 return 0;
656}
657U_BOOT_CMD(
658 hubinit, 1, 1, do_hubinit,
Peter Tyser2fb26042009-01-27 18:03:12 -0600659 "Initialize USB hub",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200660 ""
661);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100662#endif /* CONFIG_I2C_MULTI_BUS */
663
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200664#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100665int boot_eeprom_write (unsigned dev_addr,
666 unsigned offset,
667 uchar *buffer,
668 unsigned cnt)
669{
670 unsigned end = offset + cnt;
671 unsigned blk_off;
672 int rcode = 0;
673
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200674#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100675 eeprom_write_enable(dev_addr, 1);
676#endif
677 /*
678 * Write data until done or would cross a write page boundary.
679 * We must write the address again when changing pages
680 * because the address counter only increments within a page.
681 */
682
683 while (offset < end) {
684 unsigned alen, len;
685 unsigned maxlen;
686
687 uchar addr[2];
688
689 blk_off = offset & 0xFF; /* block offset */
690
691 addr[0] = offset >> 8; /* block number */
692 addr[1] = blk_off; /* block offset */
693 alen = 2;
694 addr[0] |= dev_addr; /* insert device address */
695
696 len = end - offset;
697
698 /*
699 * For a FRAM device there is no limit on the number of the
700 * bytes that can be ccessed with the single read or write
701 * operation.
702 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200703#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100704
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200705#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100706#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
707
708 maxlen = BOOT_EEPROM_PAGE_SIZE -
709 BOOT_EEPROM_PAGE_OFFSET(blk_off);
710#else
711 maxlen = 0x100 - blk_off;
712#endif
713 if (maxlen > I2C_RXTX_LEN)
714 maxlen = I2C_RXTX_LEN;
715
716 if (len > maxlen)
717 len = maxlen;
718
719 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
720 rcode = 1;
721
722 buffer += len;
723 offset += len;
724
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200725#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
726 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100727#endif
728 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200729#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100730 eeprom_write_enable(dev_addr, 0);
731#endif
732 return rcode;
733}
734
735int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
736{
737 ulong sdsdp[4];
738
739 if (argc > 1) {
740 if (!strcmp(argv[1], "533")) {
741 printf("Bootstrapping for 533MHz\n");
742 sdsdp[0] = 0x87788252;
743 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
744 sdsdp[1] = 0x095fa030;
745 sdsdp[2] = 0x40082350;
746 sdsdp[3] = 0x0d050000;
747 } else if (!strcmp(argv[1], "533-66")) {
748 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
749 sdsdp[0] = 0x87788252;
750 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
751 sdsdp[1] = 0x0957a030;
752 sdsdp[2] = 0x40082350;
753 sdsdp[3] = 0x0d050000;
754 } else if (!strcmp(argv[1], "667")) {
755 printf("Bootstrapping for 667MHz\n");
756 sdsdp[0] = 0x8778a256;
757 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
758 sdsdp[1] = 0x0947a030;
759 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
760 * -> not working when overclocking 533MHz chips
761 * -> untested on 667MHz chips */
762 /* sdsdp[1]=0x095fa030; */
763 sdsdp[2] = 0x40082350;
764 sdsdp[3] = 0x0d050000;
Matthias Fuchsdf8c1ce2008-10-07 13:13:09 +0200765 } else if (!strcmp(argv[1], "667-166")) {
766 printf("Bootstrapping for 667-166MHz\n");
767 sdsdp[0] = 0x8778a252;
768 sdsdp[1] = 0x09d7a030;
769 sdsdp[2] = 0x40082350;
770 sdsdp[3] = 0x0d050000;
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100771 }
772 } else {
773 printf("Bootstrapping for 533MHz (default)\n");
774 sdsdp[0] = 0x87788252;
775 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
776 sdsdp[1] = 0x095fa030;
777 sdsdp[2] = 0x40082350;
778 sdsdp[3] = 0x0d050000;
779 }
780
781 printf("Writing boot EEPROM ...\n");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200782 if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100783 0, (uchar*)sdsdp, 16) != 0)
784 printf("boot_eeprom_write failed\n");
785 else
786 printf("done (dump via 'i2c md 52 0.1 10')\n");
787
788 return 0;
789}
790U_BOOT_CMD(
791 sbe, 2, 0, do_setup_boot_eeprom,
Peter Tyser2fb26042009-01-27 18:03:12 -0600792 "setup boot eeprom",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200793 ""
794);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100795
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200796#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100797/*
798 * Input: <dev_addr> I2C address of EEPROM device to enable.
799 * <state> -1: deliver current state
800 * 0: disable write
801 * 1: enable write
802 * Returns: -1: wrong device address
803 * 0: dis-/en- able done
804 * 0/1: current state if <state> was -1.
805 */
806int eeprom_write_enable (unsigned dev_addr, int state)
807{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200808 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
809 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100810 return -1;
811 else {
812 switch (state) {
813 case 1:
814 /* Enable write access, clear bit GPIO_SINT2. */
815 out_be32((void*)GPIO0_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200816 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100817 state = 0;
818 break;
819 case 0:
820 /* Disable write access, set bit GPIO_SINT2. */
821 out_be32((void*)GPIO0_OR,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200822 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100823 state = 0;
824 break;
825 default:
826 /* Read current status back. */
827 state = (0 == (in_be32((void*)GPIO0_OR) &
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200828 CONFIG_SYS_GPIO0_EP_EEP));
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100829 break;
830 }
831 }
832 return state;
833}
834
835int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
836{
837 int query = argc == 1;
838 int state = 0;
839
840 if (query) {
841 /* Query write access state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200842 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100843 if (state < 0)
844 puts ("Query of write access state failed.\n");
845 else {
846 printf ("Write access for device 0x%0x is %sabled.\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200847 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100848 state = 0;
849 }
850 } else {
851 if ('0' == argv[1][0]) {
852 /* Disable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200853 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100854 } else {
855 /* Enable write access. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200856 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100857 }
858 if (state < 0)
859 puts ("Setup of write access state failed.\n");
860 }
861
862 return state;
863}
864
865U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200866 "Enable / disable / query EEPROM write access",
867 ""
868);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200869#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100870
871static int got_pldirq;
872
873static int pld_interrupt(u32 arg)
874{
875 int rc = -1; /* not for us */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100876 u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100877
878 /* check for PLD interrupt */
879 if (status & PWR_INT_FLAG) {
880 /* reset this int */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100881 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100882 rc = 0;
883 got_pldirq = 1; /* trigger backend */
884 }
885
886 return rc;
887}
888
889int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
890{
891 got_pldirq = 0;
892
893 /* clear any pending interrupt */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100894 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100895
896 irq_install_handler(CPLD_IRQ,
897 (interrupt_handler_t *)pld_interrupt, 0);
898
899 printf("Waiting ...\n");
900 while(!got_pldirq) {
901 /* Abort if ctrl-c was pressed */
902 if (ctrlc()) {
903 puts("\nAbort\n");
904 break;
905 }
906 }
907 if (got_pldirq) {
908 printf("Got interrupt!\n");
909 printf("Power %sready!\n",
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100910 in_8((void *)CONFIG_SYS_CPLD_BASE) &
911 PWR_RDY ? "":"NOT ");
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100912 }
913
914 irq_free_handler(CPLD_IRQ);
915 return 0;
916}
917U_BOOT_CMD(
918 wpi, 1, 1, do_waitpwrirq,
Peter Tyser2fb26042009-01-27 18:03:12 -0600919 "Wait for power change interrupt",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200920 ""
921);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100922
923/*
924 * initialize DVI panellink transmitter
925 */
926int dvi_init(void)
927{
928 int i;
929 int ret = 0;
930 unsigned int oldbus;
931 uchar u[] = {0x08, 0x34,
932 0x09, 0x20,
933 0x0a, 0x90,
934 0x0c, 0x89,
935 0x08, 0x35};
936
937 printf("DVI: ");
938
939 oldbus = I2C_GET_BUS();
940 I2C_SET_BUS(0);
941
942 for (i = 0; i < sizeof(u); i += 2)
943 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
944 ret = -1;
945 break;
946 }
947
948 if (ret == 0)
949 printf("initialized\n");
950 else
951 printf("failed - cannot initialize DVI transmitter\n");
952
953 I2C_SET_BUS(oldbus);
954 return ret;
955}
956
957int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
958{
959 dvi_init();
960 return 0;
961}
962U_BOOT_CMD(
963 dviinit, 1, 1, do_dviinit,
Peter Tyser2fb26042009-01-27 18:03:12 -0600964 "Initialize DVI Panellink transmitter",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200965 ""
966);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100967
968/*
969 * TODO: 'time' command might be useful for others as well.
970 * Move to 'common' directory.
971 */
972int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
973{
974 unsigned long long start, end;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200975 char c, cmd[CONFIG_SYS_CBSIZE];
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100976 char *p, *d = cmd;
977 int ret, i;
978 ulong us;
979
980 for (i = 1; i < argc; i++) {
981 p = argv[i];
982
983 if (i > 1)
984 *d++ = ' ';
985
986 while ((c = *p++) != '\0') {
987 *d++ = c;
988 }
989 }
990 *d = '\0';
991
992 start = get_ticks();
993 ret = run_command (cmd, 0);
994 end = get_ticks();
995
Stefan Roeseb0021442008-07-10 09:58:06 +0200996 printf("ticks=%ld\n", (ulong)(end - start));
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100997 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
Stefan Roeseb0021442008-07-10 09:58:06 +0200998 printf("usec=%ld\n", us);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +0100999
1000 return ret;
1001}
1002U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001003 time, CONFIG_SYS_MAXARGS, 1, do_time,
Peter Tyser2fb26042009-01-27 18:03:12 -06001004 "run command and output execution time",
Wolfgang Denka89c33d2009-05-24 17:06:54 +02001005 ""
1006);
Matthias Fuchs15a08bc2008-01-17 10:52:30 +01001007
1008extern void video_hw_rectfill (
1009 unsigned int bpp, /* bytes per pixel */
1010 unsigned int dst_x, /* dest pos x */
1011 unsigned int dst_y, /* dest pos y */
1012 unsigned int dim_x, /* frame width */
1013 unsigned int dim_y, /* frame height */
1014 unsigned int color /* fill color */
1015 );
1016
1017/*
1018 * graphics demo
1019 * draw rectangles using pseudorandom number generator
1020 * (see http://www.embedded.com/columns/technicalinsights/20900500)
1021 */
1022unsigned int rprime = 9972;
1023static unsigned int r;
1024static unsigned int Y;
1025
1026unsigned int prng(unsigned int max)
1027{
1028 if (r == 0 || r == 1 || r == -1)
1029 r = rprime; /* keep from getting stuck */
1030
1031 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
1032 Y = (r >> 16) % max; /* choose upper bits and reduce */
1033 return Y;
1034}
1035
1036int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
1037{
1038 unsigned int color;
1039 unsigned int x, y, dx, dy;
1040
1041 while (!ctrlc()) {
1042 x = prng(1280 - 1);
1043 y = prng(1024 - 1);
1044 dx = prng(1280- x - 1);
1045 dy = prng(1024 - y - 1);
1046 color = prng(0x10000);
1047 video_hw_rectfill(2, x, y, dx, dy, color);
1048 }
1049
1050 return 0;
1051}
1052U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001053 gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
Peter Tyser2fb26042009-01-27 18:03:12 -06001054 "demo",
Wolfgang Denka89c33d2009-05-24 17:06:54 +02001055 ""
1056);