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Sricharanbb772a52011-11-15 09:50:00 -05001/*
2 * OMAP44xx EMIF header
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Aneesh V <aneesh@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _EMIF_H_
14#define _EMIF_H_
15#include <asm/types.h>
16#include <common.h>
17
18/* Base address */
19#define EMIF1_BASE 0x4c000000
20#define EMIF2_BASE 0x4d000000
21
Tom Rinifda35eb2012-07-03 08:51:34 -070022/* Registers shifts, masks and values */
Sricharanbb772a52011-11-15 09:50:00 -050023
24/* EMIF_MOD_ID_REV */
25#define EMIF_REG_SCHEME_SHIFT 30
26#define EMIF_REG_SCHEME_MASK (0x3 << 30)
27#define EMIF_REG_MODULE_ID_SHIFT 16
28#define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
29#define EMIF_REG_RTL_VERSION_SHIFT 11
30#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
31#define EMIF_REG_MAJOR_REVISION_SHIFT 8
32#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
33#define EMIF_REG_MINOR_REVISION_SHIFT 0
34#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
35
36/* STATUS */
37#define EMIF_REG_BE_SHIFT 31
38#define EMIF_REG_BE_MASK (1 << 31)
39#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30
40#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
41#define EMIF_REG_FAST_INIT_SHIFT 29
42#define EMIF_REG_FAST_INIT_MASK (1 << 29)
43#define EMIF_REG_PHY_DLL_READY_SHIFT 2
44#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
45
46/* SDRAM_CONFIG */
47#define EMIF_REG_SDRAM_TYPE_SHIFT 29
48#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
Tom Rinifda35eb2012-07-03 08:51:34 -070049#define EMIF_REG_SDRAM_TYPE_DDR1 0
50#define EMIF_REG_SDRAM_TYPE_LPDDR1 1
51#define EMIF_REG_SDRAM_TYPE_DDR2 2
52#define EMIF_REG_SDRAM_TYPE_DDR3 3
53#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
54#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
Sricharanbb772a52011-11-15 09:50:00 -050055#define EMIF_REG_IBANK_POS_SHIFT 27
56#define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
57#define EMIF_REG_DDR_TERM_SHIFT 24
58#define EMIF_REG_DDR_TERM_MASK (0x7 << 24)
59#define EMIF_REG_DDR2_DDQS_SHIFT 23
60#define EMIF_REG_DDR2_DDQS_MASK (1 << 23)
61#define EMIF_REG_DYN_ODT_SHIFT 21
62#define EMIF_REG_DYN_ODT_MASK (0x3 << 21)
63#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20
64#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20)
65#define EMIF_REG_SDRAM_DRIVE_SHIFT 18
66#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18)
67#define EMIF_REG_CWL_SHIFT 16
68#define EMIF_REG_CWL_MASK (0x3 << 16)
69#define EMIF_REG_NARROW_MODE_SHIFT 14
70#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14)
71#define EMIF_REG_CL_SHIFT 10
72#define EMIF_REG_CL_MASK (0xf << 10)
73#define EMIF_REG_ROWSIZE_SHIFT 7
74#define EMIF_REG_ROWSIZE_MASK (0x7 << 7)
75#define EMIF_REG_IBANK_SHIFT 4
76#define EMIF_REG_IBANK_MASK (0x7 << 4)
77#define EMIF_REG_EBANK_SHIFT 3
78#define EMIF_REG_EBANK_MASK (1 << 3)
79#define EMIF_REG_PAGESIZE_SHIFT 0
80#define EMIF_REG_PAGESIZE_MASK (0x7 << 0)
81
82/* SDRAM_CONFIG_2 */
83#define EMIF_REG_CS1NVMEN_SHIFT 30
84#define EMIF_REG_CS1NVMEN_MASK (1 << 30)
85#define EMIF_REG_EBANK_POS_SHIFT 27
86#define EMIF_REG_EBANK_POS_MASK (1 << 27)
87#define EMIF_REG_RDBNUM_SHIFT 4
88#define EMIF_REG_RDBNUM_MASK (0x3 << 4)
89#define EMIF_REG_RDBSIZE_SHIFT 0
90#define EMIF_REG_RDBSIZE_MASK (0x7 << 0)
91
92/* SDRAM_REF_CTRL */
93#define EMIF_REG_INITREF_DIS_SHIFT 31
94#define EMIF_REG_INITREF_DIS_MASK (1 << 31)
95#define EMIF_REG_SRT_SHIFT 29
96#define EMIF_REG_SRT_MASK (1 << 29)
97#define EMIF_REG_ASR_SHIFT 28
98#define EMIF_REG_ASR_MASK (1 << 28)
99#define EMIF_REG_PASR_SHIFT 24
100#define EMIF_REG_PASR_MASK (0x7 << 24)
101#define EMIF_REG_REFRESH_RATE_SHIFT 0
102#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0)
103
104/* SDRAM_REF_CTRL_SHDW */
105#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0
106#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
107
108/* SDRAM_TIM_1 */
109#define EMIF_REG_T_RP_SHIFT 25
110#define EMIF_REG_T_RP_MASK (0xf << 25)
111#define EMIF_REG_T_RCD_SHIFT 21
112#define EMIF_REG_T_RCD_MASK (0xf << 21)
113#define EMIF_REG_T_WR_SHIFT 17
114#define EMIF_REG_T_WR_MASK (0xf << 17)
115#define EMIF_REG_T_RAS_SHIFT 12
116#define EMIF_REG_T_RAS_MASK (0x1f << 12)
117#define EMIF_REG_T_RC_SHIFT 6
118#define EMIF_REG_T_RC_MASK (0x3f << 6)
119#define EMIF_REG_T_RRD_SHIFT 3
120#define EMIF_REG_T_RRD_MASK (0x7 << 3)
121#define EMIF_REG_T_WTR_SHIFT 0
122#define EMIF_REG_T_WTR_MASK (0x7 << 0)
123
124/* SDRAM_TIM_1_SHDW */
125#define EMIF_REG_T_RP_SHDW_SHIFT 25
126#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
127#define EMIF_REG_T_RCD_SHDW_SHIFT 21
128#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
129#define EMIF_REG_T_WR_SHDW_SHIFT 17
130#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
131#define EMIF_REG_T_RAS_SHDW_SHIFT 12
132#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12)
133#define EMIF_REG_T_RC_SHDW_SHIFT 6
134#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6)
135#define EMIF_REG_T_RRD_SHDW_SHIFT 3
136#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3)
137#define EMIF_REG_T_WTR_SHDW_SHIFT 0
138#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0)
139
140/* SDRAM_TIM_2 */
141#define EMIF_REG_T_XP_SHIFT 28
142#define EMIF_REG_T_XP_MASK (0x7 << 28)
143#define EMIF_REG_T_ODT_SHIFT 25
144#define EMIF_REG_T_ODT_MASK (0x7 << 25)
145#define EMIF_REG_T_XSNR_SHIFT 16
146#define EMIF_REG_T_XSNR_MASK (0x1ff << 16)
147#define EMIF_REG_T_XSRD_SHIFT 6
148#define EMIF_REG_T_XSRD_MASK (0x3ff << 6)
149#define EMIF_REG_T_RTP_SHIFT 3
150#define EMIF_REG_T_RTP_MASK (0x7 << 3)
151#define EMIF_REG_T_CKE_SHIFT 0
152#define EMIF_REG_T_CKE_MASK (0x7 << 0)
153
154/* SDRAM_TIM_2_SHDW */
155#define EMIF_REG_T_XP_SHDW_SHIFT 28
156#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28)
157#define EMIF_REG_T_ODT_SHDW_SHIFT 25
158#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25)
159#define EMIF_REG_T_XSNR_SHDW_SHIFT 16
160#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
161#define EMIF_REG_T_XSRD_SHDW_SHIFT 6
162#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
163#define EMIF_REG_T_RTP_SHDW_SHIFT 3
164#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3)
165#define EMIF_REG_T_CKE_SHDW_SHIFT 0
166#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0)
167
168/* SDRAM_TIM_3 */
169#define EMIF_REG_T_CKESR_SHIFT 21
170#define EMIF_REG_T_CKESR_MASK (0x7 << 21)
171#define EMIF_REG_ZQ_ZQCS_SHIFT 15
172#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15)
173#define EMIF_REG_T_TDQSCKMAX_SHIFT 13
174#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13)
175#define EMIF_REG_T_RFC_SHIFT 4
176#define EMIF_REG_T_RFC_MASK (0x1ff << 4)
177#define EMIF_REG_T_RAS_MAX_SHIFT 0
178#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
179
180/* SDRAM_TIM_3_SHDW */
181#define EMIF_REG_T_CKESR_SHDW_SHIFT 21
182#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21)
183#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15
184#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
185#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13
186#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
187#define EMIF_REG_T_RFC_SHDW_SHIFT 4
188#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4)
189#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0
190#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
191
192/* LPDDR2_NVM_TIM */
193#define EMIF_REG_NVM_T_XP_SHIFT 28
194#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28)
195#define EMIF_REG_NVM_T_WTR_SHIFT 24
196#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24)
197#define EMIF_REG_NVM_T_RP_SHIFT 20
198#define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
199#define EMIF_REG_NVM_T_WRA_SHIFT 16
200#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16)
201#define EMIF_REG_NVM_T_RRD_SHIFT 8
202#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8)
203#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0
204#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0)
205
206/* LPDDR2_NVM_TIM_SHDW */
207#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28
208#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
209#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24
210#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
211#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20
212#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
213#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16
214#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
215#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8
216#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
217#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
218#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
219
220/* PWR_MGMT_CTRL */
221#define EMIF_REG_IDLEMODE_SHIFT 30
222#define EMIF_REG_IDLEMODE_MASK (0x3 << 30)
223#define EMIF_REG_PD_TIM_SHIFT 12
224#define EMIF_REG_PD_TIM_MASK (0xf << 12)
225#define EMIF_REG_DPD_EN_SHIFT 11
226#define EMIF_REG_DPD_EN_MASK (1 << 11)
227#define EMIF_REG_LP_MODE_SHIFT 8
228#define EMIF_REG_LP_MODE_MASK (0x7 << 8)
229#define EMIF_REG_SR_TIM_SHIFT 4
230#define EMIF_REG_SR_TIM_MASK (0xf << 4)
231#define EMIF_REG_CS_TIM_SHIFT 0
232#define EMIF_REG_CS_TIM_MASK (0xf << 0)
233
234/* PWR_MGMT_CTRL_SHDW */
SRICHARAN Raaec4482012-03-12 02:25:46 +0000235#define EMIF_REG_PD_TIM_SHDW_SHIFT 12
236#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12)
Sricharanbb772a52011-11-15 09:50:00 -0500237#define EMIF_REG_SR_TIM_SHDW_SHIFT 4
238#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4)
239#define EMIF_REG_CS_TIM_SHDW_SHIFT 0
240#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0)
241
242/* LPDDR2_MODE_REG_DATA */
243#define EMIF_REG_VALUE_0_SHIFT 0
244#define EMIF_REG_VALUE_0_MASK (0x7f << 0)
245
246/* LPDDR2_MODE_REG_CFG */
247#define EMIF_REG_CS_SHIFT 31
248#define EMIF_REG_CS_MASK (1 << 31)
249#define EMIF_REG_REFRESH_EN_SHIFT 30
250#define EMIF_REG_REFRESH_EN_MASK (1 << 30)
251#define EMIF_REG_ADDRESS_SHIFT 0
252#define EMIF_REG_ADDRESS_MASK (0xff << 0)
253
254/* OCP_CONFIG */
255#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24
256#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24)
257#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20
258#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20)
259#define EMIF_REG_LL_THRESH_MAX_SHIFT 16
260#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16)
261#define EMIF_REG_PR_OLD_COUNT_SHIFT 0
262#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0)
263
264/* OCP_CFG_VAL_1 */
265#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30
266#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
267#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28
268#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
269#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8
270#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
271#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0
272#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
273
274/* OCP_CFG_VAL_2 */
275#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16
276#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
277#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8
278#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
279#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0
280#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
281
282/* IODFT_TLGC */
283#define EMIF_REG_TLEC_SHIFT 16
284#define EMIF_REG_TLEC_MASK (0xffff << 16)
285#define EMIF_REG_MT_SHIFT 14
286#define EMIF_REG_MT_MASK (1 << 14)
287#define EMIF_REG_ACT_CAP_EN_SHIFT 13
288#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13)
289#define EMIF_REG_OPG_LD_SHIFT 12
290#define EMIF_REG_OPG_LD_MASK (1 << 12)
291#define EMIF_REG_RESET_PHY_SHIFT 10
292#define EMIF_REG_RESET_PHY_MASK (1 << 10)
293#define EMIF_REG_MMS_SHIFT 8
294#define EMIF_REG_MMS_MASK (1 << 8)
295#define EMIF_REG_MC_SHIFT 4
296#define EMIF_REG_MC_MASK (0x3 << 4)
297#define EMIF_REG_PC_SHIFT 1
298#define EMIF_REG_PC_MASK (0x7 << 1)
299#define EMIF_REG_TM_SHIFT 0
300#define EMIF_REG_TM_MASK (1 << 0)
301
302/* IODFT_CTRL_MISR_RSLT */
303#define EMIF_REG_DQM_TLMR_SHIFT 16
304#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16)
305#define EMIF_REG_CTL_TLMR_SHIFT 0
306#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0)
307
308/* IODFT_ADDR_MISR_RSLT */
309#define EMIF_REG_ADDR_TLMR_SHIFT 0
310#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0)
311
312/* IODFT_DATA_MISR_RSLT_1 */
313#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0
314#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
315
316/* IODFT_DATA_MISR_RSLT_2 */
317#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0
318#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
319
320/* IODFT_DATA_MISR_RSLT_3 */
321#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0
322#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
323
324/* PERF_CNT_1 */
325#define EMIF_REG_COUNTER1_SHIFT 0
326#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0)
327
328/* PERF_CNT_2 */
329#define EMIF_REG_COUNTER2_SHIFT 0
330#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0)
331
332/* PERF_CNT_CFG */
333#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31
334#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
335#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30
336#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30)
337#define EMIF_REG_CNTR2_CFG_SHIFT 16
338#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16)
339#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15
340#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
341#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14
342#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14)
343#define EMIF_REG_CNTR1_CFG_SHIFT 0
344#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0)
345
346/* PERF_CNT_SEL */
347#define EMIF_REG_MCONNID2_SHIFT 24
348#define EMIF_REG_MCONNID2_MASK (0xff << 24)
349#define EMIF_REG_REGION_SEL2_SHIFT 16
350#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16)
351#define EMIF_REG_MCONNID1_SHIFT 8
352#define EMIF_REG_MCONNID1_MASK (0xff << 8)
353#define EMIF_REG_REGION_SEL1_SHIFT 0
354#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0)
355
356/* PERF_CNT_TIM */
357#define EMIF_REG_TOTAL_TIME_SHIFT 0
358#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0)
359
360/* READ_IDLE_CTRL */
361#define EMIF_REG_READ_IDLE_LEN_SHIFT 16
362#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16)
363#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0
364#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
365
366/* READ_IDLE_CTRL_SHDW */
367#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16
368#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
369#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
370#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
371
372/* IRQ_EOI */
373#define EMIF_REG_EOI_SHIFT 0
374#define EMIF_REG_EOI_MASK (1 << 0)
375
376/* IRQSTATUS_RAW_SYS */
377#define EMIF_REG_DNV_SYS_SHIFT 2
378#define EMIF_REG_DNV_SYS_MASK (1 << 2)
379#define EMIF_REG_TA_SYS_SHIFT 1
380#define EMIF_REG_TA_SYS_MASK (1 << 1)
381#define EMIF_REG_ERR_SYS_SHIFT 0
382#define EMIF_REG_ERR_SYS_MASK (1 << 0)
383
384/* IRQSTATUS_RAW_LL */
385#define EMIF_REG_DNV_LL_SHIFT 2
386#define EMIF_REG_DNV_LL_MASK (1 << 2)
387#define EMIF_REG_TA_LL_SHIFT 1
388#define EMIF_REG_TA_LL_MASK (1 << 1)
389#define EMIF_REG_ERR_LL_SHIFT 0
390#define EMIF_REG_ERR_LL_MASK (1 << 0)
391
392/* IRQSTATUS_SYS */
393
394/* IRQSTATUS_LL */
395
396/* IRQENABLE_SET_SYS */
397#define EMIF_REG_EN_DNV_SYS_SHIFT 2
398#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2)
399#define EMIF_REG_EN_TA_SYS_SHIFT 1
400#define EMIF_REG_EN_TA_SYS_MASK (1 << 1)
401#define EMIF_REG_EN_ERR_SYS_SHIFT 0
402#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0)
403
404/* IRQENABLE_SET_LL */
405#define EMIF_REG_EN_DNV_LL_SHIFT 2
406#define EMIF_REG_EN_DNV_LL_MASK (1 << 2)
407#define EMIF_REG_EN_TA_LL_SHIFT 1
408#define EMIF_REG_EN_TA_LL_MASK (1 << 1)
409#define EMIF_REG_EN_ERR_LL_SHIFT 0
410#define EMIF_REG_EN_ERR_LL_MASK (1 << 0)
411
412/* IRQENABLE_CLR_SYS */
413
414/* IRQENABLE_CLR_LL */
415
416/* ZQ_CONFIG */
417#define EMIF_REG_ZQ_CS1EN_SHIFT 31
418#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31)
419#define EMIF_REG_ZQ_CS0EN_SHIFT 30
420#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30)
421#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29
422#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29)
423#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28
424#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28)
425#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18
426#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
427#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16
428#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
429#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0
430#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
431
432/* TEMP_ALERT_CONFIG */
433#define EMIF_REG_TA_CS1EN_SHIFT 31
434#define EMIF_REG_TA_CS1EN_MASK (1 << 31)
435#define EMIF_REG_TA_CS0EN_SHIFT 30
436#define EMIF_REG_TA_CS0EN_MASK (1 << 30)
437#define EMIF_REG_TA_SFEXITEN_SHIFT 28
438#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28)
439#define EMIF_REG_TA_DEVWDT_SHIFT 26
440#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26)
441#define EMIF_REG_TA_DEVCNT_SHIFT 24
442#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24)
443#define EMIF_REG_TA_REFINTERVAL_SHIFT 0
444#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
445
446/* OCP_ERR_LOG */
447#define EMIF_REG_MADDRSPACE_SHIFT 14
448#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14)
449#define EMIF_REG_MBURSTSEQ_SHIFT 11
450#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11)
451#define EMIF_REG_MCMD_SHIFT 8
452#define EMIF_REG_MCMD_MASK (0x7 << 8)
453#define EMIF_REG_MCONNID_SHIFT 0
454#define EMIF_REG_MCONNID_MASK (0xff << 0)
455
456/* DDR_PHY_CTRL_1 */
457#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4
458#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
459#define EMIF_REG_READ_LATENCY_SHIFT 0
460#define EMIF_REG_READ_LATENCY_MASK (0xf << 0)
461#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
462#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
463#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
464#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
465
466/* DDR_PHY_CTRL_1_SHDW */
467#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
468#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
469#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0
470#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
471#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
472#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
473#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
474#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
475
476/* DDR_PHY_CTRL_2 */
477#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
478#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
479
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000480/*EMIF_READ_WRITE_LEVELING_CONTROL*/
481#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
482#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
483#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
484#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
485#define EMIF_REG_RDLVLINC_INT_SHIFT 16
486#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
487#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
488#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
489#define EMIF_REG_WRLVLINC_INT_SHIFT 0
490#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
491
492/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
493#define EMIF_REG_RDWRLVL_EN_SHIFT 31
494#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
495#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
496#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
497#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
498#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
499#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
500#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
501#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
502#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
503
504/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
505#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
506#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
507
508/*Leveling Fields */
509#define DDR3_WR_LVL_INT 0x73
510#define DDR3_RD_LVL_INT 0x33
511#define DDR3_RD_LVL_GATE_INT 0x59
512#define RD_RW_LVL_INC_PRE 0x0
513#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
514
515#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
516 | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
517 | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
518 | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
519
520#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
521#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
Lokesh Vutla9100ede2013-02-12 01:33:44 +0000522#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
Lokesh Vutla784ab7c2012-05-22 00:03:25 +0000523
Sricharanbb772a52011-11-15 09:50:00 -0500524/* DMM */
525#define DMM_BASE 0x4E000040
526
527/* Memory Adapter */
528#define MA_BASE 0x482AF040
529
530/* DMM_LISA_MAP */
531#define EMIF_SYS_ADDR_SHIFT 24
532#define EMIF_SYS_ADDR_MASK (0xff << 24)
533#define EMIF_SYS_SIZE_SHIFT 20
534#define EMIF_SYS_SIZE_MASK (0x7 << 20)
535#define EMIF_SDRC_INTL_SHIFT 18
536#define EMIF_SDRC_INTL_MASK (0x3 << 18)
537#define EMIF_SDRC_ADDRSPC_SHIFT 16
538#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16)
539#define EMIF_SDRC_MAP_SHIFT 8
540#define EMIF_SDRC_MAP_MASK (0x3 << 8)
541#define EMIF_SDRC_ADDR_SHIFT 0
542#define EMIF_SDRC_ADDR_MASK (0xff << 0)
543
544/* DMM_LISA_MAP fields */
545#define DMM_SDRC_MAP_UNMAPPED 0
546#define DMM_SDRC_MAP_EMIF1_ONLY 1
547#define DMM_SDRC_MAP_EMIF2_ONLY 2
548#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
549
550#define DMM_SDRC_INTL_NONE 0
551#define DMM_SDRC_INTL_128B 1
552#define DMM_SDRC_INTL_256B 2
553#define DMM_SDRC_INTL_512 3
554
555#define DMM_SDRC_ADDR_SPC_SDRAM 0
556#define DMM_SDRC_ADDR_SPC_NVM 1
557#define DMM_SDRC_ADDR_SPC_INVALID 2
558
559#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
560 (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
561 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
562 (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
563 (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
564
565#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
566 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
567 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
568 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
569
570#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
571 (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
572 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
573 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
574
575/* Trap for invalid TILER PAT entries */
576#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
577 (0 << EMIF_SDRC_ADDR_SHIFT) |\
578 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
579 (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
580 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
581 (0xFF << EMIF_SYS_ADDR_SHIFT))
582
SRICHARAN Rf4010732012-03-12 02:25:37 +0000583#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
584#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13
Sricharanbb772a52011-11-15 09:50:00 -0500585
586/* Reg mapping structure */
587struct emif_reg_struct {
588 u32 emif_mod_id_rev;
589 u32 emif_status;
590 u32 emif_sdram_config;
591 u32 emif_lpddr2_nvm_config;
592 u32 emif_sdram_ref_ctrl;
593 u32 emif_sdram_ref_ctrl_shdw;
594 u32 emif_sdram_tim_1;
595 u32 emif_sdram_tim_1_shdw;
596 u32 emif_sdram_tim_2;
597 u32 emif_sdram_tim_2_shdw;
598 u32 emif_sdram_tim_3;
599 u32 emif_sdram_tim_3_shdw;
600 u32 emif_lpddr2_nvm_tim;
601 u32 emif_lpddr2_nvm_tim_shdw;
602 u32 emif_pwr_mgmt_ctrl;
603 u32 emif_pwr_mgmt_ctrl_shdw;
604 u32 emif_lpddr2_mode_reg_data;
605 u32 padding1[1];
606 u32 emif_lpddr2_mode_reg_data_es2;
607 u32 padding11[1];
608 u32 emif_lpddr2_mode_reg_cfg;
609 u32 emif_l3_config;
610 u32 emif_l3_cfg_val_1;
611 u32 emif_l3_cfg_val_2;
612 u32 emif_iodft_tlgc;
613 u32 padding2[7];
614 u32 emif_perf_cnt_1;
615 u32 emif_perf_cnt_2;
616 u32 emif_perf_cnt_cfg;
617 u32 emif_perf_cnt_sel;
618 u32 emif_perf_cnt_tim;
619 u32 padding3;
620 u32 emif_read_idlectrl;
621 u32 emif_read_idlectrl_shdw;
622 u32 padding4;
623 u32 emif_irqstatus_raw_sys;
624 u32 emif_irqstatus_raw_ll;
625 u32 emif_irqstatus_sys;
626 u32 emif_irqstatus_ll;
627 u32 emif_irqenable_set_sys;
628 u32 emif_irqenable_set_ll;
629 u32 emif_irqenable_clr_sys;
630 u32 emif_irqenable_clr_ll;
631 u32 padding5;
632 u32 emif_zq_config;
633 u32 emif_temp_alert_config;
634 u32 emif_l3_err_log;
SRICHARAN Rf4010732012-03-12 02:25:37 +0000635 u32 emif_rd_wr_lvl_rmp_win;
636 u32 emif_rd_wr_lvl_rmp_ctl;
637 u32 emif_rd_wr_lvl_ctl;
638 u32 padding6[1];
Sricharanbb772a52011-11-15 09:50:00 -0500639 u32 emif_ddr_phy_ctrl_1;
640 u32 emif_ddr_phy_ctrl_1_shdw;
641 u32 emif_ddr_phy_ctrl_2;
SRICHARAN Rf4010732012-03-12 02:25:37 +0000642 u32 padding7[12];
643 u32 emif_rd_wr_exec_thresh;
644 u32 padding8[55];
645 u32 emif_ddr_ext_phy_ctrl_1;
646 u32 emif_ddr_ext_phy_ctrl_1_shdw;
647 u32 emif_ddr_ext_phy_ctrl_2;
648 u32 emif_ddr_ext_phy_ctrl_2_shdw;
649 u32 emif_ddr_ext_phy_ctrl_3;
650 u32 emif_ddr_ext_phy_ctrl_3_shdw;
651 u32 emif_ddr_ext_phy_ctrl_4;
652 u32 emif_ddr_ext_phy_ctrl_4_shdw;
653 u32 emif_ddr_ext_phy_ctrl_5;
654 u32 emif_ddr_ext_phy_ctrl_5_shdw;
655 u32 emif_ddr_ext_phy_ctrl_6;
656 u32 emif_ddr_ext_phy_ctrl_6_shdw;
657 u32 emif_ddr_ext_phy_ctrl_7;
658 u32 emif_ddr_ext_phy_ctrl_7_shdw;
659 u32 emif_ddr_ext_phy_ctrl_8;
660 u32 emif_ddr_ext_phy_ctrl_8_shdw;
661 u32 emif_ddr_ext_phy_ctrl_9;
662 u32 emif_ddr_ext_phy_ctrl_9_shdw;
663 u32 emif_ddr_ext_phy_ctrl_10;
664 u32 emif_ddr_ext_phy_ctrl_10_shdw;
665 u32 emif_ddr_ext_phy_ctrl_11;
666 u32 emif_ddr_ext_phy_ctrl_11_shdw;
667 u32 emif_ddr_ext_phy_ctrl_12;
668 u32 emif_ddr_ext_phy_ctrl_12_shdw;
669 u32 emif_ddr_ext_phy_ctrl_13;
670 u32 emif_ddr_ext_phy_ctrl_13_shdw;
671 u32 emif_ddr_ext_phy_ctrl_14;
672 u32 emif_ddr_ext_phy_ctrl_14_shdw;
673 u32 emif_ddr_ext_phy_ctrl_15;
674 u32 emif_ddr_ext_phy_ctrl_15_shdw;
675 u32 emif_ddr_ext_phy_ctrl_16;
676 u32 emif_ddr_ext_phy_ctrl_16_shdw;
677 u32 emif_ddr_ext_phy_ctrl_17;
678 u32 emif_ddr_ext_phy_ctrl_17_shdw;
679 u32 emif_ddr_ext_phy_ctrl_18;
680 u32 emif_ddr_ext_phy_ctrl_18_shdw;
681 u32 emif_ddr_ext_phy_ctrl_19;
682 u32 emif_ddr_ext_phy_ctrl_19_shdw;
683 u32 emif_ddr_ext_phy_ctrl_20;
684 u32 emif_ddr_ext_phy_ctrl_20_shdw;
685 u32 emif_ddr_ext_phy_ctrl_21;
686 u32 emif_ddr_ext_phy_ctrl_21_shdw;
687 u32 emif_ddr_ext_phy_ctrl_22;
688 u32 emif_ddr_ext_phy_ctrl_22_shdw;
689 u32 emif_ddr_ext_phy_ctrl_23;
690 u32 emif_ddr_ext_phy_ctrl_23_shdw;
691 u32 emif_ddr_ext_phy_ctrl_24;
692 u32 emif_ddr_ext_phy_ctrl_24_shdw;
Sricharanbb772a52011-11-15 09:50:00 -0500693};
694
695struct dmm_lisa_map_regs {
696 u32 dmm_lisa_map_0;
697 u32 dmm_lisa_map_1;
698 u32 dmm_lisa_map_2;
699 u32 dmm_lisa_map_3;
Lokesh Vutla78314192013-02-12 21:29:07 +0000700 u8 is_ma_present;
Sricharanbb772a52011-11-15 09:50:00 -0500701};
702
703#define CS0 0
704#define CS1 1
705/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
706#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
707
708/*
709 * The period of DDR clk is represented as numerator and denominator for
710 * better accuracy in integer based calculations. However, if the numerator
711 * and denominator are very huge there may be chances of overflow in
712 * calculations. So, as a trade-off keep denominator(and consequently
713 * numerator) within a limit sacrificing some accuracy - but not much
714 * If denominator and numerator are already small (such as at 400 MHz)
715 * no adjustment is needed
716 */
717#define EMIF_PERIOD_DEN_LIMIT 1000
718/*
719 * Maximum number of different frequencies supported by EMIF driver
720 * Determines the number of entries in the pointer array for register
721 * cache
722 */
723#define EMIF_MAX_NUM_FREQUENCIES 6
724/*
725 * Indices into the Addressing Table array.
726 * One entry each for all the different types of devices with different
727 * addressing schemes
728 */
729#define ADDR_TABLE_INDEX64M 0
730#define ADDR_TABLE_INDEX128M 1
731#define ADDR_TABLE_INDEX256M 2
732#define ADDR_TABLE_INDEX512M 3
733#define ADDR_TABLE_INDEX1GS4 4
734#define ADDR_TABLE_INDEX2GS4 5
735#define ADDR_TABLE_INDEX4G 6
736#define ADDR_TABLE_INDEX8G 7
737#define ADDR_TABLE_INDEX1GS2 8
738#define ADDR_TABLE_INDEX2GS2 9
739#define ADDR_TABLE_INDEXMAX 10
740
741/* Number of Row bits */
742#define ROW_9 0
743#define ROW_10 1
744#define ROW_11 2
745#define ROW_12 3
746#define ROW_13 4
747#define ROW_14 5
748#define ROW_15 6
749#define ROW_16 7
750
751/* Number of Column bits */
752#define COL_8 0
753#define COL_9 1
754#define COL_10 2
755#define COL_11 3
756#define COL_7 4 /*Not supported by OMAP included for completeness */
757
758/* Number of Banks*/
759#define BANKS1 0
760#define BANKS2 1
761#define BANKS4 2
762#define BANKS8 3
763
764/* Refresh rate in micro seconds x 10 */
765#define T_REFI_15_6 156
766#define T_REFI_7_8 78
767#define T_REFI_3_9 39
768
769#define EBANK_CS1_DIS 0
770#define EBANK_CS1_EN 1
771
772/* Read Latency used by the device at reset */
773#define RL_BOOT 3
774/* Read Latency for the highest frequency you want to use */
775#ifdef CONFIG_OMAP54XX
776#define RL_FINAL 8
777#else
778#define RL_FINAL 6
779#endif
780
781
782/* Interleaving policies at EMIF level- between banks and Chip Selects */
783#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
784#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
785
786/*
787 * Interleaving policy to be used
788 * Currently set to MAX interleaving for better performance
789 */
790#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
791
792/* State of the core voltage:
793 * This is important for some parameters such as read idle control and
794 * ZQ calibration timings. Timings are much stricter when voltage ramp
795 * is happening compared to when the voltage is stable.
796 * We need to calculate two sets of values for these parameters and use
797 * them accordingly
798 */
799#define LPDDR2_VOLTAGE_STABLE 0
800#define LPDDR2_VOLTAGE_RAMPING 1
801
802/* Length of the forced read idle period in terms of cycles */
803#define EMIF_REG_READ_IDLE_LEN_VAL 5
804
805/* Interval between forced 'read idles' */
806/* To be used when voltage is changed for DPS/DVFS - 1us */
807#define READ_IDLE_INTERVAL_DVFS (1*1000)
808/*
809 * To be used when voltage is not scaled except by Smart Reflex
810 * 50us - or maximum value will do
811 */
812#define READ_IDLE_INTERVAL_NORMAL (50*1000)
813
814
815/*
816 * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
817 * be enough. This shoule be enough also in the case when voltage is changing
818 * due to smart-reflex.
819 */
820#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
821/*
822 * If voltage is changing due to DVFS ZQCS should be performed more
823 * often(every 50us)
824 */
825#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
826
827/* The interval between ZQCL commands as a multiple of ZQCS interval */
828#define REG_ZQ_ZQCL_MULT 4
829/* The interval between ZQINIT commands as a multiple of ZQCL interval */
830#define REG_ZQ_ZQINIT_MULT 3
831/* Enable ZQ Calibration on exiting Self-refresh */
832#define REG_ZQ_SFEXITEN_ENABLE 1
833/*
834 * ZQ Calibration simultaneously on both chip-selects:
835 * Needs one calibration resistor per CS
836 * None of the boards that we know of have this capability
837 * So disabled by default
838 */
839#define REG_ZQ_DUALCALEN_DISABLE 0
840/*
841 * Enable ZQ Calibration by default on CS0. If we are asked to program
842 * the EMIF there will be something connected to CS0 for sure
843 */
844#define REG_ZQ_CS0EN_ENABLE 1
845
846/* EMIF_PWR_MGMT_CTRL register */
847/* Low power modes */
848#define LP_MODE_DISABLE 0
849#define LP_MODE_CLOCK_STOP 1
850#define LP_MODE_SELF_REFRESH 2
851#define LP_MODE_PWR_DN 3
852
853/* REG_DPD_EN */
854#define DPD_DISABLE 0
855#define DPD_ENABLE 1
856
857/* Maximum delay before Low Power Modes */
SRICHARAN Rf4010732012-03-12 02:25:37 +0000858#ifndef CONFIG_OMAP54XX
Sricharanbb772a52011-11-15 09:50:00 -0500859#define REG_CS_TIM 0xF
SRICHARAN Rf4010732012-03-12 02:25:37 +0000860#else
861#define REG_CS_TIM 0x0
862#endif
Sricharanbb772a52011-11-15 09:50:00 -0500863#define REG_SR_TIM 0xF
864#define REG_PD_TIM 0xF
865
866/* EMIF_PWR_MGMT_CTRL register */
867#define EMIF_PWR_MGMT_CTRL (\
868 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
869 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
870 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
871 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
872 ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
873 & EMIF_REG_LP_MODE_MASK) |\
874 ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
875 & EMIF_REG_DPD_EN_MASK))\
876
877#define EMIF_PWR_MGMT_CTRL_SHDW (\
878 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
879 & EMIF_REG_CS_TIM_SHDW_MASK) |\
880 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
881 & EMIF_REG_SR_TIM_SHDW_MASK) |\
882 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
883 & EMIF_REG_PD_TIM_SHDW_MASK) |\
884 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
885 & EMIF_REG_PD_TIM_SHDW_MASK))
886
887/* EMIF_L3_CONFIG register value */
888#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
889#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
SRICHARAN Rf4010732012-03-12 02:25:37 +0000890#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000
Sricharanbb772a52011-11-15 09:50:00 -0500891
892/*
893 * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
894 * All these fields have magic values dependent on frequency and
895 * determined by PHY and DLL integration with EMIF. Setting the magic
896 * values suggested by hw team.
897 */
898#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
899#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
900#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
901#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
902
903/*
904* MR1 value:
905* Burst length : 8
906* Burst type : sequential
907* Wrap : enabled
908* nWR : 3(default). EMIF does not do pre-charge.
909* : So nWR is don't care
910*/
911#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
SRICHARAN Rf4010732012-03-12 02:25:37 +0000912#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3
Sricharanbb772a52011-11-15 09:50:00 -0500913
914/* MR2 */
915#define MR2_RL3_WL1 1
916#define MR2_RL4_WL2 2
917#define MR2_RL5_WL2 3
918#define MR2_RL6_WL3 4
919
920/* MR10: ZQ calibration codes */
921#define MR10_ZQ_ZQCS 0x56
922#define MR10_ZQ_ZQCL 0xAB
923#define MR10_ZQ_ZQINIT 0xFF
924#define MR10_ZQ_ZQRESET 0xC3
925
926/* TEMP_ALERT_CONFIG */
927#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
928#define TEMP_ALERT_CONFIG_DEVCT_1 0
929#define TEMP_ALERT_CONFIG_DEVWDT_32 2
930
931/* MR16 value: refresh full array(no partial array self refresh) */
932#define MR16_REF_FULL_ARRAY 0
933
934/*
935 * Maximum number of entries we keep in our array of timing tables
936 * We need not keep all the speed bins supported by the device
937 * We need to keep timing tables for only the speed bins that we
938 * are interested in
939 */
940#define MAX_NUM_SPEEDBINS 4
941
942/* LPDDR2 Densities */
943#define LPDDR2_DENSITY_64Mb 0
944#define LPDDR2_DENSITY_128Mb 1
945#define LPDDR2_DENSITY_256Mb 2
946#define LPDDR2_DENSITY_512Mb 3
947#define LPDDR2_DENSITY_1Gb 4
948#define LPDDR2_DENSITY_2Gb 5
949#define LPDDR2_DENSITY_4Gb 6
950#define LPDDR2_DENSITY_8Gb 7
951#define LPDDR2_DENSITY_16Gb 8
952#define LPDDR2_DENSITY_32Gb 9
953
954/* LPDDR2 type */
955#define LPDDR2_TYPE_S4 0
956#define LPDDR2_TYPE_S2 1
957#define LPDDR2_TYPE_NVM 2
958
959/* LPDDR2 IO width */
960#define LPDDR2_IO_WIDTH_32 0
961#define LPDDR2_IO_WIDTH_16 1
962#define LPDDR2_IO_WIDTH_8 2
963
964/* Mode register numbers */
965#define LPDDR2_MR0 0
966#define LPDDR2_MR1 1
967#define LPDDR2_MR2 2
968#define LPDDR2_MR3 3
969#define LPDDR2_MR4 4
970#define LPDDR2_MR5 5
971#define LPDDR2_MR6 6
972#define LPDDR2_MR7 7
973#define LPDDR2_MR8 8
974#define LPDDR2_MR9 9
975#define LPDDR2_MR10 10
976#define LPDDR2_MR11 11
977#define LPDDR2_MR16 16
978#define LPDDR2_MR17 17
979#define LPDDR2_MR18 18
980
981/* MR0 */
982#define LPDDR2_MR0_DAI_SHIFT 0
983#define LPDDR2_MR0_DAI_MASK 1
984#define LPDDR2_MR0_DI_SHIFT 1
985#define LPDDR2_MR0_DI_MASK (1 << 1)
986#define LPDDR2_MR0_DNVI_SHIFT 2
987#define LPDDR2_MR0_DNVI_MASK (1 << 2)
988
989/* MR4 */
990#define MR4_SDRAM_REF_RATE_SHIFT 0
991#define MR4_SDRAM_REF_RATE_MASK 7
992#define MR4_TUF_SHIFT 7
993#define MR4_TUF_MASK (1 << 7)
994
995/* MR4 SDRAM Refresh Rate field values */
996#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
997#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
998#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
999#define SDRAM_TEMP_NOMINAL 0x3
1000#define SDRAM_TEMP_RESERVED_4 0x4
1001#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
1002#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
1003#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
1004
1005#define LPDDR2_MANUFACTURER_SAMSUNG 1
1006#define LPDDR2_MANUFACTURER_QIMONDA 2
1007#define LPDDR2_MANUFACTURER_ELPIDA 3
1008#define LPDDR2_MANUFACTURER_ETRON 4
1009#define LPDDR2_MANUFACTURER_NANYA 5
1010#define LPDDR2_MANUFACTURER_HYNIX 6
1011#define LPDDR2_MANUFACTURER_MOSEL 7
1012#define LPDDR2_MANUFACTURER_WINBOND 8
1013#define LPDDR2_MANUFACTURER_ESMT 9
1014#define LPDDR2_MANUFACTURER_SPANSION 11
1015#define LPDDR2_MANUFACTURER_SST 12
1016#define LPDDR2_MANUFACTURER_ZMOS 13
1017#define LPDDR2_MANUFACTURER_INTEL 14
1018#define LPDDR2_MANUFACTURER_NUMONYX 254
1019#define LPDDR2_MANUFACTURER_MICRON 255
1020
1021/* MR8 register fields */
1022#define MR8_TYPE_SHIFT 0x0
1023#define MR8_TYPE_MASK 0x3
1024#define MR8_DENSITY_SHIFT 0x2
1025#define MR8_DENSITY_MASK (0xF << 0x2)
1026#define MR8_IO_WIDTH_SHIFT 0x6
1027#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
1028
Lokesh Vutla9ca8bfe2013-02-04 04:21:59 +00001029/* SDRAM TYPE */
1030#define EMIF_SDRAM_TYPE_DDR2 0x2
1031#define EMIF_SDRAM_TYPE_DDR3 0x3
1032#define EMIF_SDRAM_TYPE_LPDDR2 0x4
1033
Sricharanbb772a52011-11-15 09:50:00 -05001034struct lpddr2_addressing {
1035 u8 num_banks;
1036 u8 t_REFI_us_x10;
1037 u8 row_sz[2]; /* One entry each for x32 and x16 */
1038 u8 col_sz[2]; /* One entry each for x32 and x16 */
1039};
1040
1041/* Structure for timings from the DDR datasheet */
1042struct lpddr2_ac_timings {
1043 u32 max_freq;
1044 u8 RL;
1045 u8 tRPab;
1046 u8 tRCD;
1047 u8 tWR;
1048 u8 tRASmin;
1049 u8 tRRD;
1050 u8 tWTRx2;
1051 u8 tXSR;
1052 u8 tXPx2;
1053 u8 tRFCab;
1054 u8 tRTPx2;
1055 u8 tCKE;
1056 u8 tCKESR;
1057 u8 tZQCS;
1058 u32 tZQCL;
1059 u32 tZQINIT;
1060 u8 tDQSCKMAXx2;
1061 u8 tRASmax;
1062 u8 tFAW;
1063
1064};
1065
1066/*
1067 * Min tCK values for some of the parameters:
1068 * If the calculated clock cycles for the respective parameter is
1069 * less than the corresponding min tCK value, we need to set the min
1070 * tCK value. This may happen at lower frequencies.
1071 */
1072struct lpddr2_min_tck {
1073 u32 tRL;
1074 u32 tRP_AB;
1075 u32 tRCD;
1076 u32 tWR;
1077 u32 tRAS_MIN;
1078 u32 tRRD;
1079 u32 tWTR;
1080 u32 tXP;
1081 u32 tRTP;
1082 u8 tCKE;
1083 u32 tCKESR;
1084 u32 tFAW;
1085};
1086
1087struct lpddr2_device_details {
1088 u8 type;
1089 u8 density;
1090 u8 io_width;
1091 u8 manufacturer;
1092};
1093
1094struct lpddr2_device_timings {
1095 const struct lpddr2_ac_timings **ac_timings;
1096 const struct lpddr2_min_tck *min_tck;
1097};
1098
1099/* Details of the devices connected to each chip-select of an EMIF instance */
1100struct emif_device_details {
1101 const struct lpddr2_device_details *cs0_device_details;
1102 const struct lpddr2_device_details *cs1_device_details;
1103 const struct lpddr2_device_timings *cs0_device_timings;
1104 const struct lpddr2_device_timings *cs1_device_timings;
1105};
1106
1107/*
1108 * Structure containing shadow of important registers in EMIF
1109 * The calculation function fills in this structure to be later used for
1110 * initialization and DVFS
1111 */
1112struct emif_regs {
1113 u32 freq;
1114 u32 sdram_config_init;
1115 u32 sdram_config;
1116 u32 ref_ctrl;
1117 u32 sdram_tim1;
1118 u32 sdram_tim2;
1119 u32 sdram_tim3;
1120 u32 read_idle_ctrl;
1121 u32 zq_config;
1122 u32 temp_alert_config;
1123 u32 emif_ddr_phy_ctlr_1_init;
1124 u32 emif_ddr_phy_ctlr_1;
SRICHARAN Rf4010732012-03-12 02:25:37 +00001125 u32 emif_ddr_ext_phy_ctrl_1;
1126 u32 emif_ddr_ext_phy_ctrl_2;
1127 u32 emif_ddr_ext_phy_ctrl_3;
1128 u32 emif_ddr_ext_phy_ctrl_4;
1129 u32 emif_ddr_ext_phy_ctrl_5;
Lokesh Vutla43037d72012-05-22 00:03:24 +00001130 u32 emif_rd_wr_lvl_rmp_win;
1131 u32 emif_rd_wr_lvl_rmp_ctl;
1132 u32 emif_rd_wr_lvl_ctl;
1133 u32 emif_rd_wr_exec_thresh;
Sricharanbb772a52011-11-15 09:50:00 -05001134};
1135
Lokesh Vutlae05a4f12013-02-04 04:22:03 +00001136struct lpddr2_mr_regs {
1137 s8 mr1;
1138 s8 mr2;
1139 s8 mr3;
1140 s8 mr10;
1141 s8 mr16;
1142};
1143
Sricharanbb772a52011-11-15 09:50:00 -05001144/* assert macros */
1145#if defined(DEBUG)
1146#define emif_assert(c) ({ if (!(c)) for (;;); })
1147#else
1148#define emif_assert(c) ({ if (0) hang(); })
1149#endif
1150
1151#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1152void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
1153void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
1154#else
1155struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1156 struct lpddr2_device_details *lpddr2_dev_details);
1157void emif_get_device_timings(u32 emif_nr,
1158 const struct lpddr2_device_timings **cs0_device_timings,
1159 const struct lpddr2_device_timings **cs1_device_timings);
1160#endif
1161
SRICHARAN R25476382012-06-04 03:40:23 +00001162void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
Lokesh Vutlae05a4f12013-02-04 04:22:03 +00001163void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
SRICHARAN R25476382012-06-04 03:40:23 +00001164
Sricharanbb772a52011-11-15 09:50:00 -05001165#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1166extern u32 *const T_num;
1167extern u32 *const T_den;
Sricharanbb772a52011-11-15 09:50:00 -05001168#endif
1169
Lokesh Vutla784ab7c2012-05-22 00:03:25 +00001170void config_data_eye_leveling_samples(u32 emif_base);
Lokesh Vutla9ca8bfe2013-02-04 04:21:59 +00001171u32 emif_sdram_type(void);
Sricharanbb772a52011-11-15 09:50:00 -05001172#endif