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gerrit.cesnet.cz / github / trini / u-boot / 8b7776b9f95d542d0e81357c4f8aa32f7bf466e5 / . / arch / arm / cpu / tegra30-common / pinmux.c
blob: 122665fd3c69c280896df4893e28024caa774349 [file] [log] [blame]
Tom Warrenb2871032012-12-11 13:34:15 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra30 pin multiplexing functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/tegra.h>
22#include <asm/arch/pinmux.h>
23
24struct tegra_pingroup_desc {
25 const char *name;
26 enum pmux_func funcs[4];
27 enum pmux_func func_safe;
28 enum pmux_vddio vddio;
29 enum pmux_pin_io io;
30};
31
32#define PMUX_MUXCTL_SHIFT 0
33#define PMUX_PULL_SHIFT 2
34#define PMUX_TRISTATE_SHIFT 4
35#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
36#define PMUX_IO_SHIFT 5
37#define PMUX_OD_SHIFT 6
38#define PMUX_LOCK_SHIFT 7
39#define PMUX_IO_RESET_SHIFT 8
40
41/* Convenient macro for defining pin group properties */
42#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
43 { \
44 .vddio = PMUX_VDDIO_ ## vdd, \
45 .funcs = { \
46 PMUX_FUNC_ ## f0, \
47 PMUX_FUNC_ ## f1, \
48 PMUX_FUNC_ ## f2, \
49 PMUX_FUNC_ ## f3, \
50 }, \
51 .func_safe = PMUX_FUNC_RSVD1, \
52 .io = PMUX_PIN_ ## iod, \
53 }
54
55/* Input and output pins */
56#define PINI(pg_name, vdd, f0, f1, f2, f3) \
57 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
58#define PINO(pg_name, vdd, f0, f1, f2, f3) \
59 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
60
61const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
62 /* NAME VDD f0 f1 f2 f3 */
63 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
64 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
65 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
66 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
67 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
68 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
69 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
70 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
71 PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
72 PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
73 PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
74 PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
75 PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
76 PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
77 PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
78 PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
79 PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
80 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
81 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
82 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
83 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
84 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
85 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
86 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
87 PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
88 PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
89 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
90 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
91 PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
92 PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
93 PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
94 PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
95 PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
96 PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
97 PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
98 PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
99 PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
100 PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
101 PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
102 PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
103 PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
104 PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
105 PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
106 PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
107 PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
108 PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
109 PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
110 PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
111 PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
112 PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
113 PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
114 PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
115 PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
116 PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
117 PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
118 PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
119 PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
120 PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
121 PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
122 PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
123 PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
124 PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
125 PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
126 PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
127 PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
128 PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
129 PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
130 PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
131 PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
132 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
133 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
134 PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
135 PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
136 PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
137 PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
138 PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
139 PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
140 PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
141 PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
142 PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
143 PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
144 PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
145 PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
146 PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
147 PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
148 PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
149 PINI(VI_MCLK, VI, VI, VI, VI, VI),
150 PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
151 PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
152 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
153 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
154 PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
155 PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
156 PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
157 PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
158 PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
159 PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
160 PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
161 PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
162 PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
163 PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
164 PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
165 PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
166 PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
167 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
168 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
169 PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
170 PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
171 PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
172 PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
173 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
174 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
175 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
176 PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
177 PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
178 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
179 PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
180 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
181 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
182 PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
183 PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
184 PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
185 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
186 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
187 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
188 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
189 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
190 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
191 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
192 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
193 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
194 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
195 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
196 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
197 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
198 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
199 PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
200 PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
201 PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
202 PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
203 PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
204 PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
205 PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
206 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
207 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
208 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
209 PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
210 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
211 PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
212 PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
213 PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
214 PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
215 PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
216 PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
217 PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
218 PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
219 PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
220 PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
221 PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
222 PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
223 PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
224 PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
225 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
226 PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
227 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
228 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
229 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
230 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
231 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
232 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
233 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
234 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
235 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
236 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
237 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
238 PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
239 PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
240 PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
241 PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
242 PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
243 PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
244 PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
245 PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
246 PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
247 PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
248 PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
249 PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
250 PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
251 PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
252 PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
253 PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
254 PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
255 PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
256 PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
257 PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
258 PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
259 PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
260 PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
261 PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
262 PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
263 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
264 PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
265 PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
266 PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
267 PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
268 PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
269 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
270 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
271 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
272 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
273 PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
274 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
275 PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
276 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
277 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
278 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
279 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
280 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
281 PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
282 PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
283 PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
284 PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
285 PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
286 PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
287 PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
288 PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
289 PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
290 PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
291 PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
292 PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
293 PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
294 PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
295 PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
296 PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
297 PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
298 PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
299 PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
300 PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
301 PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
302 PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
303 PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
304 PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
305 PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
306 PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
307 PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
308 PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
309 PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
310 PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
311 PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
312};
313
314void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
315{
316 struct pmux_tri_ctlr *pmt =
317 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
318 u32 *tri = &pmt->pmt_ctl[pin];
319 u32 reg;
320
321 /* Error check on pin */
322 assert(pmux_pingrp_isvalid(pin));
323
324 reg = readl(tri);
325 if (enable)
326 reg |= PMUX_TRISTATE_MASK;
327 else
328 reg &= ~PMUX_TRISTATE_MASK;
329 writel(reg, tri);
330}
331
332void pinmux_tristate_enable(enum pmux_pingrp pin)
333{
334 pinmux_set_tristate(pin, 1);
335}
336
337void pinmux_tristate_disable(enum pmux_pingrp pin)
338{
339 pinmux_set_tristate(pin, 0);
340}
341
342void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
343{
344 struct pmux_tri_ctlr *pmt =
345 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
346 u32 *pull = &pmt->pmt_ctl[pin];
347 u32 reg;
348
349 /* Error check on pin and pupd */
350 assert(pmux_pingrp_isvalid(pin));
351 assert(pmux_pin_pupd_isvalid(pupd));
352
353 reg = readl(pull);
354 reg &= ~(0x3 << PMUX_PULL_SHIFT);
355 reg |= (pupd << PMUX_PULL_SHIFT);
356 writel(reg, pull);
357}
358
359void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
360{
361 struct pmux_tri_ctlr *pmt =
362 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
363 u32 *muxctl = &pmt->pmt_ctl[pin];
364 int i, mux = -1;
365 u32 reg;
366
367 /* Error check on pin and func */
368 assert(pmux_pingrp_isvalid(pin));
369 assert(pmux_func_isvalid(func));
370
371 /* Handle special values */
372 if (func == PMUX_FUNC_SAFE)
373 func = tegra_soc_pingroups[pin].func_safe;
374
375 if (func & PMUX_FUNC_RSVD1) {
376 mux = func & 0x3;
377 } else {
378 /* Search for the appropriate function */
379 for (i = 0; i < 4; i++) {
380 if (tegra_soc_pingroups[pin].funcs[i] == func) {
381 mux = i;
382 break;
383 }
384 }
385 }
386 assert(mux != -1);
387
388 reg = readl(muxctl);
389 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
390 reg |= (mux << PMUX_MUXCTL_SHIFT);
391 writel(reg, muxctl);
392
393}
394
395void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
396{
397 struct pmux_tri_ctlr *pmt =
398 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
399 u32 *pin_io = &pmt->pmt_ctl[pin];
400 u32 reg;
401
402 /* Error check on pin and io */
403 assert(pmux_pingrp_isvalid(pin));
404 assert(pmux_pin_io_isvalid(io));
405
406 reg = readl(pin_io);
407 reg &= ~(0x1 << PMUX_IO_SHIFT);
408 reg |= (io & 0x1) << PMUX_IO_SHIFT;
409 writel(reg, pin_io);
410}
411
412static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
413{
414 struct pmux_tri_ctlr *pmt =
415 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
416 u32 *pin_lock = &pmt->pmt_ctl[pin];
417 u32 reg;
418
419 /* Error check on pin and lock */
420 assert(pmux_pingrp_isvalid(pin));
421 assert(pmux_pin_lock_isvalid(lock));
422
423 if (lock == PMUX_PIN_LOCK_DEFAULT)
424 return 0;
425
426 reg = readl(pin_lock);
427 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
428 if (lock == PMUX_PIN_LOCK_ENABLE)
429 reg |= (0x1 << PMUX_LOCK_SHIFT);
430 else {
431 /* lock == DISABLE, which isn't possible */
432 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
433 __func__, lock);
434 }
435 writel(reg, pin_lock);
436
437 return 0;
438}
439
440static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
441{
442 struct pmux_tri_ctlr *pmt =
443 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
444 u32 *pin_od = &pmt->pmt_ctl[pin];
445 u32 reg;
446
447 /* Error check on pin and od */
448 assert(pmux_pingrp_isvalid(pin));
449 assert(pmux_pin_od_isvalid(od));
450
451 if (od == PMUX_PIN_OD_DEFAULT)
452 return 0;
453
454 reg = readl(pin_od);
455 reg &= ~(0x1 << PMUX_OD_SHIFT);
456 if (od == PMUX_PIN_OD_ENABLE)
457 reg |= (0x1 << PMUX_OD_SHIFT);
458 writel(reg, pin_od);
459
460 return 0;
461}
462
463static int pinmux_set_ioreset(enum pmux_pingrp pin,
464 enum pmux_pin_ioreset ioreset)
465{
466 struct pmux_tri_ctlr *pmt =
467 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
468 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
469 u32 reg;
470
471 /* Error check on pin and ioreset */
472 assert(pmux_pingrp_isvalid(pin));
473 assert(pmux_pin_ioreset_isvalid(ioreset));
474
475 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
476 return 0;
477
478 reg = readl(pin_ioreset);
479 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
480 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
481 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
482 writel(reg, pin_ioreset);
483
484 return 0;
485}
486
487void pinmux_config_pingroup(struct pingroup_config *config)
488{
489 enum pmux_pingrp pin = config->pingroup;
490
491 pinmux_set_func(pin, config->func);
492 pinmux_set_pullupdown(pin, config->pull);
493 pinmux_set_tristate(pin, config->tristate);
494 pinmux_set_io(pin, config->io);
495 pinmux_set_lock(pin, config->lock);
496 pinmux_set_od(pin, config->od);
497 pinmux_set_ioreset(pin, config->ioreset);
498}
499
500void pinmux_config_table(struct pingroup_config *config, int len)
501{
502 int i;
503
504 for (i = 0; i < len; i++)
505 pinmux_config_pingroup(&config[i]);
506}