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gerrit.cesnet.cz / github / trini / u-boot / 993cad9364c6b87ae429d1ed1130d8153f6f027e / . / board / dnp1110 / memsetup.S
blob: 6539c2082b281165b77ab2db56a6383ada7c0da8 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]28#include "config.h"
29#include "version.h"
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]30
31
32/* some parameters for the board */
33
34MEM_BASE: .long 0xa0000000
35MEM_START: .long 0xc0000000
36
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]37#define MDCNFG 0x00
38#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */
39#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */
40#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */
41#define MDREFR 0x1C /* DRAM refresh control reg */
42#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */
43#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */
44#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */
45#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */
46#define MSC0 0x10 /* static memory control reg 0 */
47#define MSC1 0x14 /* static memory control reg 1 */
48#define MSC2 0x2C /* static memory control reg 2 */
49#define SMCNFG 0x30 /* SMROM configuration reg */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]50
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]51mdcas00: .long 0x5555557F
52mdcas01: .long 0x55555555
53mdcas02: .long 0x55555555
54mdcas20: .long 0x5555557F
55mdcas21: .long 0x55555555
56mdcas22: .long 0x55555555
57mdcnfg: .long 0x0000B25C
58mdrefr: .long 0x007000C1
59mecr: .long 0x10841084
60msc0: .long 0x00004774
61msc1: .long 0x00000000
62msc2: .long 0x00000000
63smcnfg: .long 0x00000000
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]64
65/* setting up the memory */
66
67.globl memsetup
68memsetup:
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]69
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]70 ldr r0, MEM_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]71
72 /* Set up the DRAM */
73
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]74 /* MDCAS00 */
75 ldr r1, mdcas00
76 str r1, [r0, #MDCAS00]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]77
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]78 /* MDCAS01 */
79 ldr r1, mdcas01
80 str r1, [r0, #MDCAS01]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]81
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]82 /* MDCAS02 */
83 ldr r1, mdcas02
84 str r1, [r0, #MDCAS02]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]85
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]86 /* MDCAS20 */
87 ldr r1, mdcas20
88 str r1, [r0, #MDCAS20]
89
90 /* MDCAS21 */
91 ldr r1, mdcas21
92 str r1, [r0, #MDCAS21]
93
94 /* MDCAS22 */
95 ldr r1, mdcas22
96 str r1, [r0, #MDCAS22]
97
98 /* MDREFR */
99 ldr r1, mdrefr
100 str r1, [r0, #MDREFR]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]101
102 /* Set up PCMCIA space */
103 ldr r1, mecr
104 str r1, [r0, #MECR]
105
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]106 /* Setup the flash memory and other */
107 ldr r1, msc0
108 str r1, [r0, #MSC0]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]109
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]110 ldr r1, msc1
111 str r1, [r0, #MSC1]
112
113 ldr r1, msc2
114 str r1, [r0, #MSC2]
115
116 ldr r1, smcnfg
117 str r1, [r0, #SMCNFG]
118
119 /* MDCNFG */
120 ldr r1, mdcnfg
121 bic r1, r1, #0x00000001
122 str r1, [r0, #MDCNFG]
123
124 /* Load something to activate bank */
125 ldr r2, MEM_START
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]126.rept 8
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]127 ldr r1, [r2]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]128.endr
129
wdenkdc7c9a12003-03-26 06:55:25 +0000[diff] [blame]130 /* MDCNFG */
131 ldr r1, mdcnfg
132 orr r1, r1, #0x00000001
133 str r1, [r0, #MDCNFG]
134
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]135 /* everything is fine now */
136 mov pc, lr