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Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +00001/*
2 * Bluegiga APX4 Development Kit
3 *
4 * Copyright (C) 2012 Bluegiga Technologies Oy
5 *
6 * Authors:
7 * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
8 * Lauri Hintsala <lauri.hintsala@bluegiga.com>
9 *
10 * Based on m28evk.c:
11 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
12 * on behalf of DENX Software Engineering GmbH
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000015 */
16
17#include <common.h>
18#include <asm/gpio.h>
19#include <asm/io.h>
Simon Glass5d982852017-05-17 08:23:00 -060020#include <asm/setup.h>
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000021#include <asm/arch/imx-regs.h>
22#include <asm/arch/iomux-mx28.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/sys_proto.h>
25#include <linux/mii.h>
26#include <miiphy.h>
27#include <netdev.h>
28#include <errno.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32/* Functions */
33int board_early_init_f(void)
34{
35 /* IO0 clock at 480MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000036 mxs_set_ioclk(MXC_IOCLK0, 480000);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000037 /* IO1 clock at 480MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000038 mxs_set_ioclk(MXC_IOCLK1, 480000);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000039
40 /* SSP0 clock at 96MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000041 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000042
43 return 0;
44}
45
46int dram_init(void)
47{
Otavio Salvador72f8ebf2012-08-19 04:58:30 +000048 return mxs_dram_init();
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000049}
50
51int board_init(void)
52{
53 /* Adress of boot parameters */
54 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
55
56 return 0;
57}
58
59#ifdef CONFIG_CMD_MMC
60int board_mmc_init(bd_t *bis)
61{
Marek Vasut90bc2bf2013-01-22 15:01:03 +000062 return mxsmmc_initialize(bis, 0, NULL, NULL);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000063}
64#endif
65
66
67#ifdef CONFIG_CMD_NET
68
69#define MII_PHY_CTRL2 0x1f
70int fecmxc_mii_postcall(int phy)
71{
72 /* change PHY RMII clock to 50MHz */
73 miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
74
75 return 0;
76}
77
78int board_eth_init(bd_t *bis)
79{
80 int ret;
81 struct eth_device *dev;
82
83 ret = cpu_eth_init(bis);
84 if (ret) {
85 printf("FEC MXS: Unable to init FEC clocks\n");
86 return ret;
87 }
88
89 ret = fecmxc_initialize(bis);
90 if (ret) {
91 printf("FEC MXS: Unable to init FEC\n");
92 return ret;
93 }
94
95 dev = eth_get_dev_by_name("FEC");
96 if (!dev) {
97 printf("FEC MXS: Unable to get FEC device entry\n");
98 return -EINVAL;
99 }
100
101 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
102 if (ret) {
103 printf("FEC MXS: Unable to register FEC MII postcall\n");
104 return ret;
105 }
106
107 return ret;
108}
109#endif
110
111#ifdef CONFIG_SERIAL_TAG
112#define MXS_OCOTP_MAX_TIMEOUT 1000000
113void get_board_serial(struct tag_serialnr *serialnr)
114{
Otavio Salvador9c471142012-08-05 09:05:31 +0000115 struct mxs_ocotp_regs *ocotp_regs =
116 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000117
118 serialnr->high = 0;
119 serialnr->low = 0;
120
121 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
122
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000123 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000124 MXS_OCOTP_MAX_TIMEOUT)) {
125 printf("MXS: Can't get serial number from OCOTP\n");
126 return;
127 }
128
129 serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
130}
131#endif
132
133#ifdef CONFIG_REVISION_TAG
134u32 get_board_rev(void)
135{
Simon Glass00caae62017-08-03 12:22:12 -0600136 if (env_get("revision#") != NULL)
137 return simple_strtoul(env_get("revision#"), NULL, 10);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000138 return 0;
139}
140#endif