blob: f3179bcf1e2e75ba5d66570a8cfeb1749c7268bd [file] [log] [blame]
Rene Griessle9954b82014-11-07 16:53:48 +01001/*
2 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
3 * based on the U-Boot Asix driver as well as information
4 * from the Linux AX88179_178a driver
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <usb.h>
11#include <net.h>
12#include <linux/mii.h>
13#include "usb_ether.h"
14#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060015#include <memalign.h>
Rene Griessle9954b82014-11-07 16:53:48 +010016#include <errno.h>
17
18/* ASIX AX88179 based USB 3.0 Ethernet Devices */
19#define AX88179_PHY_ID 0x03
20#define AX_EEPROM_LEN 0x100
21#define AX88179_EEPROM_MAGIC 0x17900b95
22#define AX_MCAST_FLTSIZE 8
23#define AX_MAX_MCAST 64
24#define AX_INT_PPLS_LINK (1 << 16)
25#define AX_RXHDR_L4_TYPE_MASK 0x1c
26#define AX_RXHDR_L4_TYPE_UDP 4
27#define AX_RXHDR_L4_TYPE_TCP 16
28#define AX_RXHDR_L3CSUM_ERR 2
29#define AX_RXHDR_L4CSUM_ERR 1
30#define AX_RXHDR_CRC_ERR (1 << 29)
31#define AX_RXHDR_DROP_ERR (1 << 31)
32#define AX_ENDPOINT_INT 0x01
33#define AX_ENDPOINT_IN 0x02
34#define AX_ENDPOINT_OUT 0x03
35#define AX_ACCESS_MAC 0x01
36#define AX_ACCESS_PHY 0x02
37#define AX_ACCESS_EEPROM 0x04
38#define AX_ACCESS_EFUS 0x05
39#define AX_PAUSE_WATERLVL_HIGH 0x54
40#define AX_PAUSE_WATERLVL_LOW 0x55
41
42#define PHYSICAL_LINK_STATUS 0x02
43 #define AX_USB_SS (1 << 2)
44 #define AX_USB_HS (1 << 1)
45
46#define GENERAL_STATUS 0x03
47 #define AX_SECLD (1 << 2)
48
49#define AX_SROM_ADDR 0x07
50#define AX_SROM_CMD 0x0a
51 #define EEP_RD (1 << 2)
52 #define EEP_BUSY (1 << 4)
53
54#define AX_SROM_DATA_LOW 0x08
55#define AX_SROM_DATA_HIGH 0x09
56
57#define AX_RX_CTL 0x0b
58 #define AX_RX_CTL_DROPCRCERR (1 << 8)
59 #define AX_RX_CTL_IPE (1 << 9)
60 #define AX_RX_CTL_START (1 << 7)
61 #define AX_RX_CTL_AP (1 << 5)
62 #define AX_RX_CTL_AM (1 << 4)
63 #define AX_RX_CTL_AB (1 << 3)
64 #define AX_RX_CTL_AMALL (1 << 1)
65 #define AX_RX_CTL_PRO (1 << 0)
66 #define AX_RX_CTL_STOP 0
67
68#define AX_NODE_ID 0x10
69#define AX_MULFLTARY 0x16
70
71#define AX_MEDIUM_STATUS_MODE 0x22
72 #define AX_MEDIUM_GIGAMODE (1 << 0)
73 #define AX_MEDIUM_FULL_DUPLEX (1 << 1)
74 #define AX_MEDIUM_EN_125MHZ (1 << 3)
75 #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
76 #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
77 #define AX_MEDIUM_RECEIVE_EN (1 << 8)
78 #define AX_MEDIUM_PS (1 << 9)
79 #define AX_MEDIUM_JUMBO_EN 0x8040
80
81#define AX_MONITOR_MOD 0x24
82 #define AX_MONITOR_MODE_RWLC (1 << 1)
83 #define AX_MONITOR_MODE_RWMP (1 << 2)
84 #define AX_MONITOR_MODE_PMEPOL (1 << 5)
85 #define AX_MONITOR_MODE_PMETYPE (1 << 6)
86
87#define AX_GPIO_CTRL 0x25
88 #define AX_GPIO_CTRL_GPIO3EN (1 << 7)
89 #define AX_GPIO_CTRL_GPIO2EN (1 << 6)
90 #define AX_GPIO_CTRL_GPIO1EN (1 << 5)
91
92#define AX_PHYPWR_RSTCTL 0x26
93 #define AX_PHYPWR_RSTCTL_BZ (1 << 4)
94 #define AX_PHYPWR_RSTCTL_IPRL (1 << 5)
95 #define AX_PHYPWR_RSTCTL_AT (1 << 12)
96
97#define AX_RX_BULKIN_QCTRL 0x2e
98#define AX_CLK_SELECT 0x33
99 #define AX_CLK_SELECT_BCS (1 << 0)
100 #define AX_CLK_SELECT_ACS (1 << 1)
101 #define AX_CLK_SELECT_ULR (1 << 3)
102
103#define AX_RXCOE_CTL 0x34
104 #define AX_RXCOE_IP (1 << 0)
105 #define AX_RXCOE_TCP (1 << 1)
106 #define AX_RXCOE_UDP (1 << 2)
107 #define AX_RXCOE_TCPV6 (1 << 5)
108 #define AX_RXCOE_UDPV6 (1 << 6)
109
110#define AX_TXCOE_CTL 0x35
111 #define AX_TXCOE_IP (1 << 0)
112 #define AX_TXCOE_TCP (1 << 1)
113 #define AX_TXCOE_UDP (1 << 2)
114 #define AX_TXCOE_TCPV6 (1 << 5)
115 #define AX_TXCOE_UDPV6 (1 << 6)
116
117#define AX_LEDCTRL 0x73
118
119#define GMII_PHY_PHYSR 0x11
120 #define GMII_PHY_PHYSR_SMASK 0xc000
121 #define GMII_PHY_PHYSR_GIGA (1 << 15)
122 #define GMII_PHY_PHYSR_100 (1 << 14)
123 #define GMII_PHY_PHYSR_FULL (1 << 13)
124 #define GMII_PHY_PHYSR_LINK (1 << 10)
125
126#define GMII_LED_ACT 0x1a
127 #define GMII_LED_ACTIVE_MASK 0xff8f
128 #define GMII_LED0_ACTIVE (1 << 4)
129 #define GMII_LED1_ACTIVE (1 << 5)
130 #define GMII_LED2_ACTIVE (1 << 6)
131
132#define GMII_LED_LINK 0x1c
133 #define GMII_LED_LINK_MASK 0xf888
134 #define GMII_LED0_LINK_10 (1 << 0)
135 #define GMII_LED0_LINK_100 (1 << 1)
136 #define GMII_LED0_LINK_1000 (1 << 2)
137 #define GMII_LED1_LINK_10 (1 << 4)
138 #define GMII_LED1_LINK_100 (1 << 5)
139 #define GMII_LED1_LINK_1000 (1 << 6)
140 #define GMII_LED2_LINK_10 (1 << 8)
141 #define GMII_LED2_LINK_100 (1 << 9)
142 #define GMII_LED2_LINK_1000 (1 << 10)
143 #define LED0_ACTIVE (1 << 0)
144 #define LED0_LINK_10 (1 << 1)
145 #define LED0_LINK_100 (1 << 2)
146 #define LED0_LINK_1000 (1 << 3)
147 #define LED0_FD (1 << 4)
148 #define LED0_USB3_MASK 0x001f
149 #define LED1_ACTIVE (1 << 5)
150 #define LED1_LINK_10 (1 << 6)
151 #define LED1_LINK_100 (1 << 7)
152 #define LED1_LINK_1000 (1 << 8)
153 #define LED1_FD (1 << 9)
154 #define LED1_USB3_MASK 0x03e0
155 #define LED2_ACTIVE (1 << 10)
156 #define LED2_LINK_1000 (1 << 13)
157 #define LED2_LINK_100 (1 << 12)
158 #define LED2_LINK_10 (1 << 11)
159 #define LED2_FD (1 << 14)
160 #define LED_VALID (1 << 15)
161 #define LED2_USB3_MASK 0x7c00
162
163#define GMII_PHYPAGE 0x1e
164#define GMII_PHY_PAGE_SELECT 0x1f
165 #define GMII_PHY_PGSEL_EXT 0x0007
166 #define GMII_PHY_PGSEL_PAGE0 0x0000
167
168/* local defines */
169#define ASIX_BASE_NAME "axg"
170#define USB_CTRL_SET_TIMEOUT 5000
171#define USB_CTRL_GET_TIMEOUT 5000
172#define USB_BULK_SEND_TIMEOUT 5000
173#define USB_BULK_RECV_TIMEOUT 5000
174
175#define AX_RX_URB_SIZE 1024 * 0x12
176#define BLK_FRAME_SIZE 0x200
177#define PHY_CONNECT_TIMEOUT 5000
178
179#define TIMEOUT_RESOLUTION 50 /* ms */
180
181#define FLAG_NONE 0
182#define FLAG_TYPE_AX88179 (1U << 0)
183#define FLAG_TYPE_AX88178a (1U << 1)
184#define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
185#define FLAG_TYPE_SITECOM (1U << 3)
186#define FLAG_TYPE_SAMSUNG (1U << 4)
187#define FLAG_TYPE_LENOVO (1U << 5)
Alban Bedel652b2692016-08-03 08:14:40 +0200188#define FLAG_TYPE_GX3 (1U << 6)
Rene Griessle9954b82014-11-07 16:53:48 +0100189
190/* local vars */
191static const struct {
192 unsigned char ctrl, timer_l, timer_h, size, ifg;
193} AX88179_BULKIN_SIZE[] = {
194 {7, 0x4f, 0, 0x02, 0xff},
195 {7, 0x20, 3, 0x03, 0xff},
196 {7, 0xae, 7, 0x04, 0xff},
197 {7, 0xcc, 0x4c, 0x04, 8},
198};
199
200static int curr_eth_dev; /* index for name of next device detected */
201
202/* driver private */
203struct asix_private {
204 int flags;
205 int rx_urb_size;
206 int maxpacketsize;
207};
208
209/*
210 * Asix infrastructure commands
211 */
212static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
213 u16 size, void *data)
214{
215 int len;
216 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
217
218 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
219 cmd, value, index, size);
220
221 memcpy(buf, data, size);
222
223 len = usb_control_msg(
224 dev->pusb_dev,
225 usb_sndctrlpipe(dev->pusb_dev, 0),
226 cmd,
227 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
228 value,
229 index,
230 buf,
231 size,
232 USB_CTRL_SET_TIMEOUT);
233
234 return len == size ? 0 : ECOMM;
235}
236
237static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
238 u16 size, void *data)
239{
240 int len;
241 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
242
243 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
244 cmd, value, index, size);
245
246 len = usb_control_msg(
247 dev->pusb_dev,
248 usb_rcvctrlpipe(dev->pusb_dev, 0),
249 cmd,
250 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
251 value,
252 index,
253 buf,
254 size,
255 USB_CTRL_GET_TIMEOUT);
256
257 memcpy(data, buf, size);
258
259 return len == size ? 0 : ECOMM;
260}
261
Alban Bedel620452e2016-08-09 11:10:02 +0200262static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
Rene Griessle9954b82014-11-07 16:53:48 +0100263{
Alban Bedel620452e2016-08-09 11:10:02 +0200264 int ret;
Rene Griessle9954b82014-11-07 16:53:48 +0100265
Alban Bedel620452e2016-08-09 11:10:02 +0200266 ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
267 if (ret < 0)
268 debug("Failed to read MAC address: %02x\n", ret);
Rene Griessle9954b82014-11-07 16:53:48 +0100269
Alban Bedel620452e2016-08-09 11:10:02 +0200270 return ret;
Rene Griessle9954b82014-11-07 16:53:48 +0100271}
272
Alban Bedel620452e2016-08-09 11:10:02 +0200273static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
Rene Griessl11933972015-01-12 17:51:16 +0100274{
Rene Griessl11933972015-01-12 17:51:16 +0100275 int ret;
276
277 ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
Alban Bedel620452e2016-08-09 11:10:02 +0200278 ETH_ALEN, enetaddr);
Rene Griessl11933972015-01-12 17:51:16 +0100279 if (ret < 0)
280 debug("Failed to set MAC address: %02x\n", ret);
281
282 return ret;
283}
284
Alban Bedel620452e2016-08-09 11:10:02 +0200285static int asix_basic_reset(struct ueth_data *dev,
286 struct asix_private *dev_priv)
Rene Griessle9954b82014-11-07 16:53:48 +0100287{
Rene Griessle9954b82014-11-07 16:53:48 +0100288 u8 buf[5];
289 u16 *tmp16;
290 u8 *tmp;
291
292 tmp16 = (u16 *)buf;
293 tmp = (u8 *)buf;
294
295 /* Power up ethernet PHY */
296 *tmp16 = 0;
297 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
298
299 *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
300 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
301 mdelay(200);
302
303 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
304 asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
305 mdelay(200);
306
307 /* RX bulk configuration */
308 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
309 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
310
311 dev_priv->rx_urb_size = 128 * 20;
312
313 /* Water Level configuration */
314 *tmp = 0x34;
315 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
316
317 *tmp = 0x52;
318 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
319
320 /* Enable checksum offload */
321 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
322 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
323 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
324
325 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
326 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
327 asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
328
329 /* Configure RX control register => start operation */
330 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
331 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
332 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
333
334 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
335 AX_MONITOR_MODE_RWMP;
336 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
337
338 /* Configure default medium type => giga */
339 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
340 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
341 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
342 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
343
344 u16 adv = 0;
345 adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
346 ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
347 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
348
349 adv = ADVERTISE_1000FULL;
350 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
351
352 return 0;
353}
354
355static int asix_wait_link(struct ueth_data *dev)
356{
357 int timeout = 0;
358 int link_detected;
359 u8 buf[2];
360 u16 *tmp16;
361
362 tmp16 = (u16 *)buf;
363
364 do {
365 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
366 MII_BMSR, 2, buf);
367 link_detected = *tmp16 & BMSR_LSTATUS;
368 if (!link_detected) {
369 if (timeout == 0)
370 printf("Waiting for Ethernet connection... ");
371 mdelay(TIMEOUT_RESOLUTION);
372 timeout += TIMEOUT_RESOLUTION;
373 }
374 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
375
376 if (link_detected) {
377 if (timeout > 0)
378 printf("done.\n");
379 return 0;
380 } else {
381 printf("unable to connect.\n");
382 return -ENETUNREACH;
383 }
384}
385
Alban Bedel620452e2016-08-09 11:10:02 +0200386static int asix_init_common(struct ueth_data *dev,
387 struct asix_private *dev_priv)
Rene Griessle9954b82014-11-07 16:53:48 +0100388{
Rene Griessle9954b82014-11-07 16:53:48 +0100389 u8 buf[2], tmp[5], link_sts;
390 u16 *tmp16, mode;
391
392
393 tmp16 = (u16 *)buf;
394
395 debug("** %s()\n", __func__);
396
397 /* Configure RX control register => start operation */
398 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
399 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
400 if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
401 goto out_err;
402
403 if (asix_wait_link(dev) != 0) {
404 /*reset device and try again*/
405 printf("Reset Ethernet Device\n");
Alban Bedel620452e2016-08-09 11:10:02 +0200406 asix_basic_reset(dev, dev_priv);
Rene Griessle9954b82014-11-07 16:53:48 +0100407 if (asix_wait_link(dev) != 0)
408 goto out_err;
409 }
410
411 /* Configure link */
412 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
413 AX_MEDIUM_RXFLOW_CTRLEN;
414
415 asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
416 1, 1, &link_sts);
417
418 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
419 GMII_PHY_PHYSR, 2, tmp16);
420
421 if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
422 return 0;
423 } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
424 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
425 AX_MEDIUM_JUMBO_EN;
426
427 if (link_sts & AX_USB_SS)
428 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
429 else if (link_sts & AX_USB_HS)
430 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
431 else
432 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
433 } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
434 mode |= AX_MEDIUM_PS;
435
436 if (link_sts & (AX_USB_SS | AX_USB_HS))
437 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
438 else
439 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
440 } else {
441 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
442 }
443
444 /* RX bulk configuration */
445 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
446
447 dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
448 if (*tmp16 & GMII_PHY_PHYSR_FULL)
449 mode |= AX_MEDIUM_FULL_DUPLEX;
450 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
451 2, 2, &mode);
452
453 return 0;
454out_err:
455 return -1;
456}
457
Alban Bedel620452e2016-08-09 11:10:02 +0200458static int asix_send_common(struct ueth_data *dev,
459 struct asix_private *dev_priv,
460 void *packet, int length)
Rene Griessle9954b82014-11-07 16:53:48 +0100461{
Rene Griessle9954b82014-11-07 16:53:48 +0100462 int err;
463 u32 packet_len, tx_hdr2;
464 int actual_len, framesize;
465 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
466 PKTSIZE + (2 * sizeof(packet_len)));
467
468 debug("** %s(), len %d\n", __func__, length);
469
470 packet_len = length;
471 cpu_to_le32s(&packet_len);
472
473 memcpy(msg, &packet_len, sizeof(packet_len));
474 framesize = dev_priv->maxpacketsize;
475 tx_hdr2 = 0;
476 if (((length + 8) % framesize) == 0)
477 tx_hdr2 |= 0x80008000; /* Enable padding */
478
479 cpu_to_le32s(&tx_hdr2);
480
481 memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
482
483 memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
484 (void *)packet, length);
485
486 err = usb_bulk_msg(dev->pusb_dev,
487 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
488 (void *)msg,
489 length + sizeof(packet_len) + sizeof(tx_hdr2),
490 &actual_len,
491 USB_BULK_SEND_TIMEOUT);
Mateusz Kulikowski64160a52016-03-31 23:12:22 +0200492 debug("Tx: len = %zu, actual = %u, err = %d\n",
Rene Griessle9954b82014-11-07 16:53:48 +0100493 length + sizeof(packet_len), actual_len, err);
494
495 return err;
496}
497
Alban Bedel620452e2016-08-09 11:10:02 +0200498/*
499 * Asix callbacks
500 */
501static int asix_init(struct eth_device *eth, bd_t *bd)
502{
503 struct ueth_data *dev = (struct ueth_data *)eth->priv;
504 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
505
506 return asix_init_common(dev, dev_priv);
507}
508
509static int asix_write_hwaddr(struct eth_device *eth)
510{
511 struct ueth_data *dev = (struct ueth_data *)eth->priv;
512
513 return asix_write_mac(dev, eth->enetaddr);
514}
515
516static int asix_send(struct eth_device *eth, void *packet, int length)
517{
518 struct ueth_data *dev = (struct ueth_data *)eth->priv;
519 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
520
521 return asix_send_common(dev, dev_priv, packet, length);
522}
523
Rene Griessle9954b82014-11-07 16:53:48 +0100524static int asix_recv(struct eth_device *eth)
525{
526 struct ueth_data *dev = (struct ueth_data *)eth->priv;
527 struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
528
529 u16 frame_pos;
530 int err;
531 int actual_len;
532
533 int pkt_cnt;
534 u32 rx_hdr;
535 u16 hdr_off;
536 u32 *pkt_hdr;
537 ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
538
539 actual_len = -1;
540
541 debug("** %s()\n", __func__);
542
543 err = usb_bulk_msg(dev->pusb_dev,
544 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
545 (void *)recv_buf,
546 dev_priv->rx_urb_size,
547 &actual_len,
548 USB_BULK_RECV_TIMEOUT);
549 debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
550 actual_len, err);
551
552 if (err != 0) {
553 debug("Rx: failed to receive\n");
554 return -ECOMM;
555 }
556 if (actual_len > dev_priv->rx_urb_size) {
557 debug("Rx: received too many bytes %d\n", actual_len);
558 return -EMSGSIZE;
559 }
560
561
562 rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
Alban Bedel50f5bb22016-08-03 08:14:41 +0200563 le32_to_cpus(&rx_hdr);
Rene Griessle9954b82014-11-07 16:53:48 +0100564
565 pkt_cnt = (u16)rx_hdr;
566 hdr_off = (u16)(rx_hdr >> 16);
567 pkt_hdr = (u32 *)(recv_buf + hdr_off);
568
569
570 frame_pos = 0;
571
572 while (pkt_cnt--) {
573 u16 pkt_len;
574
575 le32_to_cpus(pkt_hdr);
576 pkt_len = (*pkt_hdr >> 16) & 0x1fff;
577
578 frame_pos += 2;
579
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500580 net_process_received_packet(recv_buf + frame_pos, pkt_len);
Rene Griessle9954b82014-11-07 16:53:48 +0100581
582 pkt_hdr++;
583 frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
584
585 if (pkt_cnt == 0)
586 return 0;
587 }
588 return err;
589}
590
591static void asix_halt(struct eth_device *eth)
592{
593 debug("** %s()\n", __func__);
594}
595
596/*
597 * Asix probing functions
598 */
599void ax88179_eth_before_probe(void)
600{
601 curr_eth_dev = 0;
602}
603
604struct asix_dongle {
605 unsigned short vendor;
606 unsigned short product;
607 int flags;
608};
609
610static const struct asix_dongle asix_dongles[] = {
611 { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
612 { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
613 { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
614 { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
615 { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
616 { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
Alban Bedel652b2692016-08-03 08:14:40 +0200617 { 0x04b4, 0x3610, FLAG_TYPE_GX3 },
Rene Griessle9954b82014-11-07 16:53:48 +0100618 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
619};
620
621/* Probe to see if a new device is actually an asix device */
622int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
623 struct ueth_data *ss)
624{
625 struct usb_interface *iface;
626 struct usb_interface_descriptor *iface_desc;
627 struct asix_private *dev_priv;
628 int ep_in_found = 0, ep_out_found = 0;
629 int i;
630
631 /* let's examine the device now */
632 iface = &dev->config.if_desc[ifnum];
633 iface_desc = &dev->config.if_desc[ifnum].desc;
634
635 for (i = 0; asix_dongles[i].vendor != 0; i++) {
636 if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
637 dev->descriptor.idProduct == asix_dongles[i].product)
638 /* Found a supported dongle */
639 break;
640 }
641
642 if (asix_dongles[i].vendor == 0)
643 return 0;
644
645 memset(ss, 0, sizeof(struct ueth_data));
646
647 /* At this point, we know we've got a live one */
648 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
649 dev->descriptor.idVendor, dev->descriptor.idProduct);
650
651 /* Initialize the ueth_data structure with some useful info */
652 ss->ifnum = ifnum;
653 ss->pusb_dev = dev;
654 ss->subclass = iface_desc->bInterfaceSubClass;
655 ss->protocol = iface_desc->bInterfaceProtocol;
656
657 /* alloc driver private */
658 ss->dev_priv = calloc(1, sizeof(struct asix_private));
659 if (!ss->dev_priv)
660 return 0;
661 dev_priv = ss->dev_priv;
662 dev_priv->flags = asix_dongles[i].flags;
663
664 /*
665 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
666 * int. We will ignore any others.
667 */
668 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
669 /* is it an interrupt endpoint? */
670 if ((iface->ep_desc[i].bmAttributes &
671 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
672 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
673 USB_ENDPOINT_NUMBER_MASK;
674 ss->irqinterval = iface->ep_desc[i].bInterval;
675 continue;
676 }
677
678 /* is it an BULK endpoint? */
679 if (!((iface->ep_desc[i].bmAttributes &
680 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
681 continue;
682
683 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
684 if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
685 ss->ep_in = ep_addr &
686 USB_ENDPOINT_NUMBER_MASK;
687 ep_in_found = 1;
688 }
689 if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
690 ss->ep_out = ep_addr &
691 USB_ENDPOINT_NUMBER_MASK;
692 dev_priv->maxpacketsize =
693 dev->epmaxpacketout[AX_ENDPOINT_OUT];
694 ep_out_found = 1;
695 }
696 }
697 debug("Endpoints In %d Out %d Int %d\n",
698 ss->ep_in, ss->ep_out, ss->ep_int);
699
700 /* Do some basic sanity checks, and bail if we find a problem */
701 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
702 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
703 debug("Problems with device\n");
704 return 0;
705 }
706 dev->privptr = (void *)ss;
707 return 1;
708}
709
710int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
711 struct eth_device *eth)
712{
Alban Bedel620452e2016-08-09 11:10:02 +0200713 struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
714
Rene Griessle9954b82014-11-07 16:53:48 +0100715 if (!eth) {
716 debug("%s: missing parameter.\n", __func__);
717 return 0;
718 }
719 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
720 eth->init = asix_init;
721 eth->send = asix_send;
722 eth->recv = asix_recv;
723 eth->halt = asix_halt;
Alban Bedel620452e2016-08-09 11:10:02 +0200724 eth->write_hwaddr = asix_write_hwaddr;
Rene Griessle9954b82014-11-07 16:53:48 +0100725 eth->priv = ss;
726
Alban Bedel620452e2016-08-09 11:10:02 +0200727 if (asix_basic_reset(ss, dev_priv))
Rene Griessle9954b82014-11-07 16:53:48 +0100728 return 0;
729
730 /* Get the MAC address */
Alban Bedel620452e2016-08-09 11:10:02 +0200731 if (asix_read_mac(ss, eth->enetaddr))
Rene Griessle9954b82014-11-07 16:53:48 +0100732 return 0;
733 debug("MAC %pM\n", eth->enetaddr);
734
735 return 1;
736}