blob: 1d18815b2b977afaacad18667e1578fdc8266234 [file] [log] [blame]
Dipen Dudhat52f90da2011-03-22 09:27:39 +05301/* Integrated Flash Controller NAND Machine Driver
2 *
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +05303 * Copyright (c) 2012 Freescale Semiconductor, Inc
Dipen Dudhat52f90da2011-03-22 09:27:39 +05304 *
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Dipen Dudhat52f90da2011-03-22 09:27:39 +05308 */
9
10#include <common.h>
11#include <malloc.h>
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +000012#include <nand.h>
Dipen Dudhat52f90da2011-03-22 09:27:39 +053013
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/mtd/nand_ecc.h>
17
18#include <asm/io.h>
19#include <asm/errno.h>
20#include <asm/fsl_ifc.h>
21
Prabhakar Kushwaha79da5e32012-09-12 22:26:05 +000022#define FSL_IFC_V1_1_0 0x01010000
Dipen Dudhat52f90da2011-03-22 09:27:39 +053023#define MAX_BANKS 4
24#define ERR_BYTE 0xFF /* Value returned for read bytes
25 when read failed */
26#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
27 NAND Machine */
28
29struct fsl_ifc_ctrl;
30
31/* mtd information per set */
32struct fsl_ifc_mtd {
Dipen Dudhat52f90da2011-03-22 09:27:39 +053033 struct nand_chip chip;
34 struct fsl_ifc_ctrl *ctrl;
35
36 struct device *dev;
37 int bank; /* Chip select bank number */
38 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
39 u8 __iomem *vbase; /* Chip select base virtual address */
40};
41
42/* overview of the fsl ifc controller */
43struct fsl_ifc_ctrl {
44 struct nand_hw_control controller;
45 struct fsl_ifc_mtd *chips[MAX_BANKS];
46
47 /* device info */
48 struct fsl_ifc *regs;
49 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
50 unsigned int cs_nand; /* On which chipsel NAND is connected */
51 unsigned int page; /* Last page written to / read from */
52 unsigned int read_bytes; /* Number of bytes read during command */
53 unsigned int column; /* Saved column from SEQIN */
54 unsigned int index; /* Pointer to next byte to 'read' */
55 unsigned int status; /* status read from NEESR after last op */
56 unsigned int oob; /* Non zero if operating on OOB data */
57 unsigned int eccread; /* Non zero for a full-page ECC read */
58};
59
60static struct fsl_ifc_ctrl *ifc_ctrl;
61
62/* 512-byte page with 4-bit ECC, 8-bit */
63static struct nand_ecclayout oob_512_8bit_ecc4 = {
64 .eccbytes = 8,
65 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
66 .oobfree = { {0, 5}, {6, 2} },
67};
68
69/* 512-byte page with 4-bit ECC, 16-bit */
70static struct nand_ecclayout oob_512_16bit_ecc4 = {
71 .eccbytes = 8,
72 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
73 .oobfree = { {2, 6}, },
74};
75
76/* 2048-byte page size with 4-bit ECC */
77static struct nand_ecclayout oob_2048_ecc4 = {
78 .eccbytes = 32,
79 .eccpos = {
80 8, 9, 10, 11, 12, 13, 14, 15,
81 16, 17, 18, 19, 20, 21, 22, 23,
82 24, 25, 26, 27, 28, 29, 30, 31,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 },
85 .oobfree = { {2, 6}, {40, 24} },
86};
87
88/* 4096-byte page size with 4-bit ECC */
89static struct nand_ecclayout oob_4096_ecc4 = {
90 .eccbytes = 64,
91 .eccpos = {
92 8, 9, 10, 11, 12, 13, 14, 15,
93 16, 17, 18, 19, 20, 21, 22, 23,
94 24, 25, 26, 27, 28, 29, 30, 31,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
100 },
101 .oobfree = { {2, 6}, {72, 56} },
102};
103
104/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
105static struct nand_ecclayout oob_4096_ecc8 = {
106 .eccbytes = 128,
107 .eccpos = {
108 8, 9, 10, 11, 12, 13, 14, 15,
109 16, 17, 18, 19, 20, 21, 22, 23,
110 24, 25, 26, 27, 28, 29, 30, 31,
111 32, 33, 34, 35, 36, 37, 38, 39,
112 40, 41, 42, 43, 44, 45, 46, 47,
113 48, 49, 50, 51, 52, 53, 54, 55,
114 56, 57, 58, 59, 60, 61, 62, 63,
115 64, 65, 66, 67, 68, 69, 70, 71,
116 72, 73, 74, 75, 76, 77, 78, 79,
117 80, 81, 82, 83, 84, 85, 86, 87,
118 88, 89, 90, 91, 92, 93, 94, 95,
119 96, 97, 98, 99, 100, 101, 102, 103,
120 104, 105, 106, 107, 108, 109, 110, 111,
121 112, 113, 114, 115, 116, 117, 118, 119,
122 120, 121, 122, 123, 124, 125, 126, 127,
123 128, 129, 130, 131, 132, 133, 134, 135,
124 },
125 .oobfree = { {2, 6}, {136, 82} },
126};
127
128
129/*
130 * Generic flash bbt descriptors
131 */
132static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
133static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
134
135static struct nand_bbt_descr bbt_main_descr = {
136 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
137 NAND_BBT_2BIT | NAND_BBT_VERSION,
138 .offs = 2, /* 0 on 8-bit small page */
139 .len = 4,
140 .veroffs = 6,
141 .maxblocks = 4,
142 .pattern = bbt_pattern,
143};
144
145static struct nand_bbt_descr bbt_mirror_descr = {
146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
147 NAND_BBT_2BIT | NAND_BBT_VERSION,
148 .offs = 2, /* 0 on 8-bit small page */
149 .len = 4,
150 .veroffs = 6,
151 .maxblocks = 4,
152 .pattern = mirror_pattern,
153};
154
155/*
156 * Set up the IFC hardware block and page address fields, and the ifc nand
157 * structure addr field to point to the correct IFC buffer in memory
158 */
159static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
160{
161 struct nand_chip *chip = mtd->priv;
162 struct fsl_ifc_mtd *priv = chip->priv;
163 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
164 struct fsl_ifc *ifc = ctrl->regs;
165 int buf_num;
166
167 ctrl->page = page_addr;
168
169 /* Program ROW0/COL0 */
170 out_be32(&ifc->ifc_nand.row0, page_addr);
171 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
172
173 buf_num = page_addr & priv->bufnum_mask;
174
175 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
176 ctrl->index = column;
177
178 /* for OOB data point to the second half of the buffer */
179 if (oob)
180 ctrl->index += mtd->writesize;
181}
182
183static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
184 unsigned int bufnum)
185{
186 struct nand_chip *chip = mtd->priv;
187 struct fsl_ifc_mtd *priv = chip->priv;
188 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
189 u32 __iomem *main = (u32 *)addr;
190 u8 __iomem *oob = addr + mtd->writesize;
191 int i;
192
193 for (i = 0; i < mtd->writesize / 4; i++) {
194 if (__raw_readl(&main[i]) != 0xffffffff)
195 return 0;
196 }
197
198 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
199 int pos = chip->ecc.layout->eccpos[i];
200
201 if (__raw_readb(&oob[pos]) != 0xff)
202 return 0;
203 }
204
205 return 1;
206}
207
208/* returns nonzero if entire page is blank */
209static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
210 u32 *eccstat, unsigned int bufnum)
211{
212 u32 reg = eccstat[bufnum / 4];
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530213 int errors;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530214
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530215 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530216
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530217 return errors;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530218}
219
220/*
221 * execute IFC NAND command and wait for it to complete
222 */
223static int fsl_ifc_run_command(struct mtd_info *mtd)
224{
225 struct nand_chip *chip = mtd->priv;
226 struct fsl_ifc_mtd *priv = chip->priv;
227 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
228 struct fsl_ifc *ifc = ctrl->regs;
229 long long end_tick;
230 u32 eccstat[4];
231 int i;
232
233 /* set the chip select for NAND Transaction */
234 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
235
236 /* start read/write seq */
237 out_be32(&ifc->ifc_nand.nandseq_strt,
238 IFC_NAND_SEQ_STRT_FIR_STRT);
239
240 /* wait for NAND Machine complete flag or timeout */
241 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
242
243 while (end_tick > get_ticks()) {
244 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
245
246 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
247 break;
248 }
249
250 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
251
252 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
253 printf("%s: Flash Time Out Error\n", __func__);
254 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
255 printf("%s: Write Protect Error\n", __func__);
256
257 if (ctrl->eccread) {
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530258 int errors;
259 int bufnum = ctrl->page & priv->bufnum_mask;
260 int sector = bufnum * chip->ecc.steps;
261 int sector_end = sector + chip->ecc.steps - 1;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530262
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530263 for (i = sector / 4; i <= sector_end / 4; i++)
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530264 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
265
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530266 for (i = sector; i <= sector_end; i++) {
267 errors = check_read_ecc(mtd, ctrl, eccstat, i);
268
269 if (errors == 15) {
270 /*
271 * Uncorrectable error.
272 * OK only if the whole page is blank.
273 *
274 * We disable ECCER reporting due to erratum
275 * IFC-A002770 -- so report it now if we
276 * see an uncorrectable error in ECCSTAT.
277 */
278 if (!is_blank(mtd, ctrl, bufnum))
279 ctrl->status |=
280 IFC_NAND_EVTER_STAT_ECCER;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530281 break;
Prabhakar Kushwaha5f720b82012-01-20 18:38:14 +0530282 }
283
284 mtd->ecc_stats.corrected += errors;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530285 }
286
287 ctrl->eccread = 0;
288 }
289
290 /* returns 0 on success otherwise non-zero) */
291 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
292}
293
294static void fsl_ifc_do_read(struct nand_chip *chip,
295 int oob,
296 struct mtd_info *mtd)
297{
298 struct fsl_ifc_mtd *priv = chip->priv;
299 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
300 struct fsl_ifc *ifc = ctrl->regs;
301
302 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
303 if (mtd->writesize > 512) {
304 out_be32(&ifc->ifc_nand.nand_fir0,
305 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
306 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
307 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
308 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
309 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
310 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
311
312 out_be32(&ifc->ifc_nand.nand_fcr0,
313 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
314 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
315 } else {
316 out_be32(&ifc->ifc_nand.nand_fir0,
317 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
321
322 if (oob)
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
325 else
326 out_be32(&ifc->ifc_nand.nand_fcr0,
327 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
328 }
329}
330
331/* cmdfunc send commands to the IFC NAND Machine */
332static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
333 int column, int page_addr)
334{
335 struct nand_chip *chip = mtd->priv;
336 struct fsl_ifc_mtd *priv = chip->priv;
337 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
338 struct fsl_ifc *ifc = ctrl->regs;
339
340 /* clear the read buffer */
341 ctrl->read_bytes = 0;
342 if (command != NAND_CMD_PAGEPROG)
343 ctrl->index = 0;
344
345 switch (command) {
346 /* READ0 read the entire buffer to use hardware ECC. */
347 case NAND_CMD_READ0: {
348 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
349 set_addr(mtd, 0, page_addr, 0);
350
351 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
352 ctrl->index += column;
353
354 if (chip->ecc.mode == NAND_ECC_HW)
355 ctrl->eccread = 1;
356
357 fsl_ifc_do_read(chip, 0, mtd);
358 fsl_ifc_run_command(mtd);
359 return;
360 }
361
362 /* READOOB reads only the OOB because no ECC is performed. */
363 case NAND_CMD_READOOB:
364 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
365 set_addr(mtd, column, page_addr, 1);
366
367 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
368
369 fsl_ifc_do_read(chip, 1, mtd);
370 fsl_ifc_run_command(mtd);
371
372 return;
373
374 /* READID must read all possible bytes while CEB is active */
375 case NAND_CMD_READID:
Prabhakar Kushwaha807fc702012-04-08 18:57:18 +0000376 case NAND_CMD_PARAM: {
377 int timing = IFC_FIR_OP_RB;
378 if (command == NAND_CMD_PARAM)
379 timing = IFC_FIR_OP_RBCD;
380
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530381 out_be32(&ifc->ifc_nand.nand_fir0,
Prabhakar Kushwahaba427672012-11-07 21:52:27 +0000382 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530383 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
Prabhakar Kushwaha807fc702012-04-08 18:57:18 +0000384 (timing << IFC_NAND_FIR0_OP2_SHIFT));
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530385 out_be32(&ifc->ifc_nand.nand_fcr0,
Prabhakar Kushwaha807fc702012-04-08 18:57:18 +0000386 command << IFC_NAND_FCR0_CMD0_SHIFT);
387 out_be32(&ifc->ifc_nand.row3, column);
388
389 /*
390 * although currently it's 8 bytes for READID, we always read
391 * the maximum 256 bytes(for PARAM)
392 */
393 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
394 ctrl->read_bytes = 256;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530395
396 set_addr(mtd, 0, 0, 0);
397 fsl_ifc_run_command(mtd);
398 return;
Prabhakar Kushwaha807fc702012-04-08 18:57:18 +0000399 }
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530400
401 /* ERASE1 stores the block and page address */
402 case NAND_CMD_ERASE1:
403 set_addr(mtd, 0, page_addr, 0);
404 return;
405
406 /* ERASE2 uses the block and page address from ERASE1 */
407 case NAND_CMD_ERASE2:
408 out_be32(&ifc->ifc_nand.nand_fir0,
409 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
410 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
411 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
412
413 out_be32(&ifc->ifc_nand.nand_fcr0,
414 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
415 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
416
417 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
418 ctrl->read_bytes = 0;
419 fsl_ifc_run_command(mtd);
420 return;
421
422 /* SEQIN sets up the addr buffer and all registers except the length */
423 case NAND_CMD_SEQIN: {
424 u32 nand_fcr0;
425 ctrl->column = column;
426 ctrl->oob = 0;
427
428 if (mtd->writesize > 512) {
429 nand_fcr0 =
430 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
Prabhakar Kushwahaed5ac342013-10-03 11:35:35 +0530431 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
432 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530433
434 out_be32(&ifc->ifc_nand.nand_fir0,
435 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
436 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
437 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
438 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
Prabhakar Kushwahaed5ac342013-10-03 11:35:35 +0530439 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
440 out_be32(&ifc->ifc_nand.nand_fir1,
441 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
442 (IFC_FIR_OP_RDSTAT <<
443 IFC_NAND_FIR1_OP6_SHIFT) |
444 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530445 } else {
446 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
447 IFC_NAND_FCR0_CMD1_SHIFT) |
448 (NAND_CMD_SEQIN <<
Prabhakar Kushwahaed5ac342013-10-03 11:35:35 +0530449 IFC_NAND_FCR0_CMD2_SHIFT) |
450 (NAND_CMD_STATUS <<
451 IFC_NAND_FCR0_CMD3_SHIFT));
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530452
453 out_be32(&ifc->ifc_nand.nand_fir0,
454 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
455 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
456 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
457 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
458 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
459 out_be32(&ifc->ifc_nand.nand_fir1,
Prabhakar Kushwahaed5ac342013-10-03 11:35:35 +0530460 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
461 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
462 (IFC_FIR_OP_RDSTAT <<
463 IFC_NAND_FIR1_OP7_SHIFT) |
464 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530465
Prabhakar Kushwahad9036122012-01-20 18:39:05 +0530466 if (column >= mtd->writesize)
467 nand_fcr0 |=
468 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
469 else
470 nand_fcr0 |=
471 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530472 }
473
Prabhakar Kushwahad9036122012-01-20 18:39:05 +0530474 if (column >= mtd->writesize) {
475 /* OOB area --> READOOB */
476 column -= mtd->writesize;
477 ctrl->oob = 1;
478 }
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530479 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
480 set_addr(mtd, column, page_addr, ctrl->oob);
481 return;
482 }
483
484 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
485 case NAND_CMD_PAGEPROG:
486 if (ctrl->oob)
Prabhakar Kushwahad9036122012-01-20 18:39:05 +0530487 out_be32(&ifc->ifc_nand.nand_fbcr,
488 ctrl->index - ctrl->column);
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530489 else
490 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
491
492 fsl_ifc_run_command(mtd);
493 return;
494
495 case NAND_CMD_STATUS:
496 out_be32(&ifc->ifc_nand.nand_fir0,
497 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499 out_be32(&ifc->ifc_nand.nand_fcr0,
500 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
502 set_addr(mtd, 0, 0, 0);
503 ctrl->read_bytes = 1;
504
505 fsl_ifc_run_command(mtd);
506
507 /* Chip sometimes reporting write protect even when it's not */
508 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
509 return;
510
511 case NAND_CMD_RESET:
512 out_be32(&ifc->ifc_nand.nand_fir0,
513 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
514 out_be32(&ifc->ifc_nand.nand_fcr0,
515 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
516 fsl_ifc_run_command(mtd);
517 return;
518
519 default:
520 printf("%s: error, unsupported command 0x%x.\n",
521 __func__, command);
522 }
523}
524
525/*
526 * Write buf to the IFC NAND Controller Data Buffer
527 */
528static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
529{
530 struct nand_chip *chip = mtd->priv;
531 struct fsl_ifc_mtd *priv = chip->priv;
532 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
533 unsigned int bufsize = mtd->writesize + mtd->oobsize;
534
535 if (len <= 0) {
536 printf("%s of %d bytes", __func__, len);
537 ctrl->status = 0;
538 return;
539 }
540
541 if ((unsigned int)len > bufsize - ctrl->index) {
542 printf("%s beyond end of buffer "
543 "(%d requested, %u available)\n",
544 __func__, len, bufsize - ctrl->index);
545 len = bufsize - ctrl->index;
546 }
547
548 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
549 ctrl->index += len;
550}
551
552/*
553 * read a byte from either the IFC hardware buffer if it has any data left
554 * otherwise issue a command to read a single byte.
555 */
556static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
557{
558 struct nand_chip *chip = mtd->priv;
559 struct fsl_ifc_mtd *priv = chip->priv;
560 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
561
562 /* If there are still bytes in the IFC buffer, then use the
563 * next byte. */
564 if (ctrl->index < ctrl->read_bytes)
565 return in_8(&ctrl->addr[ctrl->index++]);
566
567 printf("%s beyond end of buffer\n", __func__);
568 return ERR_BYTE;
569}
570
571/*
572 * Read two bytes from the IFC hardware buffer
573 * read function for 16-bit buswith
574 */
575static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
576{
577 struct nand_chip *chip = mtd->priv;
578 struct fsl_ifc_mtd *priv = chip->priv;
579 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
580 uint16_t data;
581
582 /*
583 * If there are still bytes in the IFC buffer, then use the
584 * next byte.
585 */
586 if (ctrl->index < ctrl->read_bytes) {
587 data = in_be16((uint16_t *)&ctrl->
588 addr[ctrl->index]);
589 ctrl->index += 2;
590 return (uint8_t)data;
591 }
592
593 printf("%s beyond end of buffer\n", __func__);
594 return ERR_BYTE;
595}
596
597/*
598 * Read from the IFC Controller Data Buffer
599 */
600static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
601{
602 struct nand_chip *chip = mtd->priv;
603 struct fsl_ifc_mtd *priv = chip->priv;
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
605 int avail;
606
607 if (len < 0)
608 return;
609
610 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
611 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
612 ctrl->index += avail;
613
614 if (len > avail)
615 printf("%s beyond end of buffer "
616 "(%d requested, %d available)\n",
617 __func__, len, avail);
618}
619
620/*
621 * Verify buffer against the IFC Controller Data Buffer
622 */
623static int fsl_ifc_verify_buf(struct mtd_info *mtd,
624 const u_char *buf, int len)
625{
626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv;
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
629 int i;
630
631 if (len < 0) {
632 printf("%s of %d bytes", __func__, len);
633 return -EINVAL;
634 }
635
636 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
637 printf("%s beyond end of buffer "
638 "(%d requested, %u available)\n",
639 __func__, len, ctrl->read_bytes - ctrl->index);
640
641 ctrl->index = ctrl->read_bytes;
642 return -EINVAL;
643 }
644
645 for (i = 0; i < len; i++)
646 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
647 break;
648
649 ctrl->index += len;
650 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
651}
652
653/* This function is called after Program and Erase Operations to
654 * check for success or failure.
655 */
656static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
657{
658 struct fsl_ifc_mtd *priv = chip->priv;
659 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
660 struct fsl_ifc *ifc = ctrl->regs;
661 u32 nand_fsr;
662
663 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
664 return NAND_STATUS_FAIL;
665
666 /* Use READ_STATUS command, but wait for the device to be ready */
667 out_be32(&ifc->ifc_nand.nand_fir0,
668 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
669 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
670 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
671 IFC_NAND_FCR0_CMD0_SHIFT);
672 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
673 set_addr(mtd, 0, 0, 0);
674 ctrl->read_bytes = 1;
675
676 fsl_ifc_run_command(mtd);
677
678 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
679 return NAND_STATUS_FAIL;
680
681 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
682
683 /* Chip sometimes reporting write protect even when it's not */
684 nand_fsr = nand_fsr | NAND_STATUS_WP;
685 return nand_fsr;
686}
687
Sergey Lapindfe64e22013-01-14 03:46:50 +0000688static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
689 uint8_t *buf, int oob_required, int page)
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530690{
691 struct fsl_ifc_mtd *priv = chip->priv;
692 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
693
694 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
695 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
696
697 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
698 mtd->ecc_stats.failed++;
699
700 return 0;
701}
702
703/* ECC will be calculated automatically, and errors will be detected in
704 * waitfunc.
705 */
Sergey Lapindfe64e22013-01-14 03:46:50 +0000706static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
707 const uint8_t *buf, int oob_required)
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530708{
709 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
710 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
Sergey Lapindfe64e22013-01-14 03:46:50 +0000711
712 return 0;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530713}
714
715static void fsl_ifc_ctrl_init(void)
716{
717 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
718 if (!ifc_ctrl)
719 return;
720
721 ifc_ctrl->regs = IFC_BASE_ADDR;
722
723 /* clear event registers */
724 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
725 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
726
727 /* Enable error and event for any detected errors */
728 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
729 IFC_NAND_EVTER_EN_OPC_EN |
730 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
731 IFC_NAND_EVTER_EN_FTOER_EN |
732 IFC_NAND_EVTER_EN_WPER_EN);
733
734 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
735}
736
737static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
738{
739}
740
Prabhakar Kushwaha79da5e32012-09-12 22:26:05 +0000741static void fsl_ifc_sram_init(void)
742{
743 struct fsl_ifc *ifc = ifc_ctrl->regs;
744 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
745 long long end_tick;
746
747 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
748
749 /* Save CSOR and CSOR_ext */
750 csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
751 csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
752
753 /* chage PageSize 8K and SpareSize 1K*/
754 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
755 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
756 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
757
758 /* READID */
759 out_be32(&ifc->ifc_nand.nand_fir0,
Prabhakar Kushwahaba427672012-11-07 21:52:27 +0000760 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
Prabhakar Kushwaha79da5e32012-09-12 22:26:05 +0000761 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
762 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
763 out_be32(&ifc->ifc_nand.nand_fcr0,
764 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
765 out_be32(&ifc->ifc_nand.row3, 0x0);
766
767 out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
768
769 /* Program ROW0/COL0 */
770 out_be32(&ifc->ifc_nand.row0, 0x0);
771 out_be32(&ifc->ifc_nand.col0, 0x0);
772
773 /* set the chip select for NAND Transaction */
774 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
775
776 /* start read seq */
777 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
778
779 /* wait for NAND Machine complete flag or timeout */
780 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
781
782 while (end_tick > get_ticks()) {
783 ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
784
785 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
786 break;
787 }
788
789 out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
790
791 /* Restore CSOR and CSOR_ext */
792 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
793 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
794}
795
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000796static int fsl_ifc_chip_init(int devnum, u8 *addr)
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530797{
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000798 struct mtd_info *mtd = &nand_info[devnum];
799 struct nand_chip *nand;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530800 struct fsl_ifc_mtd *priv;
801 struct nand_ecclayout *layout;
Prabhakar Kushwaha79da5e32012-09-12 22:26:05 +0000802 uint32_t cspr = 0, csor = 0, ver = 0;
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000803 int ret;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530804
805 if (!ifc_ctrl) {
806 fsl_ifc_ctrl_init();
807 if (!ifc_ctrl)
808 return -1;
809 }
810
811 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
812 if (!priv)
813 return -ENOMEM;
814
815 priv->ctrl = ifc_ctrl;
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000816 priv->vbase = addr;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530817
818 /* Find which chip select it is connected to.
819 */
820 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000821 phys_addr_t phys_addr = virt_to_phys(addr);
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530822
823 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
824 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
825
826 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000827 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530828 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
829 break;
830 }
831 }
832
833 if (priv->bank >= MAX_BANKS) {
834 printf("%s: address did not match any "
835 "chip selects\n", __func__);
Prabhakar Kushwaha76d067a2012-04-10 22:48:27 +0000836 kfree(priv);
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530837 return -ENODEV;
838 }
839
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000840 nand = &priv->chip;
841 mtd->priv = nand;
842
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530843 ifc_ctrl->chips[priv->bank] = priv;
844
845 /* fill in nand_chip structure */
846 /* set up function call table */
847
848 nand->write_buf = fsl_ifc_write_buf;
849 nand->read_buf = fsl_ifc_read_buf;
850 nand->verify_buf = fsl_ifc_verify_buf;
851 nand->select_chip = fsl_ifc_select_chip;
852 nand->cmdfunc = fsl_ifc_cmdfunc;
853 nand->waitfunc = fsl_ifc_wait;
854
855 /* set up nand options */
856 nand->bbt_td = &bbt_main_descr;
857 nand->bbt_md = &bbt_mirror_descr;
858
859 /* set up nand options */
Sergey Lapindfe64e22013-01-14 03:46:50 +0000860 nand->options = NAND_NO_SUBPAGE_WRITE;
861 nand->bbt_options = NAND_BBT_USE_FLASH;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530862
863 if (cspr & CSPR_PORT_SIZE_16) {
864 nand->read_byte = fsl_ifc_read_byte16;
865 nand->options |= NAND_BUSWIDTH_16;
866 } else {
867 nand->read_byte = fsl_ifc_read_byte;
868 }
869
870 nand->controller = &ifc_ctrl->controller;
871 nand->priv = priv;
872
873 nand->ecc.read_page = fsl_ifc_read_page;
874 nand->ecc.write_page = fsl_ifc_write_page;
875
876 /* Hardware generates ECC per 512 Bytes */
877 nand->ecc.size = 512;
878 nand->ecc.bytes = 8;
879
880 switch (csor & CSOR_NAND_PGS_MASK) {
881 case CSOR_NAND_PGS_512:
882 if (nand->options & NAND_BUSWIDTH_16) {
883 layout = &oob_512_16bit_ecc4;
884 } else {
885 layout = &oob_512_8bit_ecc4;
886
887 /* Avoid conflict with bad block marker */
888 bbt_main_descr.offs = 0;
889 bbt_mirror_descr.offs = 0;
890 }
891
Sergey Lapindfe64e22013-01-14 03:46:50 +0000892 nand->ecc.strength = 4;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530893 priv->bufnum_mask = 15;
894 break;
895
896 case CSOR_NAND_PGS_2K:
897 layout = &oob_2048_ecc4;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000898 nand->ecc.strength = 4;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530899 priv->bufnum_mask = 3;
900 break;
901
902 case CSOR_NAND_PGS_4K:
903 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
904 CSOR_NAND_ECC_MODE_4) {
905 layout = &oob_4096_ecc4;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000906 nand->ecc.strength = 4;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530907 } else {
908 layout = &oob_4096_ecc8;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000909 nand->ecc.strength = 8;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530910 nand->ecc.bytes = 16;
911 }
912
913 priv->bufnum_mask = 1;
914 break;
915
916 default:
917 printf("ifc nand: bad csor %#x: bad page size\n", csor);
918 return -ENODEV;
919 }
920
921 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
922 if (csor & CSOR_NAND_ECC_DEC_EN) {
923 nand->ecc.mode = NAND_ECC_HW;
924 nand->ecc.layout = layout;
925 } else {
926 nand->ecc.mode = NAND_ECC_SOFT;
927 }
928
Prabhakar Kushwaha79da5e32012-09-12 22:26:05 +0000929 ver = in_be32(&ifc_ctrl->regs->ifc_rev);
930 if (ver == FSL_IFC_V1_1_0)
931 fsl_ifc_sram_init();
932
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000933 ret = nand_scan_ident(mtd, 1, NULL);
934 if (ret)
935 return ret;
936
937 ret = nand_scan_tail(mtd);
938 if (ret)
939 return ret;
940
941 ret = nand_register(devnum);
942 if (ret)
943 return ret;
Dipen Dudhat52f90da2011-03-22 09:27:39 +0530944 return 0;
945}
Prabhakar Kushwahaa1b81ab2013-04-04 18:44:06 +0000946
947#ifndef CONFIG_SYS_NAND_BASE_LIST
948#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
949#endif
950
951static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
952 CONFIG_SYS_NAND_BASE_LIST;
953
954void board_nand_init(void)
955{
956 int i;
957
958 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
959 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
960}