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robert lazarski7bd61042007-12-21 10:36:37 -05001/*
2 * Copyright 2007
3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
4 *
5 * Copyright 2004, 2007 Freescale Semiconductor.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * atum8548 board configuration file
28 *
29 * Please refer to doc/README.atum8548 for more info.
30 *
31 */
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/* Debug Options, Disable in production
36#define ET_DEBUG 1
37#define CONFIG_PANIC_HANG 1
38#define DEBUG 1
39*/
40
41/* CPLD Configuration Options */
42#define MPC85xx_ATUM_CLKOCR 0x80000002
43
44/* High Level Configuration Options */
45#define CONFIG_BOOKE 1 /* BOOKE */
46#define CONFIG_E500 1 /* BOOKE e500 family */
47#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
48#define CONFIG_MPC8548 1 /* MPC8548 specific */
49
50#define CONFIG_PCI 1 /* enable any pci type devices */
51#define CONFIG_PCI1 1 /* PCI controller 1 */
52#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
53#define CONFIG_PCI2 1 /* PCI controller 2 */
54#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
55
56#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
57#define CONFIG_ENV_OVERWRITE
robert lazarski7bd61042007-12-21 10:36:37 -050058
robert lazarski7bd61042007-12-21 10:36:37 -050059#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
60
Kumar Gala4d3521c2008-01-16 09:15:29 -060061#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
62
robert lazarski7bd61042007-12-21 10:36:37 -050063#define CONFIG_SYS_CLK_FREQ 33000000
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
72
73/*
74 * Only possible on E500 Version 2 or newer cores.
75 */
76#define CONFIG_ENABLE_36BIT_PHYS 1
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
79
Wolfgang Denk53677ef2008-05-20 16:00:29 +020080#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
robert lazarski7bd61042007-12-21 10:36:37 -050081#define CONFIG_ENABLE_36BIT_PHYS 1
82#undef CFG_DRAM_TEST
83#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
84#define CFG_MEMTEST_END 0x00400000
85
86/*
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
89 */
90#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -060092#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
robert lazarski7bd61042007-12-21 10:36:37 -050093#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
94
95#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
96#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
97#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
98#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
99
Kumar Galaa947e4c2008-08-26 23:14:14 -0500100/* DDR Setup */
101#define CONFIG_FSL_DDR2
102#undef CONFIG_FSL_DDR_INTERACTIVE
103#define CONFIG_DDR_ECC /* only for ECC DDR module */
104#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
105#define CONFIG_DDR_SPD
106
107#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
108#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
109
110#define CFG_DDR_SDRAM_BASE 0x00000000
robert lazarski7bd61042007-12-21 10:36:37 -0500111#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
Kumar Galaa947e4c2008-08-26 23:14:14 -0500112#define CONFIG_VERY_BIG_RAM
robert lazarski7bd61042007-12-21 10:36:37 -0500113
Kumar Galaa947e4c2008-08-26 23:14:14 -0500114#define CONFIG_NUM_DDR_CONTROLLERS 1
115#define CONFIG_DIMM_SLOTS_PER_CTLR 1
116#define CONFIG_CHIP_SELECTS_PER_CTRL 2
robert lazarski7bd61042007-12-21 10:36:37 -0500117
Kumar Galaa947e4c2008-08-26 23:14:14 -0500118/* I2C addresses of SPD EEPROMs */
119#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
120
121/* Manually set up DDR parameters */
122#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
123#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
124#define CFG_DDR_CS0_CONFIG 0x80000102
125#define CFG_DDR_TIMING_0 0x00260802
126#define CFG_DDR_TIMING_1 0x38355322
127#define CFG_DDR_TIMING_2 0x039048c7
128#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
129#define CFG_DDR_MODE 0x00000432
130#define CFG_DDR_INTERVAL 0x05150100
131#define DDR_SDRAM_CFG 0x43000000
robert lazarski7bd61042007-12-21 10:36:37 -0500132
133#undef CONFIG_CLOCKS_IN_MHZ
134
135/*
136 * Local Bus Definitions
137 */
138
139/*
140 * FLASH on the Local Bus
141 * based on flash chip S29GL01GP
142 * One bank, 128M, using the CFI driver.
143 * Boot from BR0 bank at 0xf800_0000
144 *
145 * BR0:
146 * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
147 * Port Size = 16 bits = BRx[19:20] = 10
148 * Use GPCM = BRx[24:26] = 000
149 * Valid = BRx[31] = 1
150 *
151 * 0 4 8 12 16 20 24 28
152 * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
153 *
154 * OR0:
155 * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
156 * Reserved ORx[17:18] = 00
157 * CSNT = ORx[20] = 1
158 * ACS = half cycle delay = ORx[21:22] = 11
159 * SCY = 6 = ORx[24:27] = 0110
160 * TRLX = use relaxed timing = ORx[29] = 1
161 * EAD = use external address latch delay = OR[31] = 1
162 *
163 * 0 4 8 12 16 20 24 28
164 * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
165 */
166
167#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
168#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
169
170#define CFG_BR0_PRELIM 0xf8001001
171
172#define CFG_OR0_PRELIM 0xf8000E65
173
174#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
175#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
176#undef CFG_FLASH_CHECKSUM
177#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
178#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
179
180
181#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
182
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200183#define CONFIG_FLASH_CFI_DRIVER 1
robert lazarski7bd61042007-12-21 10:36:37 -0500184#define CFG_FLASH_CFI 1
185#define CFG_FLASH_EMPTY_INFO
186
187/*
188 * Flash on the LocalBus
189 */
190#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
191
192/* Memory */
193#define CFG_INIT_RAM_LOCK 1
194#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
195#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
196
197#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
198
199#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
200#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
201#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
202
203#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
204#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
205
206/* Serial Port */
207#define CONFIG_CONS_INDEX 1
208#undef CONFIG_SERIAL_SOFTWARE_FIFO
209#define CFG_NS16550
210#define CFG_NS16550_SERIAL
211#define CFG_NS16550_REG_SIZE 1
212#define CFG_NS16550_CLK get_bus_freq(0)
213
214#define CFG_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
216
217#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
218#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
219
220/* Use the HUSH parser */
221#define CFG_HUSH_PARSER
222#ifdef CFG_HUSH_PARSER
223#define CFG_PROMPT_HUSH_PS2 "> "
224#endif
225
226/* pass open firmware flat tree */
227#define CONFIG_OF_LIBFDT 1
228#define CONFIG_OF_BOARD_SETUP 1
229
230/*
231 * I2C
232 */
233#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
234#define CONFIG_HARD_I2C /* I2C with hardware support*/
235#undef CONFIG_SOFT_I2C /* I2C bit-banged */
236#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
237#define CFG_I2C_EEPROM_ADDR 0x57
238#define CFG_I2C_SLAVE 0x7F
239#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
240#define CFG_I2C_OFFSET 0x3000
241
242/*
243 * General PCI
244 * Memory space is mapped 1-1, but I/O space must start from 0.
245 */
246#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
247
248#define CFG_PCI1_MEM_BASE 0x80000000
249#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
250#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
251#define CFG_PCI1_IO_BASE 0x00000000
252#define CFG_PCI1_IO_PHYS 0xe2000000
253#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
254
255#ifdef CONFIG_PCI2
256#define CFG_PCI2_MEM_BASE 0xC0000000
257#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
258#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
259#define CFG_PCI2_IO_BASE 0x00000000
260#define CFG_PCI2_IO_PHYS 0xe2800000
261#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
262#endif
263
264#ifdef CONFIG_PCIE1
265#define CFG_PCIE1_MEM_BASE 0xa0000000
266#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
267#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
268#define CFG_PCIE1_IO_BASE 0x00000000
269#define CFG_PCIE1_IO_PHYS 0xe3000000
270#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
271#endif
272
273
274#if !defined(CONFIG_PCI_PNP)
275 #define PCI_ENET0_IOADDR 0xe0000000
276 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200277 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
robert lazarski7bd61042007-12-21 10:36:37 -0500278#endif
279
280#if defined(CONFIG_PCI)
281
282#define CONFIG_NET_MULTI
283#define CONFIG_PCI_PNP /* do pci plug-and-play */
284
285#undef CONFIG_EEPRO100
286#undef CONFIG_TULIP
287
288#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
289
290/* PCI view of System Memory */
291#define CFG_PCI_MEMORY_BUS 0x00000000
292#define CFG_PCI_MEMORY_PHYS 0x00000000
293#define CFG_PCI_MEMORY_SIZE 0x80000000
294
295#endif /* CONFIG_PCI */
296
297#if defined(CONFIG_TSEC_ENET)
298
299#ifndef CONFIG_NET_MULTI
300#define CONFIG_NET_MULTI 1
301#endif
302
303#define CONFIG_MII 1 /* MII PHY management */
304#define CONFIG_TSEC1 1
305#define CONFIG_TSEC1_NAME "eTSEC0"
306#define CONFIG_TSEC2 1
307#define CONFIG_TSEC2_NAME "eTSEC1"
308#define CONFIG_TSEC3 1
309#define CONFIG_TSEC3_NAME "eTSEC2"
310#define CONFIG_TSEC4 1
311#define CONFIG_TSEC4_NAME "eTSEC3"
312#undef CONFIG_MPC85XX_FEC
313
314#define TSEC1_PHY_ADDR 0
315#define TSEC2_PHY_ADDR 1
316#define TSEC3_PHY_ADDR 2
317#define TSEC4_PHY_ADDR 3
318
319#define TSEC1_PHYIDX 0
320#define TSEC2_PHYIDX 0
321#define TSEC3_PHYIDX 0
322#define TSEC4_PHYIDX 0
323#define TSEC1_FLAGS TSEC_GIGABIT
324#define TSEC2_FLAGS TSEC_GIGABIT
325#define TSEC3_FLAGS TSEC_GIGABIT
326#define TSEC4_FLAGS TSEC_GIGABIT
327
328/* Options are: eTSEC[0-3] */
329#define CONFIG_ETHPRIME "eTSEC2"
330#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
331#endif /* CONFIG_TSEC_ENET */
332
333/*
334 * Environment
335 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200336#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200337#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
338#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
339#define CONFIG_ENV_SIZE 0x2000
robert lazarski7bd61042007-12-21 10:36:37 -0500340
341#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
342#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
343
344/*
345 * BOOTP options
346 */
347#define CONFIG_BOOTP_BOOTFILESIZE
348#define CONFIG_BOOTP_BOOTPATH
349#define CONFIG_BOOTP_GATEWAY
350#define CONFIG_BOOTP_HOSTNAME
351
352
353/*
354 * Command line configuration.
355 */
356#include <config_cmd_default.h>
357
358#define CONFIG_CMD_PING
359#define CONFIG_CMD_I2C
360#define CONFIG_CMD_MII
361
362#if defined(CONFIG_PCI)
363 #define CONFIG_CMD_PCI
364#endif
365
366
367#undef CONFIG_WATCHDOG /* watchdog disabled */
368
369/*
370 * Miscellaneous configurable options
371 */
372#define CFG_LONGHELP /* undef to save memory */
373#define CFG_LOAD_ADDR 0x2000000 /* default load address */
374#define CFG_PROMPT "=> " /* Monitor Command Prompt */
375#if defined(CONFIG_CMD_KGDB)
376#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
377#else
378#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
379#endif
380#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
381#define CFG_MAXARGS 16 /* max number of command args */
382#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
383#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
384
385/*
386 * For booting Linux, the board info and command line data
387 * have to be in the first 8 MB of memory, since this is
388 * the maximum mapped by the Linux kernel during initialization.
389 */
390#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
391
robert lazarski7bd61042007-12-21 10:36:37 -0500392/*
393 * Internal Definitions
394 *
395 * Boot Flags
396 */
397#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
398#define BOOTFLAG_WARM 0x02 /* Software reboot */
399
400#if defined(CONFIG_CMD_KGDB)
401#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
402#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
403#endif
404
405/*
406 * Environment Configuration
407 */
408
409/* The mac addresses for all ethernet interface */
410#if defined(CONFIG_TSEC_ENET)
411#define CONFIG_HAS_ETH0
412#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
413#define CONFIG_HAS_ETH1
414#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
415#define CONFIG_HAS_ETH2
416#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
417#define CONFIG_HAS_ETH3
418#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
419#endif
420
421#define CONFIG_IPADDR 10.101.43.142
422
423#define CONFIG_HOSTNAME atum
424#define CONFIG_ROOTPATH /nfsroot
425#define CONFIG_BOOTFILE /tftpboot/uImage.atum
426#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
427
428#define CONFIG_SERVERIP 10.101.43.10
429#define CONFIG_GATEWAYIP 10.101.45.1
430#define CONFIG_NETMASK 255.255.248.0
431
432#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
433
434#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
435#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
436
437#define CONFIG_BAUDRATE 115200
438
439#define CONFIG_NFSBOOTCOMMAND \
440 "setenv bootargs root=/dev/nfs rw " \
441 "nfsroot=$serverip:$rootpath " \
442 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
443 "console=$consoledev,$baudrate $othbootargs;" \
444 "tftp $loadaddr $bootfile;" \
445 "tftp $dtbaddr $dtbfile;" \
446 "bootm $loadaddr - $dtbaddr"
447
448
449#define CONFIG_RAMBOOTCOMMAND \
450 "setenv bootargs root=/dev/ram rw " \
451 "console=$consoledev,$baudrate $othbootargs;" \
452 "tftp $ramdiskaddr $ramdiskfile;" \
453 "tftp $loadaddr $bootfile;" \
454 "tftp $dtbaddr $dtbfile;" \
455 "bootm $loadaddr $ramdiskaddr $dtbaddr"
456
457#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
458
459#endif /* __CONFIG_H */