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Michal Simek185f7d92012-09-13 20:23:34 +00001/*
2 * (C) Copyright 2011 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Michal Simek185f7d92012-09-13 20:23:34 +000010 */
11
12#include <common.h>
13#include <net.h>
Michal Simek2fd24892014-04-25 14:17:38 +020014#include <netdev.h>
Michal Simek185f7d92012-09-13 20:23:34 +000015#include <config.h>
Michal Simekf88a6862014-02-24 11:16:30 +010016#include <fdtdec.h>
17#include <libfdt.h>
Michal Simek185f7d92012-09-13 20:23:34 +000018#include <malloc.h>
19#include <asm/io.h>
20#include <phy.h>
21#include <miiphy.h>
22#include <watchdog.h>
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +053023#include <asm/system.h>
David Andrey01fbf312013-04-05 17:24:24 +020024#include <asm/arch/hardware.h>
Michal Simek80243522012-10-15 14:01:23 +020025#include <asm/arch/sys_proto.h>
Michal Simeke4d23182015-08-17 09:57:46 +020026#include <asm-generic/errno.h>
Michal Simek185f7d92012-09-13 20:23:34 +000027
28#if !defined(CONFIG_PHYLIB)
29# error XILINX_GEM_ETHERNET requires PHYLIB
30#endif
31
32/* Bit/mask specification */
33#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38
39#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42
43#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46
47/* Wrap bit, last descriptor */
48#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
Michal Simek23a598f2015-08-17 09:58:54 +020050#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
Michal Simek185f7d92012-09-13 20:23:34 +000051
Michal Simek185f7d92012-09-13 20:23:34 +000052#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56
Michal Simek80243522012-10-15 14:01:23 +020057#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
58#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
59#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
60#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
Michal Simek6777f382015-09-08 17:07:01 +020061#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
Michal Simek185f7d92012-09-13 20:23:34 +000062
Siva Durga Prasad Paladugu8a584c82014-07-08 15:31:03 +053063#ifdef CONFIG_ARM64
64# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
65#else
66# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
67#endif
68
69#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
70 ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek185f7d92012-09-13 20:23:34 +000071 ZYNQ_GEM_NWCFG_FSREM | \
72 ZYNQ_GEM_NWCFG_MDCCLKDIV)
73
74#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
75
76#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
77/* Use full configured addressable space (8 Kb) */
78#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
79/* Use full configured addressable space (4 Kb) */
80#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
81/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
82#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
83
84#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
85 ZYNQ_GEM_DMACR_RXSIZE | \
86 ZYNQ_GEM_DMACR_TXSIZE | \
87 ZYNQ_GEM_DMACR_RXBUF)
88
Michal Simeke4d23182015-08-17 09:57:46 +020089#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
90
Michal Simekf97d7e82013-04-22 14:41:09 +020091/* Use MII register 1 (MII status register) to detect PHY */
92#define PHY_DETECT_REG 1
93
94/* Mask used to verify certain PHY features (or register contents)
95 * in the register above:
96 * 0x1000: 10Mbps full duplex support
97 * 0x0800: 10Mbps half duplex support
98 * 0x0008: Auto-negotiation support
99 */
100#define PHY_DETECT_MASK 0x1808
101
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530102/* TX BD status masks */
103#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
104#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
105#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
106
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800107/* Clock frequencies for different speeds */
108#define ZYNQ_GEM_FREQUENCY_10 2500000UL
109#define ZYNQ_GEM_FREQUENCY_100 25000000UL
110#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
111
Michal Simek185f7d92012-09-13 20:23:34 +0000112/* Device registers */
113struct zynq_gem_regs {
Michal Simek97a51a02015-10-05 11:49:43 +0200114 u32 nwctrl; /* 0x0 - Network Control reg */
115 u32 nwcfg; /* 0x4 - Network Config reg */
116 u32 nwsr; /* 0x8 - Network Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000117 u32 reserved1;
Michal Simek97a51a02015-10-05 11:49:43 +0200118 u32 dmacr; /* 0x10 - DMA Control reg */
119 u32 txsr; /* 0x14 - TX Status reg */
120 u32 rxqbase; /* 0x18 - RX Q Base address reg */
121 u32 txqbase; /* 0x1c - TX Q Base address reg */
122 u32 rxsr; /* 0x20 - RX Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000123 u32 reserved2[2];
Michal Simek97a51a02015-10-05 11:49:43 +0200124 u32 idr; /* 0x2c - Interrupt Disable reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000125 u32 reserved3;
Michal Simek97a51a02015-10-05 11:49:43 +0200126 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000127 u32 reserved4[18];
Michal Simek97a51a02015-10-05 11:49:43 +0200128 u32 hashl; /* 0x80 - Hash Low address reg */
129 u32 hashh; /* 0x84 - Hash High address reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000130#define LADDR_LOW 0
131#define LADDR_HIGH 1
Michal Simek97a51a02015-10-05 11:49:43 +0200132 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
133 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000134 u32 reserved6[18];
Michal Simek0ebf4042015-10-05 12:49:48 +0200135#define STAT_SIZE 44
136 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700137 u32 reserved7[164];
138 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
139 u32 reserved8[15];
140 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
Michal Simek185f7d92012-09-13 20:23:34 +0000141};
142
143/* BD descriptors */
144struct emac_bd {
145 u32 addr; /* Next descriptor pointer */
146 u32 status;
147};
148
Siva Durga Prasad Paladugueda9d302015-04-15 12:15:01 +0530149#define RX_BUF 32
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530150/* Page table entries are set to 1MB, or multiples of 1MB
151 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
152 */
153#define BD_SPACE 0x100000
154/* BD separation space */
Michal Simekff475872015-08-17 09:45:53 +0200155#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
Michal Simek185f7d92012-09-13 20:23:34 +0000156
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700157/* Setup the first free TX descriptor */
158#define TX_FREE_DESC 2
159
Michal Simek185f7d92012-09-13 20:23:34 +0000160/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
161struct zynq_gem_priv {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530162 struct emac_bd *tx_bd;
163 struct emac_bd *rx_bd;
164 char *rxbuffers;
Michal Simek185f7d92012-09-13 20:23:34 +0000165 u32 rxbd_current;
166 u32 rx_first_buf;
167 int phyaddr;
David Andrey01fbf312013-04-05 17:24:24 +0200168 u32 emio;
Michal Simek05868752013-01-24 13:04:12 +0100169 int init;
Michal Simekf2fc2762015-11-30 10:24:15 +0100170 struct zynq_gem_regs *iobase;
Michal Simek16ce6de2015-10-07 16:42:56 +0200171 phy_interface_t interface;
Michal Simek185f7d92012-09-13 20:23:34 +0000172 struct phy_device *phydev;
173 struct mii_dev *bus;
174};
175
Michal Simek3fac2722015-11-30 10:09:43 +0100176static inline int mdio_wait(struct zynq_gem_regs *regs)
Michal Simek185f7d92012-09-13 20:23:34 +0000177{
Michal Simek4c8b7bf2012-10-16 17:37:11 +0200178 u32 timeout = 20000;
Michal Simek185f7d92012-09-13 20:23:34 +0000179
180 /* Wait till MDIO interface is ready to accept a new transaction. */
181 while (--timeout) {
182 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
183 break;
184 WATCHDOG_RESET();
185 }
186
187 if (!timeout) {
188 printf("%s: Timeout\n", __func__);
189 return 1;
190 }
191
192 return 0;
193}
194
Michal Simekf2fc2762015-11-30 10:24:15 +0100195static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
196 u32 op, u16 *data)
Michal Simek185f7d92012-09-13 20:23:34 +0000197{
198 u32 mgtcr;
Michal Simekf2fc2762015-11-30 10:24:15 +0100199 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000200
Michal Simek3fac2722015-11-30 10:09:43 +0100201 if (mdio_wait(regs))
Michal Simek185f7d92012-09-13 20:23:34 +0000202 return 1;
203
204 /* Construct mgtcr mask for the operation */
205 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
206 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
207 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
208
209 /* Write mgtcr and wait for completion */
210 writel(mgtcr, &regs->phymntnc);
211
Michal Simek3fac2722015-11-30 10:09:43 +0100212 if (mdio_wait(regs))
Michal Simek185f7d92012-09-13 20:23:34 +0000213 return 1;
214
215 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
216 *data = readl(&regs->phymntnc);
217
218 return 0;
219}
220
Michal Simekf2fc2762015-11-30 10:24:15 +0100221static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
222 u32 regnum, u16 *val)
Michal Simek185f7d92012-09-13 20:23:34 +0000223{
Michal Simek198e9a42015-10-07 16:34:51 +0200224 u32 ret;
225
Michal Simekf2fc2762015-11-30 10:24:15 +0100226 ret = phy_setup_op(priv, phy_addr, regnum,
227 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
Michal Simek198e9a42015-10-07 16:34:51 +0200228
229 if (!ret)
230 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
231 phy_addr, regnum, *val);
232
233 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000234}
235
Michal Simekf2fc2762015-11-30 10:24:15 +0100236static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
237 u32 regnum, u16 data)
Michal Simek185f7d92012-09-13 20:23:34 +0000238{
Michal Simek198e9a42015-10-07 16:34:51 +0200239 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
240 regnum, data);
241
Michal Simekf2fc2762015-11-30 10:24:15 +0100242 return phy_setup_op(priv, phy_addr, regnum,
243 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
Michal Simek185f7d92012-09-13 20:23:34 +0000244}
245
Michal Simekb9047252015-11-30 13:38:32 +0100246static int phy_detection(struct eth_device *dev)
Michal Simekf97d7e82013-04-22 14:41:09 +0200247{
248 int i;
249 u16 phyreg;
250 struct zynq_gem_priv *priv = dev->priv;
251
252 if (priv->phyaddr != -1) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100253 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200254 if ((phyreg != 0xFFFF) &&
255 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
256 /* Found a valid PHY address */
257 debug("Default phy address %d is valid\n",
258 priv->phyaddr);
Michal Simekb9047252015-11-30 13:38:32 +0100259 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200260 } else {
261 debug("PHY address is not setup correctly %d\n",
262 priv->phyaddr);
263 priv->phyaddr = -1;
264 }
265 }
266
267 debug("detecting phy address\n");
268 if (priv->phyaddr == -1) {
269 /* detect the PHY address */
270 for (i = 31; i >= 0; i--) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100271 phyread(priv, i, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200272 if ((phyreg != 0xFFFF) &&
273 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
274 /* Found a valid PHY address */
275 priv->phyaddr = i;
276 debug("Found valid phy address, %d\n", i);
Michal Simekb9047252015-11-30 13:38:32 +0100277 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200278 }
279 }
280 }
281 printf("PHY is not detected\n");
Michal Simekb9047252015-11-30 13:38:32 +0100282 return -1;
Michal Simekf97d7e82013-04-22 14:41:09 +0200283}
284
Michal Simek185f7d92012-09-13 20:23:34 +0000285static int zynq_gem_setup_mac(struct eth_device *dev)
286{
287 u32 i, macaddrlow, macaddrhigh;
288 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
289
290 /* Set the MAC bits [31:0] in BOT */
291 macaddrlow = dev->enetaddr[0];
292 macaddrlow |= dev->enetaddr[1] << 8;
293 macaddrlow |= dev->enetaddr[2] << 16;
294 macaddrlow |= dev->enetaddr[3] << 24;
295
296 /* Set MAC bits [47:32] in TOP */
297 macaddrhigh = dev->enetaddr[4];
298 macaddrhigh |= dev->enetaddr[5] << 8;
299
300 for (i = 0; i < 4; i++) {
301 writel(0, &regs->laddr[i][LADDR_LOW]);
302 writel(0, &regs->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, &regs->match[i]);
305 }
306
307 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
309
310 return 0;
311}
312
313static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
314{
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800315 u32 i;
Michal Simekb9047252015-11-30 13:38:32 +0100316 int ret;
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800317 unsigned long clk_rate = 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000318 struct phy_device *phydev;
Michal Simek185f7d92012-09-13 20:23:34 +0000319 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
320 struct zynq_gem_priv *priv = dev->priv;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700321 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
322 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
Michal Simek185f7d92012-09-13 20:23:34 +0000323 const u32 supported = SUPPORTED_10baseT_Half |
324 SUPPORTED_10baseT_Full |
325 SUPPORTED_100baseT_Half |
326 SUPPORTED_100baseT_Full |
327 SUPPORTED_1000baseT_Half |
328 SUPPORTED_1000baseT_Full;
329
Michal Simek05868752013-01-24 13:04:12 +0100330 if (!priv->init) {
331 /* Disable all interrupts */
332 writel(0xFFFFFFFF, &regs->idr);
Michal Simek185f7d92012-09-13 20:23:34 +0000333
Michal Simek05868752013-01-24 13:04:12 +0100334 /* Disable the receiver & transmitter */
335 writel(0, &regs->nwctrl);
336 writel(0, &regs->txsr);
337 writel(0, &regs->rxsr);
338 writel(0, &regs->phymntnc);
Michal Simek185f7d92012-09-13 20:23:34 +0000339
Michal Simek05868752013-01-24 13:04:12 +0100340 /* Clear the Hash registers for the mac address
341 * pointed by AddressPtr
342 */
343 writel(0x0, &regs->hashl);
344 /* Write bits [63:32] in TOP */
345 writel(0x0, &regs->hashh);
Michal Simek185f7d92012-09-13 20:23:34 +0000346
Michal Simek05868752013-01-24 13:04:12 +0100347 /* Clear all counters */
Michal Simek0ebf4042015-10-05 12:49:48 +0200348 for (i = 0; i < STAT_SIZE; i++)
Michal Simek05868752013-01-24 13:04:12 +0100349 readl(&regs->stat[i]);
Michal Simek185f7d92012-09-13 20:23:34 +0000350
Michal Simek05868752013-01-24 13:04:12 +0100351 /* Setup RxBD space */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530352 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000353
Michal Simek05868752013-01-24 13:04:12 +0100354 for (i = 0; i < RX_BUF; i++) {
355 priv->rx_bd[i].status = 0xF0000000;
356 priv->rx_bd[i].addr =
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530357 ((ulong)(priv->rxbuffers) +
Michal Simek185f7d92012-09-13 20:23:34 +0000358 (i * PKTSIZE_ALIGN));
Michal Simek05868752013-01-24 13:04:12 +0100359 }
360 /* WRAP bit to last BD */
361 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
362 /* Write RxBDs to IP */
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530363 writel((ulong)priv->rx_bd, &regs->rxqbase);
Michal Simek185f7d92012-09-13 20:23:34 +0000364
Michal Simek05868752013-01-24 13:04:12 +0100365 /* Setup for DMA Configuration register */
366 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek185f7d92012-09-13 20:23:34 +0000367
Michal Simek05868752013-01-24 13:04:12 +0100368 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek80243522012-10-15 14:01:23 +0200369 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek185f7d92012-09-13 20:23:34 +0000370
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700371 /* Disable the second priority queue */
372 dummy_tx_bd->addr = 0;
373 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
374 ZYNQ_GEM_TXBUF_LAST_MASK|
375 ZYNQ_GEM_TXBUF_USED_MASK;
376
377 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
378 ZYNQ_GEM_RXBUF_NEW_MASK;
379 dummy_rx_bd->status = 0;
380 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
381 sizeof(dummy_tx_bd));
382 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
383 sizeof(dummy_rx_bd));
384
385 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
386 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
387
Michal Simek05868752013-01-24 13:04:12 +0100388 priv->init++;
389 }
390
Michal Simekb9047252015-11-30 13:38:32 +0100391 ret = phy_detection(dev);
392 if (ret) {
393 printf("GEM PHY init failed\n");
394 return ret;
395 }
Michal Simekf97d7e82013-04-22 14:41:09 +0200396
Michal Simek185f7d92012-09-13 20:23:34 +0000397 /* interface - look at tsec */
Michal Simekc1a9fa42014-02-25 10:25:38 +0100398 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
Michal Simek16ce6de2015-10-07 16:42:56 +0200399 priv->interface);
Michal Simek185f7d92012-09-13 20:23:34 +0000400
Michal Simek80243522012-10-15 14:01:23 +0200401 phydev->supported = supported | ADVERTISED_Pause |
402 ADVERTISED_Asym_Pause;
Michal Simek185f7d92012-09-13 20:23:34 +0000403 phydev->advertising = phydev->supported;
404 priv->phydev = phydev;
405 phy_config(phydev);
406 phy_startup(phydev);
407
Michal Simek4ed4aa22013-11-12 14:25:29 +0100408 if (!phydev->link) {
409 printf("%s: No link.\n", phydev->dev->name);
410 return -1;
411 }
412
Michal Simek80243522012-10-15 14:01:23 +0200413 switch (phydev->speed) {
414 case SPEED_1000:
415 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
416 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800417 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simek80243522012-10-15 14:01:23 +0200418 break;
419 case SPEED_100:
Michal Simek242b1542015-09-08 16:55:42 +0200420 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
421 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800422 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simek80243522012-10-15 14:01:23 +0200423 break;
424 case SPEED_10:
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800425 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simek80243522012-10-15 14:01:23 +0200426 break;
427 }
David Andrey01fbf312013-04-05 17:24:24 +0200428
429 /* Change the rclk and clk only not using EMIO interface */
430 if (!priv->emio)
431 zynq_slcr_gem_clk_setup(dev->iobase !=
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800432 ZYNQ_GEM_BASEADDR0, clk_rate);
Michal Simek80243522012-10-15 14:01:23 +0200433
434 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
435 ZYNQ_GEM_NWCTRL_TXEN_MASK);
436
Michal Simek185f7d92012-09-13 20:23:34 +0000437 return 0;
438}
439
Michal Simeke4d23182015-08-17 09:57:46 +0200440static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
441 bool set, unsigned int timeout)
442{
443 u32 val;
444 unsigned long start = get_timer(0);
445
446 while (1) {
447 val = readl(reg);
448
449 if (!set)
450 val = ~val;
451
452 if ((val & mask) == mask)
453 return 0;
454
455 if (get_timer(start) > timeout)
456 break;
457
458 udelay(1);
459 }
460
461 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
462 func, reg, mask, set);
463
464 return -ETIMEDOUT;
465}
466
Michal Simek185f7d92012-09-13 20:23:34 +0000467static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
468{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530469 u32 addr, size;
Michal Simek185f7d92012-09-13 20:23:34 +0000470 struct zynq_gem_priv *priv = dev->priv;
471 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
Michal Simek23a598f2015-08-17 09:58:54 +0200472 struct emac_bd *current_bd = &priv->tx_bd[1];
Michal Simek185f7d92012-09-13 20:23:34 +0000473
Michal Simek185f7d92012-09-13 20:23:34 +0000474 /* Setup Tx BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530475 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000476
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530477 priv->tx_bd->addr = (ulong)ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530478 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
Michal Simek23a598f2015-08-17 09:58:54 +0200479 ZYNQ_GEM_TXBUF_LAST_MASK;
480 /* Dummy descriptor to mark it as the last in descriptor chain */
481 current_bd->addr = 0x0;
482 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
483 ZYNQ_GEM_TXBUF_LAST_MASK|
484 ZYNQ_GEM_TXBUF_USED_MASK;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530485
Michal Simek45c07742015-08-17 09:50:09 +0200486 /* setup BD */
487 writel((ulong)priv->tx_bd, &regs->txqbase);
488
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530489 addr = (ulong) ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530490 addr &= ~(ARCH_DMA_MINALIGN - 1);
491 size = roundup(len, ARCH_DMA_MINALIGN);
492 flush_dcache_range(addr, addr + size);
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530493
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530494 addr = (ulong)priv->rxbuffers;
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530495 addr &= ~(ARCH_DMA_MINALIGN - 1);
496 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
497 flush_dcache_range(addr, addr + size);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530498 barrier();
Michal Simek185f7d92012-09-13 20:23:34 +0000499
500 /* Start transmit */
501 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
502
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530503 /* Read TX BD status */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530504 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
505 printf("TX buffers exhausted in mid frame\n");
Michal Simek185f7d92012-09-13 20:23:34 +0000506
Michal Simeke4d23182015-08-17 09:57:46 +0200507 return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
508 true, 20000);
Michal Simek185f7d92012-09-13 20:23:34 +0000509}
510
511/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
512static int zynq_gem_recv(struct eth_device *dev)
513{
514 int frame_len;
515 struct zynq_gem_priv *priv = dev->priv;
516 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
517 struct emac_bd *first_bd;
518
519 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
520 return 0;
521
522 if (!(current_bd->status &
523 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
524 printf("GEM: SOF or EOF not set for last buffer received!\n");
525 return 0;
526 }
527
528 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
529 if (frame_len) {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530530 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
531 addr &= ~(ARCH_DMA_MINALIGN - 1);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530532
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530533 net_process_received_packet((u8 *)(ulong)addr, frame_len);
Michal Simek185f7d92012-09-13 20:23:34 +0000534
535 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
536 priv->rx_first_buf = priv->rxbd_current;
537 else {
538 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
539 current_bd->status = 0xF0000000; /* FIXME */
540 }
541
542 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
543 first_bd = &priv->rx_bd[priv->rx_first_buf];
544 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
545 first_bd->status = 0xF0000000;
546 }
547
548 if ((++priv->rxbd_current) >= RX_BUF)
549 priv->rxbd_current = 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000550 }
551
Michal Simek3b90d0a2013-01-25 08:24:18 +0100552 return frame_len;
Michal Simek185f7d92012-09-13 20:23:34 +0000553}
554
555static void zynq_gem_halt(struct eth_device *dev)
556{
557 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
558
Michal Simek80243522012-10-15 14:01:23 +0200559 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
560 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek185f7d92012-09-13 20:23:34 +0000561}
562
563static int zynq_gem_miiphyread(const char *devname, uchar addr,
564 uchar reg, ushort *val)
565{
566 struct eth_device *dev = eth_get_dev();
Michal Simekf2fc2762015-11-30 10:24:15 +0100567 struct zynq_gem_priv *priv = dev->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000568 int ret;
569
Michal Simekf2fc2762015-11-30 10:24:15 +0100570 ret = phyread(priv, addr, reg, val);
Michal Simek185f7d92012-09-13 20:23:34 +0000571 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
572 return ret;
573}
574
575static int zynq_gem_miiphy_write(const char *devname, uchar addr,
576 uchar reg, ushort val)
577{
578 struct eth_device *dev = eth_get_dev();
Michal Simekf2fc2762015-11-30 10:24:15 +0100579 struct zynq_gem_priv *priv = dev->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000580
581 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
Michal Simekf2fc2762015-11-30 10:24:15 +0100582 return phywrite(priv, addr, reg, val);
Michal Simek185f7d92012-09-13 20:23:34 +0000583}
584
Michal Simek58405372015-01-14 15:44:21 +0100585int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
586 int phy_addr, u32 emio)
Michal Simek185f7d92012-09-13 20:23:34 +0000587{
588 struct eth_device *dev;
589 struct zynq_gem_priv *priv;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530590 void *bd_space;
Michal Simek185f7d92012-09-13 20:23:34 +0000591
592 dev = calloc(1, sizeof(*dev));
593 if (dev == NULL)
594 return -1;
595
596 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
597 if (dev->priv == NULL) {
598 free(dev);
599 return -1;
600 }
601 priv = dev->priv;
602
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530603 /* Align rxbuffers to ARCH_DMA_MINALIGN */
604 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
605 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
606
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530607 /* Align bd_space to MMU_SECTION_SHIFT */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530608 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Michal Simek9ce1edc2015-04-15 13:31:28 +0200609 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
610 BD_SPACE, DCACHE_OFF);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530611
612 /* Initialize the bd spaces for tx and rx bd's */
613 priv->tx_bd = (struct emac_bd *)bd_space;
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530614 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530615
David Andrey117cd4c2013-04-04 19:13:07 +0200616 priv->phyaddr = phy_addr;
David Andrey01fbf312013-04-05 17:24:24 +0200617 priv->emio = emio;
Michal Simek185f7d92012-09-13 20:23:34 +0000618
Michal Simek16ce6de2015-10-07 16:42:56 +0200619#ifndef CONFIG_ZYNQ_GEM_INTERFACE
620 priv->interface = PHY_INTERFACE_MODE_MII;
621#else
622 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
623#endif
624
Michal Simek58405372015-01-14 15:44:21 +0100625 sprintf(dev->name, "Gem.%lx", base_addr);
Michal Simek185f7d92012-09-13 20:23:34 +0000626
627 dev->iobase = base_addr;
Michal Simekf2fc2762015-11-30 10:24:15 +0100628 priv->iobase = (struct zynq_gem_regs *)base_addr;
Michal Simek185f7d92012-09-13 20:23:34 +0000629
630 dev->init = zynq_gem_init;
631 dev->halt = zynq_gem_halt;
632 dev->send = zynq_gem_send;
633 dev->recv = zynq_gem_recv;
634 dev->write_hwaddr = zynq_gem_setup_mac;
635
636 eth_register(dev);
637
638 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
639 priv->bus = miiphy_get_dev_by_name(dev->name);
640
641 return 1;
642}
Michal Simekf88a6862014-02-24 11:16:30 +0100643
Masahiro Yamada0f925822015-08-12 07:31:55 +0900644#if CONFIG_IS_ENABLED(OF_CONTROL)
Michal Simekf88a6862014-02-24 11:16:30 +0100645int zynq_gem_of_init(const void *blob)
646{
647 int offset = 0;
648 u32 ret = 0;
649 u32 reg, phy_reg;
650
651 debug("ZYNQ GEM: Initialization\n");
652
653 do {
654 offset = fdt_node_offset_by_compatible(blob, offset,
655 "xlnx,ps7-ethernet-1.00.a");
656 if (offset != -1) {
657 reg = fdtdec_get_addr(blob, offset, "reg");
658 if (reg != FDT_ADDR_T_NONE) {
659 offset = fdtdec_lookup_phandle(blob, offset,
660 "phy-handle");
661 if (offset != -1)
662 phy_reg = fdtdec_get_addr(blob, offset,
663 "reg");
664 else
665 phy_reg = 0;
666
667 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
668 reg, phy_reg);
669
670 ret |= zynq_gem_initialize(NULL, reg,
671 phy_reg, 0);
672
673 } else {
674 debug("ZYNQ GEM: Can't get base address\n");
675 return -1;
676 }
677 }
678 } while (offset != -1);
679
680 return ret;
681}
682#endif