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gerrit.cesnet.cz / github / trini / u-boot / e07a86b5e320113c31221029179db29e392fc090 / . / arch / arm / dts / stm32f746.dtsi
blob: 66360cf21c1ed44ea99d3a2d72d460d52200d4f6 [file] [log] [blame]
Patrick Delaunaye07a86b2019-11-06 16:16:32 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]2/*
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]3 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 *
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]5 */
6
7#include "armv7-m.dtsi"
Patrice Chotardfa87abb2017-07-18 09:29:02 +0200[diff] [blame]8#include <dt-bindings/clock/stm32fx-clock.h>
9#include <dt-bindings/mfd/stm32f7-rcc.h>
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]10
11/ {
Patrick Delaunaye07a86b2019-11-06 16:16:32 +0100[diff] [blame^]12 #address-cells = <1>;
13 #size-cells = <1>;
14
Vikas Manocha84bfdc12017-02-12 10:25:47 -0800[diff] [blame]15 clocks {
16 clk_hse: clk-hse {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
20 };
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]21
22 clk-lse {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 };
27
28 clk-lsi {
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <32000>;
32 };
33
34 clk_i2s_ckin: clk-i2s-ckin {
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <48000000>;
38 };
Patrice Chotard01aabf92019-02-19 00:37:20 +0100[diff] [blame]39 };
Vikas Manocha84bfdc12017-02-12 10:25:47 -0800[diff] [blame]40
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]41 soc {
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]42 timer2: timer@40000000 {
43 compatible = "st,stm32-timer";
44 reg = <0x40000000 0x400>;
45 interrupts = <28>;
46 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
Vikas Manocha84bfdc12017-02-12 10:25:47 -0800[diff] [blame]47 status = "disabled";
Vikas Manocha84bfdc12017-02-12 10:25:47 -0800[diff] [blame]48 };
Patrice Chotardd3651aa2017-11-15 13:14:43 +0100[diff] [blame]49
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]50 timers2: timers@40000000 {
Vikas Manochada4e17f2017-02-12 10:25:50 -0800[diff] [blame]51 #address-cells = <1>;
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]52 #size-cells = <0>;
53 compatible = "st,stm32-timers";
54 reg = <0x40000000 0x400>;
55 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
56 clock-names = "int";
Patrice Chotard77729bd2017-12-12 10:14:59 +0100[diff] [blame]57 status = "disabled";
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]58
59 pwm {
60 compatible = "st,stm32-pwm";
61 status = "disabled";
62 };
63
64 timer@1 {
65 compatible = "st,stm32-timer-trigger";
66 reg = <1>;
67 status = "disabled";
68 };
Patrice Chotard77729bd2017-12-12 10:14:59 +0100[diff] [blame]69 };
70
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]71 timer3: timer@40000400 {
72 compatible = "st,stm32-timer";
73 reg = <0x40000400 0x400>;
74 interrupts = <29>;
75 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
Patrice Chotard77729bd2017-12-12 10:14:59 +0100[diff] [blame]76 status = "disabled";
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]77 };
78
79 timers3: timers@40000400 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 compatible = "st,stm32-timers";
83 reg = <0x40000400 0x400>;
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
85 clock-names = "int";
86 status = "disabled";
87
88 pwm {
89 compatible = "st,stm32-pwm";
90 status = "disabled";
91 };
92
93 timer@2 {
94 compatible = "st,stm32-timer-trigger";
95 reg = <2>;
96 status = "disabled";
97 };
98 };
99
100 timer4: timer@40000800 {
101 compatible = "st,stm32-timer";
102 reg = <0x40000800 0x400>;
103 interrupts = <30>;
104 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
105 status = "disabled";
106 };
107
108 timers4: timers@40000800 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "st,stm32-timers";
112 reg = <0x40000800 0x400>;
113 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
114 clock-names = "int";
115 status = "disabled";
116
117 pwm {
118 compatible = "st,stm32-pwm";
119 status = "disabled";
120 };
121
122 timer@3 {
123 compatible = "st,stm32-timer-trigger";
124 reg = <3>;
125 status = "disabled";
126 };
Vikas Manochada4e17f2017-02-12 10:25:50 -0800[diff] [blame]127 };
Patrice Chotardcd389c02018-02-07 10:44:49 +0100[diff] [blame]128
129 timer5: timer@40000c00 {
130 compatible = "st,stm32-timer";
131 reg = <0x40000c00 0x400>;
132 interrupts = <50>;
133 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
134 };
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]135
136 timers5: timers@40000c00 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "st,stm32-timers";
140 reg = <0x40000C00 0x400>;
141 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
142 clock-names = "int";
143 status = "disabled";
144
145 pwm {
146 compatible = "st,stm32-pwm";
147 status = "disabled";
148 };
149
150 timer@4 {
151 compatible = "st,stm32-timer-trigger";
152 reg = <4>;
153 status = "disabled";
154 };
155 };
156
157 timer6: timer@40001000 {
158 compatible = "st,stm32-timer";
159 reg = <0x40001000 0x400>;
160 interrupts = <54>;
161 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
162 status = "disabled";
163 };
164
165 timers6: timers@40001000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "st,stm32-timers";
169 reg = <0x40001000 0x400>;
170 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
171 clock-names = "int";
172 status = "disabled";
173
174 timer@5 {
175 compatible = "st,stm32-timer-trigger";
176 reg = <5>;
177 status = "disabled";
178 };
179 };
180
181 timer7: timer@40001400 {
182 compatible = "st,stm32-timer";
183 reg = <0x40001400 0x400>;
184 interrupts = <55>;
185 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
186 status = "disabled";
187 };
188
189 timers7: timers@40001400 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "st,stm32-timers";
193 reg = <0x40001400 0x400>;
194 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
195 clock-names = "int";
196 status = "disabled";
197
198 timer@6 {
199 compatible = "st,stm32-timer-trigger";
200 reg = <6>;
201 status = "disabled";
202 };
203 };
204
205 timers12: timers@40001800 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001800 0x400>;
210 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
211 clock-names = "int";
212 status = "disabled";
213
214 pwm {
215 compatible = "st,stm32-pwm";
216 status = "disabled";
217 };
218
219 timer@11 {
220 compatible = "st,stm32-timer-trigger";
221 reg = <11>;
222 status = "disabled";
223 };
224 };
225
226 timers13: timers@40001c00 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "st,stm32-timers";
230 reg = <0x40001C00 0x400>;
231 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
232 clock-names = "int";
233 status = "disabled";
234
235 pwm {
236 compatible = "st,stm32-pwm";
237 status = "disabled";
238 };
239 };
240
241 timers14: timers@40002000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "st,stm32-timers";
245 reg = <0x40002000 0x400>;
246 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
247 clock-names = "int";
248 status = "disabled";
249
250 pwm {
251 compatible = "st,stm32-pwm";
252 status = "disabled";
253 };
254 };
255
256 rtc: rtc@40002800 {
257 compatible = "st,stm32-rtc";
258 reg = <0x40002800 0x400>;
259 clocks = <&rcc 1 CLK_RTC>;
260 clock-names = "ck_rtc";
261 assigned-clocks = <&rcc 1 CLK_RTC>;
262 assigned-clock-parents = <&rcc 1 CLK_LSE>;
263 interrupt-parent = <&exti>;
264 interrupts = <17 1>;
265 interrupt-names = "alarm";
266 st,syscfg = <&pwrcfg 0x00 0x100>;
267 status = "disabled";
268 };
269
270 usart2: serial@40004400 {
271 compatible = "st,stm32f7-uart";
272 reg = <0x40004400 0x400>;
273 interrupts = <38>;
274 clocks = <&rcc 1 CLK_USART2>;
275 status = "disabled";
276 };
277
278 usart3: serial@40004800 {
279 compatible = "st,stm32f7-uart";
280 reg = <0x40004800 0x400>;
281 interrupts = <39>;
282 clocks = <&rcc 1 CLK_USART3>;
283 status = "disabled";
284 };
285
286 usart4: serial@40004c00 {
287 compatible = "st,stm32f7-uart";
288 reg = <0x40004c00 0x400>;
289 interrupts = <52>;
290 clocks = <&rcc 1 CLK_UART4>;
291 status = "disabled";
292 };
293
294 usart5: serial@40005000 {
295 compatible = "st,stm32f7-uart";
296 reg = <0x40005000 0x400>;
297 interrupts = <53>;
298 clocks = <&rcc 1 CLK_UART5>;
299 status = "disabled";
300 };
301
302 i2c1: i2c@40005400 {
303 compatible = "st,stm32f7-i2c";
304 reg = <0x40005400 0x400>;
305 interrupts = <31>,
306 <32>;
307 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
308 clocks = <&rcc 1 CLK_I2C1>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 i2c2: i2c@40005800 {
315 compatible = "st,stm32f7-i2c";
316 reg = <0x40005800 0x400>;
317 interrupts = <33>,
318 <34>;
319 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
320 clocks = <&rcc 1 CLK_I2C2>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 i2c3: i2c@40005C00 {
327 compatible = "st,stm32f7-i2c";
328 reg = <0x40005C00 0x400>;
329 interrupts = <72>,
330 <73>;
331 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
332 clocks = <&rcc 1 CLK_I2C3>;
333 #address-cells = <1>;
334 #size-cells = <0>;
335 status = "disabled";
336 };
337
338 i2c4: i2c@40006000 {
339 compatible = "st,stm32f7-i2c";
340 reg = <0x40006000 0x400>;
341 interrupts = <95>,
342 <96>;
343 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
344 clocks = <&rcc 1 CLK_I2C4>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
350 cec: cec@40006c00 {
351 compatible = "st,stm32-cec";
352 reg = <0x40006C00 0x400>;
353 interrupts = <94>;
354 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
355 clock-names = "cec", "hdmi-cec";
356 status = "disabled";
357 };
358
359 usart7: serial@40007800 {
360 compatible = "st,stm32f7-uart";
361 reg = <0x40007800 0x400>;
362 interrupts = <82>;
363 clocks = <&rcc 1 CLK_UART7>;
364 status = "disabled";
365 };
366
367 usart8: serial@40007c00 {
368 compatible = "st,stm32f7-uart";
369 reg = <0x40007c00 0x400>;
370 interrupts = <83>;
371 clocks = <&rcc 1 CLK_UART8>;
372 status = "disabled";
373 };
374
375 timers1: timers@40010000 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "st,stm32-timers";
379 reg = <0x40010000 0x400>;
380 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
381 clock-names = "int";
382 status = "disabled";
383
384 pwm {
385 compatible = "st,stm32-pwm";
386 status = "disabled";
387 };
388
389 timer@0 {
390 compatible = "st,stm32-timer-trigger";
391 reg = <0>;
392 status = "disabled";
393 };
394 };
395
396 timers8: timers@40010400 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "st,stm32-timers";
400 reg = <0x40010400 0x400>;
401 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
402 clock-names = "int";
403 status = "disabled";
404
405 pwm {
406 compatible = "st,stm32-pwm";
407 status = "disabled";
408 };
409
410 timer@7 {
411 compatible = "st,stm32-timer-trigger";
412 reg = <7>;
413 status = "disabled";
414 };
415 };
416
417 usart1: serial@40011000 {
418 compatible = "st,stm32f7-uart";
419 reg = <0x40011000 0x400>;
420 interrupts = <37>;
421 clocks = <&rcc 1 CLK_USART1>;
422 status = "disabled";
423 };
424
425 usart6: serial@40011400 {
426 compatible = "st,stm32f7-uart";
427 reg = <0x40011400 0x400>;
428 interrupts = <71>;
429 clocks = <&rcc 1 CLK_USART6>;
430 status = "disabled";
431 };
432
433 sdio2: sdio2@40011c00 {
434 compatible = "arm,pl180", "arm,primecell";
435 arm,primecell-periphid = <0x00880180>;
436 reg = <0x40011c00 0x400>;
437 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
438 clock-names = "apb_pclk";
439 interrupts = <103>;
440 max-frequency = <48000000>;
441 status = "disabled";
442 };
443
444 sdio1: sdio1@40012c00 {
445 compatible = "arm,pl180", "arm,primecell";
446 arm,primecell-periphid = <0x00880180>;
447 reg = <0x40012c00 0x400>;
448 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
449 clock-names = "apb_pclk";
450 interrupts = <49>;
451 max-frequency = <48000000>;
452 status = "disabled";
453 };
454
455 syscfg: system-config@40013800 {
456 compatible = "syscon";
457 reg = <0x40013800 0x400>;
458 };
459
460 exti: interrupt-controller@40013c00 {
461 compatible = "st,stm32-exti";
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 reg = <0x40013C00 0x400>;
465 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
466 };
467
468 timers9: timers@40014000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "st,stm32-timers";
472 reg = <0x40014000 0x400>;
473 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
474 clock-names = "int";
475 status = "disabled";
476
477 pwm {
478 compatible = "st,stm32-pwm";
479 status = "disabled";
480 };
481
482 timer@8 {
483 compatible = "st,stm32-timer-trigger";
484 reg = <8>;
485 status = "disabled";
486 };
487 };
488
489 timers10: timers@40014400 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "st,stm32-timers";
493 reg = <0x40014400 0x400>;
494 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
495 clock-names = "int";
496 status = "disabled";
497
498 pwm {
499 compatible = "st,stm32-pwm";
500 status = "disabled";
501 };
502 };
503
504 timers11: timers@40014800 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "st,stm32-timers";
508 reg = <0x40014800 0x400>;
509 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
510 clock-names = "int";
511 status = "disabled";
512
513 pwm {
514 compatible = "st,stm32-pwm";
515 status = "disabled";
516 };
517 };
518
519 pwrcfg: power-config@40007000 {
520 compatible = "syscon";
521 reg = <0x40007000 0x400>;
522 };
523
524 crc: crc@40023000 {
525 compatible = "st,stm32f7-crc";
526 reg = <0x40023000 0x400>;
527 clocks = <&rcc 0 12>;
528 status = "disabled";
529 };
530
531 rcc: rcc@40023800 {
532 #reset-cells = <1>;
533 #clock-cells = <2>;
534 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
535 reg = <0x40023800 0x400>;
536 clocks = <&clk_hse>, <&clk_i2s_ckin>;
537 st,syscfg = <&pwrcfg>;
538 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
539 assigned-clock-rates = <1000000>;
540 };
541
542 dma1: dma@40026000 {
543 compatible = "st,stm32-dma";
544 reg = <0x40026000 0x400>;
545 interrupts = <11>,
546 <12>,
547 <13>,
548 <14>,
549 <15>,
550 <16>,
551 <17>,
552 <47>;
553 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
554 #dma-cells = <4>;
555 status = "disabled";
556 };
557
558 dma2: dma@40026400 {
559 compatible = "st,stm32-dma";
560 reg = <0x40026400 0x400>;
561 interrupts = <56>,
562 <57>,
563 <58>,
564 <59>,
565 <60>,
566 <68>,
567 <69>,
568 <70>;
569 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
570 #dma-cells = <4>;
571 st,mem2mem;
572 status = "disabled";
573 };
574
575 usbotg_hs: usb@40040000 {
576 compatible = "st,stm32f7-hsotg";
577 reg = <0x40040000 0x40000>;
578 interrupts = <77>;
579 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
580 clock-names = "otg";
581 g-rx-fifo-size = <256>;
582 g-np-tx-fifo-size = <32>;
583 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
584 status = "disabled";
585 };
586
587 usbotg_fs: usb@50000000 {
588 compatible = "st,stm32f4x9-fsotg";
589 reg = <0x50000000 0x40000>;
590 interrupts = <67>;
591 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
592 clock-names = "otg";
593 status = "disabled";
594 };
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]595 };
596};
597
598&systick {
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100[diff] [blame]599 clocks = <&rcc 1 0>;
Michael Kurzb1a8de72017-01-22 16:04:23 +0100[diff] [blame]600 status = "okay";
601};