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Stefan Roese8a316c92005-08-01 16:49:12 +02001/*
Stefan Roesea471db02007-06-01 15:19:29 +02002 * (C) Copyright 2005-2007
Stefan Roese8a316c92005-08-01 16:49:12 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkf901a832005-08-06 01:42:58 +020015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stefan Roese8a316c92005-08-01 16:49:12 +020016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
Stefan Roese09887762010-09-16 14:30:37 +020026#include <asm/ppc4xx-gpio.h>
Stefan Roese8a316c92005-08-01 16:49:12 +020027#include <spd_sdram.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020028#include <asm/ppc440.h>
Stefan Roese17f50f222005-08-04 17:09:16 +020029#include "bamboo.h"
30
31void ext_bus_cntlr_init(void);
32void configure_ppc440ep_pins(void);
Stefan Roesec57c7982005-08-11 17:56:56 +020033int is_nand_selected(void);
Stefan Roese17f50f222005-08-04 17:09:16 +020034
Eugene OBriend2f68002007-07-31 10:24:56 +020035#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36/*************************************************************************
37 *
38 * Bamboo has one bank onboard sdram (plus DIMM)
39 *
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
46 *
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
50 *
51 * Assumes: 64 MB, ECC, non-registered
52 * PLB @ 133 MHz
53 *
54 ************************************************************************/
55const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
58 0x07, /* DDR ram */
59#ifdef CONFIG_DDR_ECC
60 0x0C, /* num Row Addr: 12 */
61#else
62 0x0D, /* num Row Addr: 13 */
63#endif
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
68 0x04, /* 2.5 Volt */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
Eugene O'Brien9f798762007-10-23 08:29:10 +020070 0x00, /* SDRAM Access from clock */
Eugene OBriend2f68002007-07-31 10:24:56 +020071#ifdef CONFIG_DDR_ECC
72 0x02, /* ECC ON : 02 OFF : 00 */
73#else
74 0x00, /* ECC ON : 02 OFF : 00 */
75#endif
Eugene O'Brien9f798762007-10-23 08:29:10 +020076 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
Eugene OBriend2f68002007-07-31 10:24:56 +020077 0,
78 0,
79 0x01, /* wcsbc = 1 */
80 0,
81 0,
82 0x0C, /* casBit (2,2.5) */
83 0,
84 0,
85 0x00, /* not registered: 0 registered : 0x02*/
86 0,
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
88 0,
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
90 0,
91 0x50, /* tRpNs = 20 ns */
92 0,
93 0x50, /* tRcdNs = 20 ns */
94 45, /* tRasNs */
95#ifdef CONFIG_DDR_ECC
96 0x08, /* bankSizeID: 32MB */
97#else
98 0x10, /* bankSizeID: 64MB */
99#endif
100 0,
101 0,
102 0,
103 0,
104 0,
105 0,
106 0,
107 0,
108 0,
109 0,
110 0,
111 0,
112 0,
113 0,
114 0,
115 0,
116 0,
117 0,
118 0,
119 0,
120 0,
121 0,
122 0,
123 0,
124 0,
125 0,
126 0,
127 0,
128 0,
129 0,
130 0,
131 0,
132 0,
133 0,
134 0,
135 0,
136 0,
137 0,
138 0,
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0,
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0,
180 0,
181 0,
182 0,
183 0,
184 0,
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191 0,
192 0,
193 0,
194 0,
195 0
196};
197#endif
Stefan Roesefd49bf02005-11-15 16:04:58 +0100198
Stefan Roese17f50f222005-08-04 17:09:16 +0200199#if 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200200{ /* GPIO Alternate1 Alternate2 Alternate3 */
201 {
202 /* GPIO Core 0 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
235 },
236 {
237 /* GPIO Core 1 */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
270 }
Stefan Roese17f50f222005-08-04 17:09:16 +0200271};
272#endif
273
274/*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
Wolfgang Denkf901a832005-08-06 01:42:58 +0200276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
Stefan Roese17f50f222005-08-04 17:09:16 +0200278 +----------------------------------------------------------------------------*/
279/* Small Flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200280#define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200291 EBC0_BNAP_PEN_DISABLED
292
Wolfgang Denkf901a832005-08-06 01:42:58 +0200293#define EBC0_BNCR_SMALL_FLASH_CS0 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
295 EBC0_BNCR_BS_1MB | \
296 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200297 EBC0_BNCR_BW_8BIT
298
Wolfgang Denkf901a832005-08-06 01:42:58 +0200299#define EBC0_BNCR_SMALL_FLASH_CS4 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
301 EBC0_BNCR_BS_1MB | \
302 EBC0_BNCR_BU_RW | \
Stefan Roesec57c7982005-08-11 17:56:56 +0200303 EBC0_BNCR_BW_8BIT
Stefan Roese17f50f222005-08-04 17:09:16 +0200304
305/* Large Flash or SRAM */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200306#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
315 EBC0_BNAP_BEM_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200316 EBC0_BNAP_PEN_DISABLED
317
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200318#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
320 EBC0_BNCR_BS_8MB | \
321 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200322 EBC0_BNCR_BW_16BIT
323
324
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
327 EBC0_BNCR_BS_8MB | \
328 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200329 EBC0_BNCR_BW_16BIT
330
331/* NVRAM - FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200332#define EBC0_BNAP_NVRAM_FPGA \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200343 EBC0_BNAP_PEN_DISABLED
344
Wolfgang Denkf901a832005-08-06 01:42:58 +0200345#define EBC0_BNCR_NVRAM_FPGA_CS5 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
347 EBC0_BNCR_BS_1MB | \
348 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200349 EBC0_BNCR_BW_8BIT
350
351/* Nand Flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200352#define EBC0_BNAP_NAND_FLASH \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
362 EBC0_BNAP_BEM_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200363 EBC0_BNAP_PEN_DISABLED
364
365
Wolfgang Denkf901a832005-08-06 01:42:58 +0200366#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
Stefan Roese17f50f222005-08-04 17:09:16 +0200367
368/* NAND0 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200369#define EBC0_BNCR_NAND_FLASH_CS1 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
371 EBC0_BNCR_BS_1MB | \
372 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200373 EBC0_BNCR_BW_32BIT
374/* NAND1 - Bank2 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200375#define EBC0_BNCR_NAND_FLASH_CS2 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
377 EBC0_BNCR_BS_1MB | \
378 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200379 EBC0_BNCR_BW_32BIT
380
381/* NAND1 - Bank3 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200382#define EBC0_BNCR_NAND_FLASH_CS3 \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
384 EBC0_BNCR_BS_1MB | \
385 EBC0_BNCR_BU_RW | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200386 EBC0_BNCR_BW_32BIT
Stefan Roese8a316c92005-08-01 16:49:12 +0200387
388int board_early_init_f(void)
389{
Stefan Roese17f50f222005-08-04 17:09:16 +0200390 ext_bus_cntlr_init();
Stefan Roese8a316c92005-08-01 16:49:12 +0200391
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +0200395 mtdcr(UIC0SR, 0xffffffff); /* clear all */
396 mtdcr(UIC0ER, 0x00000000); /* disable all */
397 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
399 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
400 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Stefan Roese8a316c92005-08-01 16:49:12 +0200402
Stefan Roese952e7762009-09-24 09:55:50 +0200403 mtdcr(UIC1SR, 0xffffffff); /* clear all */
404 mtdcr(UIC1ER, 0x00000000); /* disable all */
405 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
406 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
408 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Stefan Roese8a316c92005-08-01 16:49:12 +0200410
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +0200414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
Stefan Roese8a316c92005-08-01 16:49:12 +0200424
Stefan Roese17f50f222005-08-04 17:09:16 +0200425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
Stefan Roese8a316c92005-08-01 16:49:12 +0200435
Stefan Roese17f50f222005-08-04 17:09:16 +0200436 configure_ppc440ep_pins();
Stefan Roese8a316c92005-08-01 16:49:12 +0200437
438 return 0;
439}
440
441int checkboard(void)
442{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100443 char *s = getenv("serial#");
Stefan Roese8a316c92005-08-01 16:49:12 +0200444
445 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
446 if (s != NULL) {
447 puts(", serial# ");
448 puts(s);
449 }
450 putc('\n');
451
Stefan Roese8a316c92005-08-01 16:49:12 +0200452 return (0);
453}
454
Stefan Roese8a316c92005-08-01 16:49:12 +0200455
Becky Bruce9973e3c2008-06-09 16:03:40 -0500456phys_size_t initdram (int board_type)
Stefan Roese8a316c92005-08-01 16:49:12 +0200457{
Stefan Roesea471db02007-06-01 15:19:29 +0200458#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
459 long dram_size;
Stefan Roese17f50f222005-08-04 17:09:16 +0200460
Marian Balakowiczd19206b2006-07-04 01:27:46 +0200461 dram_size = spd_sdram();
Stefan Roese17f50f222005-08-04 17:09:16 +0200462
463 return dram_size;
Stefan Roesea471db02007-06-01 15:19:29 +0200464#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465 return CONFIG_SYS_MBYTES_SDRAM << 20;
Stefan Roesea471db02007-06-01 15:19:29 +0200466#endif
Stefan Roese8a316c92005-08-01 16:49:12 +0200467}
468
Stefan Roese17f50f222005-08-04 17:09:16 +0200469/*----------------------------------------------------------------------------+
470 | is_powerpc440ep_pass1.
471 +----------------------------------------------------------------------------*/
472int is_powerpc440ep_pass1(void)
473{
474 unsigned long pvr;
475
476 pvr = get_pvr();
477
478 if (pvr == PVR_POWERPC_440EP_PASS1)
479 return TRUE;
480 else if (pvr == PVR_POWERPC_440EP_PASS2)
481 return FALSE;
482 else {
483 printf("brdutil error 3\n");
484 for (;;)
485 ;
486 }
487
488 return(FALSE);
489}
490
491/*----------------------------------------------------------------------------+
492 | is_nand_selected.
493 +----------------------------------------------------------------------------*/
494int is_nand_selected(void)
495{
Stefan Roesec57c7982005-08-11 17:56:56 +0200496#ifdef CONFIG_BAMBOO_NAND
497 return TRUE;
498#else
499 return FALSE;
500#endif
Stefan Roese17f50f222005-08-04 17:09:16 +0200501}
502
503/*----------------------------------------------------------------------------+
504 | config_on_ebc_cs4_is_small_flash => from EPLD
505 +----------------------------------------------------------------------------*/
506unsigned char config_on_ebc_cs4_is_small_flash(void)
507{
508 /* Not implemented yet => returns constant value */
509 return TRUE;
510}
511
512/*----------------------------------------------------------------------------+
513 | Ext_bus_cntlr_init.
514 | Initialize the external bus controller
515 +----------------------------------------------------------------------------*/
516void ext_bus_cntlr_init(void)
517{
518 unsigned long sdr0_pstrp0, sdr0_sdstp1;
519 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
Wolfgang Denkf901a832005-08-06 01:42:58 +0200520 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
Stefan Roese17f50f222005-08-04 17:09:16 +0200521 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
522 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
523 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
524 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
525 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
526
527
528 /*-------------------------------------------------------------------------+
529 |
530 | PART 1 : Initialize EBC Bank 5
531 | ==============================
532 | Bank5 is always associated to the NVRAM/EPLD.
533 | It has to be initialized prior to other banks settings computation since
534 | some board registers values may be needed
535 |
536 +-------------------------------------------------------------------------*/
537 /* NVRAM - FPGA */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200538 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
539 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
Stefan Roese17f50f222005-08-04 17:09:16 +0200540
541 /*-------------------------------------------------------------------------+
542 |
543 | PART 2 : Determine which boot device was selected
544 | =========================================
545 |
546 | Read Pin Strap Register in PPC440EP
547 | In case of boot from IIC, read Serial Device Strap Register1
548 |
549 | Result can either be :
550 | - Boot from EBC 8bits => SMALL FLASH
551 | - Boot from EBC 16bits => Large Flash or SRAM
552 | - Boot from NAND Flash
553 | - Boot from PCI
554 |
555 +-------------------------------------------------------------------------*/
556 /* Read Pin Strap Register in PPC440EP */
557 mfsdr(sdr_pstrp0, sdr0_pstrp0);
558 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
559
560 /*-------------------------------------------------------------------------+
561 | PPC440EP Pass1
562 +-------------------------------------------------------------------------*/
563 if (is_powerpc440ep_pass1() == TRUE) {
564 switch(bootstrap_settings) {
565 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
566 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
567 /* Boot from Small Flash */
568 computed_boot_device = BOOT_FROM_SMALL_FLASH;
569 break;
570 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
571 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
572 /* Boot from PCI */
573 computed_boot_device = BOOT_FROM_PCI;
574 break;
575
576 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
577 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
578 /* Boot from Nand Flash */
579 computed_boot_device = BOOT_FROM_NAND_FLASH0;
580 break;
581
582 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
583 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
584 /* Boot from Small Flash */
585 computed_boot_device = BOOT_FROM_SMALL_FLASH;
586 break;
587
588 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
589 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
590 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
591 /* Read Serial Device Strap Register1 in PPC440EP */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200592 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
Wolfgang Denkf901a832005-08-06 01:42:58 +0200593 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
594 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
Stefan Roese17f50f222005-08-04 17:09:16 +0200595
596 switch(boot_selection) {
597 case SDR0_SDSTP1_BOOT_SEL_EBC:
598 switch(ebc_boot_size) {
599 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
600 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
601 break;
602 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
603 computed_boot_device = BOOT_FROM_SMALL_FLASH;
604 break;
605 }
606 break;
607
608 case SDR0_SDSTP1_BOOT_SEL_PCI:
609 computed_boot_device = BOOT_FROM_PCI;
610 break;
611
612 case SDR0_SDSTP1_BOOT_SEL_NDFC:
613 computed_boot_device = BOOT_FROM_NAND_FLASH0;
614 break;
615 }
616 break;
617 }
618 }
619
620 /*-------------------------------------------------------------------------+
621 | PPC440EP Pass2
622 +-------------------------------------------------------------------------*/
623 else {
624 switch(bootstrap_settings) {
625 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
626 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
627 /* Boot from Small Flash */
628 computed_boot_device = BOOT_FROM_SMALL_FLASH;
629 break;
630 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
631 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
632 /* Boot from PCI */
633 computed_boot_device = BOOT_FROM_PCI;
634 break;
635
636 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
637 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
638 /* Boot from Nand Flash */
639 computed_boot_device = BOOT_FROM_NAND_FLASH0;
640 break;
641
642 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
643 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
644 /* Boot from Large Flash or SRAM */
645 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
646 break;
647
648 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
649 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
650 /* Boot from Large Flash or SRAM */
651 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
652 break;
653
654 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
655 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
656 /* Boot from PCI */
657 computed_boot_device = BOOT_FROM_PCI;
658 break;
659
660 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
661 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
662 /* Default Strap Settings 5-7 */
663 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
664 /* Read Serial Device Strap Register1 in PPC440EP */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200665 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
Wolfgang Denkf901a832005-08-06 01:42:58 +0200666 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
667 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
Stefan Roese17f50f222005-08-04 17:09:16 +0200668
669 switch(boot_selection) {
670 case SDR0_SDSTP1_BOOT_SEL_EBC:
671 switch(ebc_boot_size) {
672 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
673 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
674 break;
675 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
676 computed_boot_device = BOOT_FROM_SMALL_FLASH;
677 break;
678 }
679 break;
680
681 case SDR0_SDSTP1_BOOT_SEL_PCI:
682 computed_boot_device = BOOT_FROM_PCI;
683 break;
684
685 case SDR0_SDSTP1_BOOT_SEL_NDFC:
686 computed_boot_device = BOOT_FROM_NAND_FLASH0;
687 break;
688 }
689 break;
690 }
691 }
692
693 /*-------------------------------------------------------------------------+
694 |
695 | PART 3 : Compute EBC settings depending on selected boot device
696 | ====== ======================================================
697 |
698 | Resulting EBC init will be among following configurations :
699 |
700 | - Boot from EBC 8bits => boot from SMALL FLASH selected
Wolfgang Denkf901a832005-08-06 01:42:58 +0200701 | EBC-CS0 = Small Flash
702 | EBC-CS1,2,3 = NAND Flash or
703 | Exp.Slot depending on Soft Config
704 | EBC-CS4 = SRAM/Large Flash or
705 | Large Flash/SRAM depending on jumpers
706 | EBC-CS5 = NVRAM / EPLD
Stefan Roese17f50f222005-08-04 17:09:16 +0200707 |
708 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
Wolfgang Denkf901a832005-08-06 01:42:58 +0200709 | EBC-CS0 = SRAM/Large Flash or
710 | Large Flash/SRAM depending on jumpers
711 | EBC-CS1,2,3 = NAND Flash or
712 | Exp.Slot depending on Software Configuration
713 | EBC-CS4 = Small Flash
714 | EBC-CS5 = NVRAM / EPLD
Stefan Roese17f50f222005-08-04 17:09:16 +0200715 |
716 | - Boot from NAND Flash
Wolfgang Denkf901a832005-08-06 01:42:58 +0200717 | EBC-CS0 = NAND Flash0
718 | EBC-CS1,2,3 = NAND Flash1
719 | EBC-CS4 = SRAM/Large Flash or
720 | Large Flash/SRAM depending on jumpers
721 | EBC-CS5 = NVRAM / EPLD
Stefan Roese17f50f222005-08-04 17:09:16 +0200722 |
723 | - Boot from PCI
Wolfgang Denkf901a832005-08-06 01:42:58 +0200724 | EBC-CS0 = ...
725 | EBC-CS1,2,3 = NAND Flash or
726 | Exp.Slot depending on Software Configuration
727 | EBC-CS4 = SRAM/Large Flash or
728 | Large Flash/SRAM or
729 | Small Flash depending on jumpers
730 | EBC-CS5 = NVRAM / EPLD
Stefan Roese17f50f222005-08-04 17:09:16 +0200731 |
732 +-------------------------------------------------------------------------*/
733
734 switch(computed_boot_device) {
735 /*------------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200736 case BOOT_FROM_SMALL_FLASH:
Stefan Roese17f50f222005-08-04 17:09:16 +0200737 /*------------------------------------------------------------------------- */
738 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
739 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
740 if ((is_nand_selected()) == TRUE) {
741 /* NAND Flash */
742 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
743 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
Stefan Roesec57c7982005-08-11 17:56:56 +0200744 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
745 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
Stefan Roese17f50f222005-08-04 17:09:16 +0200746 ebc0_cs3_bnap_value = 0;
747 ebc0_cs3_bncr_value = 0;
748 } else {
749 /* Expansion Slot */
750 ebc0_cs1_bnap_value = 0;
751 ebc0_cs1_bncr_value = 0;
752 ebc0_cs2_bnap_value = 0;
753 ebc0_cs2_bncr_value = 0;
754 ebc0_cs3_bnap_value = 0;
755 ebc0_cs3_bncr_value = 0;
756 }
757 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
758 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
759
760 break;
761
762 /*------------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200763 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
Stefan Roese17f50f222005-08-04 17:09:16 +0200764 /*------------------------------------------------------------------------- */
765 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
766 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
767 if ((is_nand_selected()) == TRUE) {
768 /* NAND Flash */
769 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
770 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
771 ebc0_cs2_bnap_value = 0;
772 ebc0_cs2_bncr_value = 0;
773 ebc0_cs3_bnap_value = 0;
774 ebc0_cs3_bncr_value = 0;
775 } else {
776 /* Expansion Slot */
777 ebc0_cs1_bnap_value = 0;
778 ebc0_cs1_bncr_value = 0;
779 ebc0_cs2_bnap_value = 0;
780 ebc0_cs2_bncr_value = 0;
781 ebc0_cs3_bnap_value = 0;
782 ebc0_cs3_bncr_value = 0;
783 }
784 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
785 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
786
787 break;
788
789 /*------------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200790 case BOOT_FROM_NAND_FLASH0:
Stefan Roese17f50f222005-08-04 17:09:16 +0200791 /*------------------------------------------------------------------------- */
Stefan Roesea471db02007-06-01 15:19:29 +0200792 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
793 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
Stefan Roese17f50f222005-08-04 17:09:16 +0200794
Stefan Roesea471db02007-06-01 15:19:29 +0200795 ebc0_cs1_bnap_value = 0;
796 ebc0_cs1_bncr_value = 0;
Stefan Roese17f50f222005-08-04 17:09:16 +0200797 ebc0_cs2_bnap_value = 0;
798 ebc0_cs2_bncr_value = 0;
799 ebc0_cs3_bnap_value = 0;
800 ebc0_cs3_bncr_value = 0;
801
802 /* Large Flash or SRAM */
803 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
804 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
805
806 break;
807
808 /*------------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200809 case BOOT_FROM_PCI:
Stefan Roese17f50f222005-08-04 17:09:16 +0200810 /*------------------------------------------------------------------------- */
811 ebc0_cs0_bnap_value = 0;
812 ebc0_cs0_bncr_value = 0;
813
814 if ((is_nand_selected()) == TRUE) {
815 /* NAND Flash */
816 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
817 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
818 ebc0_cs2_bnap_value = 0;
819 ebc0_cs2_bncr_value = 0;
820 ebc0_cs3_bnap_value = 0;
821 ebc0_cs3_bncr_value = 0;
822 } else {
823 /* Expansion Slot */
824 ebc0_cs1_bnap_value = 0;
825 ebc0_cs1_bncr_value = 0;
826 ebc0_cs2_bnap_value = 0;
827 ebc0_cs2_bncr_value = 0;
828 ebc0_cs3_bnap_value = 0;
829 ebc0_cs3_bncr_value = 0;
830 }
831
832 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
833 /* Small Flash */
834 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
835 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
836 } else {
837 /* Large Flash or SRAM */
838 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
839 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
840 }
841
842 break;
843
844 /*------------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200845 case BOOT_DEVICE_UNKNOWN:
Stefan Roese17f50f222005-08-04 17:09:16 +0200846 /*------------------------------------------------------------------------- */
847 /* Error */
848 break;
849
850 }
851
852
853 /*-------------------------------------------------------------------------+
854 | Initialize EBC CONFIG
855 +-------------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200856 mtdcr(EBC0_CFGADDR, EBC0_CFG);
857 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
Wolfgang Denkf901a832005-08-06 01:42:58 +0200858 EBC0_CFG_PTD_ENABLED |
859 EBC0_CFG_RTC_2048PERCLK |
860 EBC0_CFG_EMPL_LOW |
861 EBC0_CFG_EMPH_LOW |
862 EBC0_CFG_CSTC_DRIVEN |
863 EBC0_CFG_BPF_ONEDW |
864 EBC0_CFG_EMS_8BIT |
865 EBC0_CFG_PME_DISABLED |
866 EBC0_CFG_PMT_ENCODE(0) );
Stefan Roese17f50f222005-08-04 17:09:16 +0200867
868 /*-------------------------------------------------------------------------+
869 | Initialize EBC Bank 0-4
870 +-------------------------------------------------------------------------*/
871 /* EBC Bank0 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200872 mtebc(PB0AP, ebc0_cs0_bnap_value);
873 mtebc(PB0CR, ebc0_cs0_bncr_value);
Stefan Roese17f50f222005-08-04 17:09:16 +0200874 /* EBC Bank1 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200875 mtebc(PB1AP, ebc0_cs1_bnap_value);
876 mtebc(PB1CR, ebc0_cs1_bncr_value);
Stefan Roese17f50f222005-08-04 17:09:16 +0200877 /* EBC Bank2 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200878 mtebc(PB2AP, ebc0_cs2_bnap_value);
879 mtebc(PB2CR, ebc0_cs2_bncr_value);
Stefan Roese17f50f222005-08-04 17:09:16 +0200880 /* EBC Bank3 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200881 mtebc(PB3AP, ebc0_cs3_bnap_value);
882 mtebc(PB3CR, ebc0_cs3_bncr_value);
Stefan Roese17f50f222005-08-04 17:09:16 +0200883 /* EBC Bank4 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200884 mtebc(PB4AP, ebc0_cs4_bnap_value);
885 mtebc(PB4CR, ebc0_cs4_bncr_value);
Stefan Roese17f50f222005-08-04 17:09:16 +0200886
887 return;
888}
889
890
891/*----------------------------------------------------------------------------+
892 | get_uart_configuration.
893 +----------------------------------------------------------------------------*/
894uart_config_nb_t get_uart_configuration(void)
895{
Stefan Roesec57c7982005-08-11 17:56:56 +0200896 return (L4);
Stefan Roese17f50f222005-08-04 17:09:16 +0200897}
898
899/*----------------------------------------------------------------------------+
900 | set_phy_configuration_through_fpga => to EPLD
901 +----------------------------------------------------------------------------*/
902void set_phy_configuration_through_fpga(zmii_config_t config)
Stefan Roese8a316c92005-08-01 16:49:12 +0200903{
904
Stefan Roese17f50f222005-08-04 17:09:16 +0200905 unsigned long fpga_selection_reg;
906
907 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
908
909 switch(config)
910 {
Wolfgang Denkf901a832005-08-06 01:42:58 +0200911 case ZMII_CONFIGURATION_IS_MII:
Stefan Roese17f50f222005-08-04 17:09:16 +0200912 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
913 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +0200914 case ZMII_CONFIGURATION_IS_RMII:
Stefan Roese17f50f222005-08-04 17:09:16 +0200915 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
916 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +0200917 case ZMII_CONFIGURATION_IS_SMII:
Stefan Roese17f50f222005-08-04 17:09:16 +0200918 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
919 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +0200920 case ZMII_CONFIGURATION_UNKNOWN:
921 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200922 break;
923 }
924 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
925
Stefan Roese8a316c92005-08-01 16:49:12 +0200926}
Stefan Roese17f50f222005-08-04 17:09:16 +0200927
928/*----------------------------------------------------------------------------+
929 | scp_selection_in_fpga.
930 +----------------------------------------------------------------------------*/
931void scp_selection_in_fpga(void)
932{
933 unsigned long fpga_selection_2_reg;
934
935 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
936 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
937 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
938}
939
940/*----------------------------------------------------------------------------+
941 | iic1_selection_in_fpga.
942 +----------------------------------------------------------------------------*/
943void iic1_selection_in_fpga(void)
944{
945 unsigned long fpga_selection_2_reg;
946
947 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
948 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
949 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
950}
951
952/*----------------------------------------------------------------------------+
953 | dma_a_b_selection_in_fpga.
954 +----------------------------------------------------------------------------*/
955void dma_a_b_selection_in_fpga(void)
956{
957 unsigned long fpga_selection_2_reg;
958
959 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
960 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
961}
962
963/*----------------------------------------------------------------------------+
964 | dma_a_b_unselect_in_fpga.
965 +----------------------------------------------------------------------------*/
966void dma_a_b_unselect_in_fpga(void)
967{
968 unsigned long fpga_selection_2_reg;
969
970 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
971 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
972}
973
974/*----------------------------------------------------------------------------+
975 | dma_c_d_selection_in_fpga.
976 +----------------------------------------------------------------------------*/
977void dma_c_d_selection_in_fpga(void)
978{
979 unsigned long fpga_selection_2_reg;
980
981 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
982 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
983}
984
985/*----------------------------------------------------------------------------+
986 | dma_c_d_unselect_in_fpga.
987 +----------------------------------------------------------------------------*/
988void dma_c_d_unselect_in_fpga(void)
989{
990 unsigned long fpga_selection_2_reg;
991
992 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
993 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
994}
995
996/*----------------------------------------------------------------------------+
997 | usb2_device_selection_in_fpga.
998 +----------------------------------------------------------------------------*/
999void usb2_device_selection_in_fpga(void)
1000{
1001 unsigned long fpga_selection_1_reg;
1002
1003 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1004 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1005}
1006
1007/*----------------------------------------------------------------------------+
1008 | usb2_device_reset_through_fpga.
1009 +----------------------------------------------------------------------------*/
1010void usb2_device_reset_through_fpga(void)
1011{
1012 /* Perform soft Reset pulse */
1013 unsigned long fpga_reset_reg;
1014 int i;
1015
1016 fpga_reset_reg = in8(FPGA_RESET_REG);
1017 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1018 for (i=0; i<500; i++)
1019 udelay(1000);
1020 out8(FPGA_RESET_REG,fpga_reset_reg);
1021}
1022
1023/*----------------------------------------------------------------------------+
1024 | usb2_host_selection_in_fpga.
1025 +----------------------------------------------------------------------------*/
1026void usb2_host_selection_in_fpga(void)
1027{
1028 unsigned long fpga_selection_1_reg;
1029
1030 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1031 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1032}
1033
1034/*----------------------------------------------------------------------------+
1035 | ndfc_selection_in_fpga.
1036 +----------------------------------------------------------------------------*/
1037void ndfc_selection_in_fpga(void)
1038{
1039 unsigned long fpga_selection_1_reg;
1040
1041 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1042 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
Stefan Roesec57c7982005-08-11 17:56:56 +02001043 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
Stefan Roese17f50f222005-08-04 17:09:16 +02001044 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1045}
1046
1047/*----------------------------------------------------------------------------+
1048 | uart_selection_in_fpga.
1049 +----------------------------------------------------------------------------*/
1050void uart_selection_in_fpga(uart_config_nb_t uart_config)
1051{
1052 /* FPGA register */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001053 unsigned char fpga_selection_3_reg;
Stefan Roese17f50f222005-08-04 17:09:16 +02001054
1055 /* Read FPGA Reagister */
1056 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1057
1058 switch (uart_config)
1059 {
1060 case L1:
1061 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001062 /* L1 configuration: UART0 = 8 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001063 /* ----------------------------------------------------------------------- */
1064 /* Configure FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001065 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1066 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001067 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1068
1069 break;
1070
1071 case L2:
1072 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001073 /* L2 configuration: UART0 = 4 pins */
1074 /* UART1 = 4 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001075 /* ----------------------------------------------------------------------- */
1076 /* Configure FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001077 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1078 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
Stefan Roese17f50f222005-08-04 17:09:16 +02001079 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1080
1081 break;
1082
1083 case L3:
1084 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001085 /* L3 configuration: UART0 = 4 pins */
1086 /* UART1 = 2 pins */
1087 /* UART2 = 2 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001088 /* ----------------------------------------------------------------------- */
1089 /* Configure FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001090 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1091 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
Stefan Roese17f50f222005-08-04 17:09:16 +02001092 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1093 break;
1094
1095 case L4:
1096 /* Configure FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001097 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1098 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
Stefan Roese17f50f222005-08-04 17:09:16 +02001099 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1100
1101 break;
1102
1103 default:
1104 /* Unsupported UART configuration number */
1105 for (;;)
1106 ;
1107 break;
1108
1109 }
1110}
1111
1112
1113/*----------------------------------------------------------------------------+
1114 | init_default_gpio
1115 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001116void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001117{
1118 int i;
1119
1120 /* Init GPIO0 */
1121 for(i=0; i<GPIO_MAX; i++)
1122 {
Wolfgang Denkf901a832005-08-06 01:42:58 +02001123 gpio_tab[GPIO0][i].add = GPIO0_BASE;
Stefan Roese17f50f222005-08-04 17:09:16 +02001124 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1125 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1126 }
1127
1128 /* Init GPIO1 */
1129 for(i=0; i<GPIO_MAX; i++)
1130 {
Wolfgang Denkf901a832005-08-06 01:42:58 +02001131 gpio_tab[GPIO1][i].add = GPIO1_BASE;
Stefan Roese17f50f222005-08-04 17:09:16 +02001132 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1133 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1134 }
1135
1136 /* EBC_CS_N(5) - GPIO0_10 */
1137 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1138 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1139
1140 /* EBC_CS_N(4) - GPIO0_9 */
1141 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1142 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1143}
1144
1145/*----------------------------------------------------------------------------+
1146 | update_uart_ios
1147 +------------------------------------------------------------------------------
1148 |
1149 | Set UART Configuration in PowerPC440EP
1150 |
1151 | +---------------------------------------------------------------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001152 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1153 | | Number | Port Name | available | naming | CORE |
Stefan Roese17f50f222005-08-04 17:09:16 +02001154 | +-----------------+---------------+------------+--------+-------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001155 | | L1 | Port_A | 8 | UART | UART core 0 |
Stefan Roese17f50f222005-08-04 17:09:16 +02001156 | +-----------------+---------------+------------+--------+-------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001157 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1158 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
Stefan Roese17f50f222005-08-04 17:09:16 +02001159 | +-----------------+---------------+------------+--------+-------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001160 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1161 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1162 | | | Port_C | 2 | UART3 | UART core 2 |
Stefan Roese17f50f222005-08-04 17:09:16 +02001163 | +-----------------+---------------+------------+--------+-------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001164 | | | Port_A | 2 | UART1 | UART core 0 |
1165 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1166 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1167 | | | Port_D | 2 | UART4 | UART core 3 |
Stefan Roese17f50f222005-08-04 17:09:16 +02001168 | +-----------------+---------------+------------+--------+-------------+
1169 |
1170 | Involved GPIOs
1171 |
1172 | +------------------------------------------------------------------------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001173 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
Stefan Roese17f50f222005-08-04 17:09:16 +02001174 | +---------+------------------+-----+-----------------+-----+-------------+-----+
Wolfgang Denkf901a832005-08-06 01:42:58 +02001175 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1176 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1177 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1178 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1179 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1180 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
Stefan Roese17f50f222005-08-04 17:09:16 +02001181 | +------------------------------------------------------------------------------+
1182 |
1183 |
1184 +----------------------------------------------------------------------------*/
1185
Eugene OBriend2f68002007-07-31 10:24:56 +02001186void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001187{
1188 switch (uart_config)
1189 {
1190 case L1:
1191 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001192 /* L1 configuration: UART0 = 8 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001193 /* ----------------------------------------------------------------------- */
1194 /* Update GPIO Configuration Table */
1195 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1196 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1197
1198 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1199 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1200
1201 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1202 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1203
1204 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1205 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1206
1207 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1208 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1209
1210 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1211 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1212
1213 break;
1214
1215 case L2:
1216 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001217 /* L2 configuration: UART0 = 4 pins */
1218 /* UART1 = 4 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001219 /* ----------------------------------------------------------------------- */
1220 /* Update GPIO Configuration Table */
1221 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1222 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1223
1224 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1225 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1226
1227 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1228 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1229
1230 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1231 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1232
1233 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1234 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1235
1236 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1237 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1238
1239 break;
1240
1241 case L3:
1242 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001243 /* L3 configuration: UART0 = 4 pins */
1244 /* UART1 = 2 pins */
1245 /* UART2 = 2 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001246 /* ----------------------------------------------------------------------- */
1247 /* Update GPIO Configuration Table */
1248 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1249 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1250
1251 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1252 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1253
1254 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1255 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1256
1257 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1258 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1259
1260 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1261 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1262
1263 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1264 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1265
1266 break;
1267
1268 case L4:
1269 /* ----------------------------------------------------------------------- */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001270 /* L4 configuration: UART0 = 2 pins */
1271 /* UART1 = 2 pins */
1272 /* UART2 = 2 pins */
1273 /* UART3 = 2 pins */
Stefan Roese17f50f222005-08-04 17:09:16 +02001274 /* ----------------------------------------------------------------------- */
1275 /* Update GPIO Configuration Table */
1276 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1277 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1278
1279 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1280 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1281
1282 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1283 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1284
1285 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1286 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1287
1288 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1289 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1290
1291 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1292 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1293
1294 break;
1295
1296 default:
1297 /* Unsupported UART configuration number */
1298 printf("ERROR - Unsupported UART configuration number.\n\n");
1299 for (;;)
1300 ;
1301 break;
1302
1303 }
1304
1305 /* Set input Selection Register on Alt_Receive for UART Input Core */
1306 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1307 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1308 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1309}
1310
1311/*----------------------------------------------------------------------------+
1312 | update_ndfc_ios(void).
1313 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001314void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001315{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001316 /* Update GPIO Configuration Table */
1317 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1318 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001319
Wolfgang Denkf901a832005-08-06 01:42:58 +02001320 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001321 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1322
Stefan Roesea471db02007-06-01 15:19:29 +02001323#if 0
Wolfgang Denkf901a832005-08-06 01:42:58 +02001324 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001325 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
Stefan Roese8a316c92005-08-01 16:49:12 +02001326#endif
Stefan Roese17f50f222005-08-04 17:09:16 +02001327}
1328
1329/*----------------------------------------------------------------------------+
1330 | update_zii_ios(void).
1331 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001332void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001333{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001334 /* Update GPIO Configuration Table */
1335 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1336 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001337
Wolfgang Denkf901a832005-08-06 01:42:58 +02001338 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1339 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001340
Wolfgang Denkf901a832005-08-06 01:42:58 +02001341 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1342 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001343
Wolfgang Denkf901a832005-08-06 01:42:58 +02001344 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1345 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001346
Wolfgang Denkf901a832005-08-06 01:42:58 +02001347 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1348 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001349
Wolfgang Denkf901a832005-08-06 01:42:58 +02001350 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1351 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001352
Wolfgang Denkf901a832005-08-06 01:42:58 +02001353 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1354 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001355
Wolfgang Denkf901a832005-08-06 01:42:58 +02001356 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1357 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001358
Wolfgang Denkf901a832005-08-06 01:42:58 +02001359 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1360 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001361
Wolfgang Denkf901a832005-08-06 01:42:58 +02001362 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1363 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001364
Wolfgang Denkf901a832005-08-06 01:42:58 +02001365 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1366 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001367
Wolfgang Denkf901a832005-08-06 01:42:58 +02001368 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1369 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001370
Wolfgang Denkf901a832005-08-06 01:42:58 +02001371 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1372 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001373
Wolfgang Denkf901a832005-08-06 01:42:58 +02001374 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1375 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
Stefan Roese17f50f222005-08-04 17:09:16 +02001376
1377}
1378
1379/*----------------------------------------------------------------------------+
1380 | update_uic_0_3_irq_ios().
1381 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001382void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001383{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001384 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001385 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1386
Wolfgang Denkf901a832005-08-06 01:42:58 +02001387 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001388 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1389
Wolfgang Denkf901a832005-08-06 01:42:58 +02001390 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001391 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1392
Wolfgang Denkf901a832005-08-06 01:42:58 +02001393 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001394 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1395}
1396
1397/*----------------------------------------------------------------------------+
1398 | update_uic_4_9_irq_ios().
1399 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001400void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001401{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001402 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001403 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1404
Wolfgang Denkf901a832005-08-06 01:42:58 +02001405 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001406 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1407
Wolfgang Denkf901a832005-08-06 01:42:58 +02001408 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001409 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1410
Wolfgang Denkf901a832005-08-06 01:42:58 +02001411 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001412 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1413
Wolfgang Denkf901a832005-08-06 01:42:58 +02001414 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001415 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1416}
1417
1418/*----------------------------------------------------------------------------+
1419 | update_dma_a_b_ios().
1420 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001421void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001422{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001423 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001424 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1425
Wolfgang Denkf901a832005-08-06 01:42:58 +02001426 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001427 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1428
Wolfgang Denkf901a832005-08-06 01:42:58 +02001429 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001430 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1431
Wolfgang Denkf901a832005-08-06 01:42:58 +02001432 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001433 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1434
Wolfgang Denkf901a832005-08-06 01:42:58 +02001435 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001436 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1437}
1438
1439/*----------------------------------------------------------------------------+
1440 | update_dma_c_d_ios().
1441 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001442void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001443{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001444 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001445 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1446
Wolfgang Denkf901a832005-08-06 01:42:58 +02001447 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001448 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1449
Wolfgang Denkf901a832005-08-06 01:42:58 +02001450 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001451 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1452
Wolfgang Denkf901a832005-08-06 01:42:58 +02001453 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001454 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1455
Wolfgang Denkf901a832005-08-06 01:42:58 +02001456 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001457 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1458
Wolfgang Denkf901a832005-08-06 01:42:58 +02001459 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
Stefan Roese17f50f222005-08-04 17:09:16 +02001460 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1461
1462}
1463
1464/*----------------------------------------------------------------------------+
1465 | update_ebc_master_ios().
1466 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001467void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001468{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001469 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
Stefan Roese17f50f222005-08-04 17:09:16 +02001470 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1471
Wolfgang Denkf901a832005-08-06 01:42:58 +02001472 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
Stefan Roese17f50f222005-08-04 17:09:16 +02001473 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1474
Wolfgang Denkf901a832005-08-06 01:42:58 +02001475 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
Stefan Roese17f50f222005-08-04 17:09:16 +02001476 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1477
Wolfgang Denkf901a832005-08-06 01:42:58 +02001478 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
Stefan Roese17f50f222005-08-04 17:09:16 +02001479 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1480}
1481
1482/*----------------------------------------------------------------------------+
1483 | update_usb2_device_ios().
1484 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001485void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001486{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001487 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
Stefan Roese17f50f222005-08-04 17:09:16 +02001488 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1489
Wolfgang Denkf901a832005-08-06 01:42:58 +02001490 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
Stefan Roese17f50f222005-08-04 17:09:16 +02001491 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1492
Wolfgang Denkf901a832005-08-06 01:42:58 +02001493 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
Stefan Roese17f50f222005-08-04 17:09:16 +02001494 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1495
Wolfgang Denkf901a832005-08-06 01:42:58 +02001496 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
Stefan Roese17f50f222005-08-04 17:09:16 +02001497 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1498
Wolfgang Denkf901a832005-08-06 01:42:58 +02001499 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
Stefan Roese17f50f222005-08-04 17:09:16 +02001500 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1501
Wolfgang Denkf901a832005-08-06 01:42:58 +02001502 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
Stefan Roese17f50f222005-08-04 17:09:16 +02001503 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1504
Wolfgang Denkf901a832005-08-06 01:42:58 +02001505 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
Stefan Roese17f50f222005-08-04 17:09:16 +02001506 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1507
Wolfgang Denkf901a832005-08-06 01:42:58 +02001508 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
Stefan Roese17f50f222005-08-04 17:09:16 +02001509 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1510
1511}
1512
1513/*----------------------------------------------------------------------------+
1514 | update_pci_patch_ios().
1515 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001516void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001517{
Wolfgang Denkf901a832005-08-06 01:42:58 +02001518 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
Stefan Roese17f50f222005-08-04 17:09:16 +02001519 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1520}
1521
1522/*----------------------------------------------------------------------------+
Eugene OBriend2f68002007-07-31 10:24:56 +02001523 | set_chip_gpio_configuration(unsigned char gpio_core,
1524 | gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001525 | Put the core impacted by clock modification and sharing in reset.
1526 | Config the select registers to resolve the sharing depending of the config.
1527 | Configure the GPIO registers.
1528 |
1529 +----------------------------------------------------------------------------*/
Eugene OBriend2f68002007-07-31 10:24:56 +02001530void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
Stefan Roese17f50f222005-08-04 17:09:16 +02001531{
1532 unsigned char i=0, j=0, reg_offset = 0;
1533 unsigned long gpio_reg, gpio_core_add;
1534
1535 /* GPIO config of the GPIOs 0 to 31 */
1536 for (i=0; i<GPIO_MAX; i++, j++)
1537 {
1538 if (i == GPIO_MAX/2)
1539 {
1540 reg_offset = 4;
1541 j = i-16;
1542 }
1543
1544 gpio_core_add = gpio_tab[gpio_core][i].add;
1545
1546 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1547 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1548 {
1549 switch (gpio_tab[gpio_core][i].alt_nb)
1550 {
1551 case GPIO_SEL:
1552 break;
1553
1554 case GPIO_ALT1:
1555 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1556 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1557 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1558 break;
1559
1560 case GPIO_ALT2:
1561 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1562 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1563 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1564 break;
1565
1566 case GPIO_ALT3:
1567 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1568 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1569 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1570 break;
1571 }
1572 }
1573 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1574 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1575 {
1576
1577 switch (gpio_tab[gpio_core][i].alt_nb)
1578 {
1579 case GPIO_SEL:
1580 break;
1581 case GPIO_ALT1:
1582 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1583 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1584 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1585 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1586 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1587 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1588 break;
1589 case GPIO_ALT2:
1590 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1591 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1592 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1593 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1594 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1595 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1596 break;
1597 case GPIO_ALT3:
1598 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1599 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1600 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1601 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1602 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1603 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1604 break;
1605 }
1606 }
1607 }
1608}
1609
1610/*----------------------------------------------------------------------------+
1611 | force_bup_core_selection.
1612 +----------------------------------------------------------------------------*/
1613void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1614{
1615 /* Pointer invalid */
1616 if (core_select_P == NULL)
1617 {
1618 printf("Configuration invalid pointer 1\n");
1619 for (;;)
1620 ;
1621 }
1622
1623 /* L4 Selection */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001624 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1625 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1626 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1627 *(core_select_P+UART_CORE3) = CORE_SELECTED;
Stefan Roese17f50f222005-08-04 17:09:16 +02001628
1629 /* RMII Selection */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001630 *(core_select_P+RMII_SEL) = CORE_SELECTED;
Stefan Roese17f50f222005-08-04 17:09:16 +02001631
1632 /* External Interrupt 0-9 selection */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001633 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1634 *(core_select_P+UIC_4_9) = CORE_SELECTED;
Stefan Roese17f50f222005-08-04 17:09:16 +02001635
Stefan Roesec57c7982005-08-11 17:56:56 +02001636 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1637 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1638 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
Wolfgang Denkf901a832005-08-06 01:42:58 +02001639 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
Stefan Roese17f50f222005-08-04 17:09:16 +02001640
Stefan Roesec57c7982005-08-11 17:56:56 +02001641 if (is_nand_selected()) {
1642 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1643 }
1644
Stefan Roese17f50f222005-08-04 17:09:16 +02001645 *config_val_P = CONFIG_IS_VALID;
1646
1647}
1648
1649/*----------------------------------------------------------------------------+
1650 | configure_ppc440ep_pins.
1651 +----------------------------------------------------------------------------*/
1652void configure_ppc440ep_pins(void)
1653{
1654 uart_config_nb_t uart_configuration;
1655 config_validity_t config_val = CONFIG_IS_INVALID;
1656
1657 /* Create Core Selection Table */
1658 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1659 {
Wolfgang Denkf901a832005-08-06 01:42:58 +02001660 CORE_NOT_SELECTED, /* IIC_CORE, */
1661 CORE_NOT_SELECTED, /* SPC_CORE, */
1662 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1663 CORE_NOT_SELECTED, /* UIC_4_9, */
1664 CORE_NOT_SELECTED, /* USB2_HOST, */
1665 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1666 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1667 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1668 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1669 CORE_NOT_SELECTED, /* EBC_MASTER, */
1670 CORE_NOT_SELECTED, /* NAND_FLASH, */
1671 CORE_NOT_SELECTED, /* UART_CORE0, */
1672 CORE_NOT_SELECTED, /* UART_CORE1, */
1673 CORE_NOT_SELECTED, /* UART_CORE2, */
1674 CORE_NOT_SELECTED, /* UART_CORE3, */
1675 CORE_NOT_SELECTED, /* MII_SEL, */
1676 CORE_NOT_SELECTED, /* RMII_SEL, */
1677 CORE_NOT_SELECTED, /* SMII_SEL, */
1678 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1679 CORE_NOT_SELECTED, /* UIC_0_3 */
1680 CORE_NOT_SELECTED, /* USB1_HOST */
1681 CORE_NOT_SELECTED /* PCI_PATCH */
Stefan Roese17f50f222005-08-04 17:09:16 +02001682 };
1683
Eugene OBriend2f68002007-07-31 10:24:56 +02001684 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
Stefan Roese17f50f222005-08-04 17:09:16 +02001685
1686 /* Table Default Initialisation + FPGA Access */
Eugene OBriend2f68002007-07-31 10:24:56 +02001687 init_default_gpio(gpio_tab);
1688 set_chip_gpio_configuration(GPIO0, gpio_tab);
1689 set_chip_gpio_configuration(GPIO1, gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001690
1691 /* Update Table */
1692 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1693#if 0 /* test-only */
1694 /* If we are running PIBS 1, force known configuration */
1695 update_core_selection_table(ppc440ep_core_selection, &config_val);
1696#endif
1697
1698 /*----------------------------------------------------------------------------+
1699 | SDR + ios table update + fpga initialization
1700 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +02001701 unsigned long sdr0_pfc1 = 0;
1702 unsigned long sdr0_usb0 = 0;
1703 unsigned long sdr0_mfr = 0;
Stefan Roese17f50f222005-08-04 17:09:16 +02001704
1705 /* PCI Always selected */
1706
1707 /* I2C Selection */
1708 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1709 {
1710 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1711 iic1_selection_in_fpga();
1712 }
1713
1714 /* SCP Selection */
1715 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1716 {
1717 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1718 scp_selection_in_fpga();
1719 }
1720
1721 /* UIC 0:3 Selection */
1722 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1723 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001724 update_uic_0_3_irq_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001725 dma_a_b_unselect_in_fpga();
1726 }
1727
1728 /* UIC 4:9 Selection */
1729 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1730 {
1731 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
Eugene OBriend2f68002007-07-31 10:24:56 +02001732 update_uic_4_9_irq_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001733 }
1734
1735 /* DMA AB Selection */
1736 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1737 {
1738 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
Eugene OBriend2f68002007-07-31 10:24:56 +02001739 update_dma_a_b_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001740 dma_a_b_selection_in_fpga();
1741 }
1742
1743 /* DMA CD Selection */
1744 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1745 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001746 update_dma_c_d_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001747 dma_c_d_selection_in_fpga();
1748 }
1749
1750 /* EBC Master Selection */
1751 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1752 {
1753 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1754 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
Eugene OBriend2f68002007-07-31 10:24:56 +02001755 update_ebc_master_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001756 }
1757
1758 /* PCI Patch Enable */
1759 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1760 {
1761 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
Eugene OBriend2f68002007-07-31 10:24:56 +02001762 update_pci_patch_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001763 }
1764
1765 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1766 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1767 {
1768 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1769 printf("Invalid configuration => USB2 Host selected\n");
1770 for (;;)
1771 ;
1772 /*usb2_host_selection_in_fpga(); */
1773 }
1774
1775 /* USB2.0 Device Selection */
1776 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1777 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001778 update_usb2_device_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001779 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1780 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1781
Stefan Roesed1c3b272009-09-09 16:25:29 +02001782 mfsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001783 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1784 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001785 mtsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001786
1787 usb2_device_selection_in_fpga();
1788 }
1789
1790 /* USB1.1 Device Selection */
1791 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1792 {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001793 mfsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001794 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1795 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001796 mtsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001797 }
1798
1799 /* USB1.1 Host Selection */
1800 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1801 {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001802 mfsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001803 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1804 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001805 mtsdr(SDR0_USB0, sdr0_usb0);
Stefan Roese17f50f222005-08-04 17:09:16 +02001806 }
1807
1808 /* NAND Flash Selection */
1809 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1810 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001811 update_ndfc_ios(gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001812
Stefan Roesea471db02007-06-01 15:19:29 +02001813#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
Stefan Roesed1c3b272009-09-09 16:25:29 +02001814 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
Wolfgang Denkf901a832005-08-06 01:42:58 +02001815 SDR0_CUST0_NDFC_ENABLE |
1816 SDR0_CUST0_NDFC_BW_8_BIT |
1817 SDR0_CUST0_NDFC_ARE_MASK |
Stefan Roesec57c7982005-08-11 17:56:56 +02001818 SDR0_CUST0_CHIPSELGAT_EN1 |
1819 SDR0_CUST0_CHIPSELGAT_EN2);
Stefan Roesea471db02007-06-01 15:19:29 +02001820#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001821 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
Stefan Roesea471db02007-06-01 15:19:29 +02001822 SDR0_CUST0_NDFC_ENABLE |
1823 SDR0_CUST0_NDFC_BW_8_BIT |
1824 SDR0_CUST0_NDFC_ARE_MASK |
1825 SDR0_CUST0_CHIPSELGAT_EN0 |
1826 SDR0_CUST0_CHIPSELGAT_EN2);
1827#endif
Stefan Roese17f50f222005-08-04 17:09:16 +02001828
1829 ndfc_selection_in_fpga();
1830 }
1831 else
1832 {
1833 /* Set Mux on EMAC */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001834 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
Stefan Roese17f50f222005-08-04 17:09:16 +02001835 }
1836
1837 /* MII Selection */
1838 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1839 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001840 update_zii_ios(gpio_tab);
Stefan Roesed1c3b272009-09-09 16:25:29 +02001841 mfsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001842 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001843 mtsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001844
1845 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1846 }
1847
1848 /* RMII Selection */
1849 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1850 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001851 update_zii_ios(gpio_tab);
Stefan Roesed1c3b272009-09-09 16:25:29 +02001852 mfsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001853 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001854 mtsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001855
1856 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1857 }
1858
1859 /* SMII Selection */
1860 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1861 {
Eugene OBriend2f68002007-07-31 10:24:56 +02001862 update_zii_ios(gpio_tab);
Stefan Roesed1c3b272009-09-09 16:25:29 +02001863 mfsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001864 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001865 mtsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001866
1867 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1868 }
1869
1870 /* UART Selection */
1871 uart_configuration = get_uart_configuration();
1872 switch (uart_configuration)
1873 {
Wolfgang Denkf901a832005-08-06 01:42:58 +02001874 case L1: /* L1 Selection */
Stefan Roese17f50f222005-08-04 17:09:16 +02001875 /* UART0 8 pins Only */
1876 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
Wolfgang Denkf901a832005-08-06 01:42:58 +02001877 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
Stefan Roese17f50f222005-08-04 17:09:16 +02001878 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1879 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +02001880 case L2: /* L2 Selection */
Stefan Roese17f50f222005-08-04 17:09:16 +02001881 /* UART0 and UART1 4 pins */
1882 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1883 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1884 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1885 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +02001886 case L3: /* L3 Selection */
Stefan Roese17f50f222005-08-04 17:09:16 +02001887 /* UART0 4 pins, UART1 and UART2 2 pins */
1888 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1889 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1890 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1891 break;
Wolfgang Denkf901a832005-08-06 01:42:58 +02001892 case L4: /* L4 Selection */
Stefan Roese17f50f222005-08-04 17:09:16 +02001893 /* UART0, UART1, UART2 and UART3 2 pins */
1894 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1895 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1896 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1897 break;
1898 }
Eugene OBriend2f68002007-07-31 10:24:56 +02001899 update_uart_ios(uart_configuration, gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001900
1901 /* UART Selection in all cases */
1902 uart_selection_in_fpga(uart_configuration);
1903
1904 /* Packet Reject Function Available */
1905 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1906 {
1907 /* Set UPR Bit in SDR0_PFC1 Register */
1908 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1909 }
1910
1911 /* Packet Reject Function Enable */
1912 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1913 {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001914 mfsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001915 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001916 mtsdr(SDR0_MFR, sdr0_mfr);
Stefan Roese17f50f222005-08-04 17:09:16 +02001917 }
1918
1919 /* Perform effective access to hardware */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001920 mtsdr(SDR0_PFC1, sdr0_pfc1);
Eugene OBriend2f68002007-07-31 10:24:56 +02001921 set_chip_gpio_configuration(GPIO0, gpio_tab);
1922 set_chip_gpio_configuration(GPIO1, gpio_tab);
Stefan Roese17f50f222005-08-04 17:09:16 +02001923
1924 /* USB2.0 Device Reset must be done after GPIO setting */
1925 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1926 usb2_device_reset_through_fpga();
1927
1928}