blob: f661c8e3b4496c59797edaa2fac4683af805d3d5 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8560ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000042#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050043#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000044
wdenk0ac6f8b2004-07-09 23:27:13 +000045#define CONFIG_PCI
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050047#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000048#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060049#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk42d1f032003-10-15 23:53:47 +000050
wdenk0ac6f8b2004-07-09 23:27:13 +000051/*
52 * sysclk for MPC85xx
53 *
54 * Two valid values are:
55 * 33000000
56 * 66000000
57 *
58 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000059 * is likely the desired value here, so that is now the default.
60 * The board, however, can run at 66MHz. In any event, this value
61 * must match the settings of some switches. Details can be found
62 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000063 */
64
wdenk9aea9532004-08-01 23:02:45 +000065#ifndef CONFIG_SYS_CLK_FREQ
66#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000067#endif
68
wdenk9aea9532004-08-01 23:02:45 +000069
wdenk0ac6f8b2004-07-09 23:27:13 +000070/*
71 * These can be toggled for performance analysis, otherwise use default.
72 */
73#define CONFIG_L2_CACHE /* toggle L2 cache */
74#define CONFIG_BTB /* toggle branch predition */
75#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
wdenk42d1f032003-10-15 23:53:47 +000076
wdenk0ac6f8b2004-07-09 23:27:13 +000077#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000078
wdenk0ac6f8b2004-07-09 23:27:13 +000079#define CFG_MEMTEST_START 0x00200000 /* memtest region */
wdenkc837dcb2004-01-20 23:12:12 +000080#define CFG_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000081
wdenk42d1f032003-10-15 23:53:47 +000082
83/*
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
86 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020087#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenk9aea9532004-08-01 23:02:45 +000088#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -060089#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenk0ac6f8b2004-07-09 23:27:13 +000090#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
wdenk42d1f032003-10-15 23:53:47 +000091
Jon Loeliger8b625112008-03-18 11:12:44 -050092/* DDR Setup */
93#define CONFIG_FSL_DDR1
94#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
95#define CONFIG_DDR_SPD
96#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000097
Jon Loeliger8b625112008-03-18 11:12:44 -050098#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
99
wdenk0ac6f8b2004-07-09 23:27:13 +0000100#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
wdenk42d1f032003-10-15 23:53:47 +0000101#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000102
Jon Loeliger8b625112008-03-18 11:12:44 -0500103#define CONFIG_NUM_DDR_CONTROLLERS 1
104#define CONFIG_DIMM_SLOTS_PER_CTLR 1
105#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +0000106
Jon Loeliger8b625112008-03-18 11:12:44 -0500107/* I2C addresses of SPD EEPROMs */
108#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +0000109
Jon Loeliger8b625112008-03-18 11:12:44 -0500110/* These are used when DDR doesn't use SPD. */
111#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
112#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
113#define CFG_DDR_CS0_CONFIG 0x80000002
114#define CFG_DDR_TIMING_1 0x37344321
115#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
116#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
117#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
118#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000119
wdenk0ac6f8b2004-07-09 23:27:13 +0000120/*
121 * SDRAM on the Local Bus
122 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000123#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
wdenk0ac6f8b2004-07-09 23:27:13 +0000124#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000125
wdenk0ac6f8b2004-07-09 23:27:13 +0000126#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
127#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000128
wdenk0ac6f8b2004-07-09 23:27:13 +0000129#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
130#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
131#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
wdenk42d1f032003-10-15 23:53:47 +0000132#undef CFG_FLASH_CHECKSUM
wdenk0ac6f8b2004-07-09 23:27:13 +0000133#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000135
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200136#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000137
wdenk42d1f032003-10-15 23:53:47 +0000138#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
139#define CFG_RAMBOOT
140#else
wdenk0ac6f8b2004-07-09 23:27:13 +0000141#undef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000142#endif
143
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200144#define CONFIG_FLASH_CFI_DRIVER
wdenkcf336782004-10-10 20:23:57 +0000145#define CFG_FLASH_CFI
146#define CFG_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000147
148#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000149
wdenk42d1f032003-10-15 23:53:47 +0000150
wdenk0ac6f8b2004-07-09 23:27:13 +0000151/*
152 * Local Bus Definitions
153 */
154
155/*
156 * Base Register 2 and Option Register 2 configure SDRAM.
157 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
158 *
159 * For BR2, need:
160 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
161 * port-size = 32-bits = BR2[19:20] = 11
162 * no parity checking = BR2[21:22] = 00
163 * SDRAM for MSEL = BR2[24:26] = 011
164 * Valid = BR[31] = 1
165 *
166 * 0 4 8 12 16 20 24 28
167 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
168 *
169 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
170 * FIXME: the top 17 bits of BR2.
171 */
172
173#define CFG_BR2_PRELIM 0xf0001861
174
175/*
176 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
177 *
178 * For OR2, need:
179 * 64MB mask for AM, OR2[0:7] = 1111 1100
180 * XAM, OR2[17:18] = 11
181 * 9 columns OR2[19-21] = 010
182 * 13 rows OR2[23-25] = 100
183 * EAD set for extra time OR[31] = 1
184 *
185 * 0 4 8 12 16 20 24 28
186 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
187 */
188
wdenk42d1f032003-10-15 23:53:47 +0000189#define CFG_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000190
191#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
192#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
193#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
194#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
195
196/*
197 * LSDMR masks
198 */
199#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
200#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
201#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
202#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
203#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
204#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
205#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
206#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
207#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
208#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
209#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
210#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
211#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
212#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
213#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
214
215#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
216#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
217#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
218#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
219#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
220#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
221#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
222#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
223
224#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
225 | CFG_LBC_LSDMR_RFCR5 \
226 | CFG_LBC_LSDMR_PRETOACT3 \
227 | CFG_LBC_LSDMR_ACTTORW3 \
228 | CFG_LBC_LSDMR_BL8 \
229 | CFG_LBC_LSDMR_WRC2 \
230 | CFG_LBC_LSDMR_CL3 \
231 | CFG_LBC_LSDMR_RFEN \
232 )
233
234/*
235 * SDRAM Controller configuration sequence.
236 */
237#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000238 | CFG_LBC_LSDMR_OP_PCHALL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000239#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000240 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000241#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000242 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000243#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000244 | CFG_LBC_LSDMR_OP_MRW)
wdenk0ac6f8b2004-07-09 23:27:13 +0000245#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000246 | CFG_LBC_LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000247
wdenk42d1f032003-10-15 23:53:47 +0000248
wdenk9aea9532004-08-01 23:02:45 +0000249/*
250 * 32KB, 8-bit wide for ADS config reg
251 */
252#define CFG_BR4_PRELIM 0xf8000801
wdenk42d1f032003-10-15 23:53:47 +0000253#define CFG_OR4_PRELIM 0xffffe1f1
254#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
255
256#define CONFIG_L1_INIT_RAM
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200257#define CFG_INIT_RAM_LOCK 1
wdenk9aea9532004-08-01 23:02:45 +0000258#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200259#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000260
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200261#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
wdenk42d1f032003-10-15 23:53:47 +0000262#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
263#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
264
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200265#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
266#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000267
268/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000269#define CONFIG_CONS_ON_SCC /* define if console on SCC */
270#undef CONFIG_CONS_NONE /* define if console on something else */
271#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000272
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200273#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000274
275#define CFG_BAUDRATE_TABLE \
276 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
277
278/* Use the HUSH parser */
279#define CFG_HUSH_PARSER
wdenk0ac6f8b2004-07-09 23:27:13 +0000280#ifdef CFG_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000281#define CFG_PROMPT_HUSH_PS2 "> "
282#endif
283
Matthew McClintock0e163872006-06-28 10:43:36 -0500284/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
287#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500288
Jon Loeliger8b625112008-03-18 11:12:44 -0500289#define CFG_64BIT_VSPRINTF 1
290#define CFG_64BIT_STRTOUL 1
291
Jon Loeliger20476722006-10-20 15:50:15 -0500292/*
293 * I2C
294 */
295#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
296#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk42d1f032003-10-15 23:53:47 +0000297#undef CONFIG_SOFT_I2C /* I2C bit-banged */
wdenk0ac6f8b2004-07-09 23:27:13 +0000298#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
wdenk42d1f032003-10-15 23:53:47 +0000299#define CFG_I2C_SLAVE 0x7F
wdenk9aea9532004-08-01 23:02:45 +0000300#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500301#define CFG_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000302
wdenk0ac6f8b2004-07-09 23:27:13 +0000303/* RapidIO MMU */
304#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
305#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
306#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000307
wdenk0ac6f8b2004-07-09 23:27:13 +0000308/*
309 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300310 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000311 */
312#define CFG_PCI1_MEM_BASE 0x80000000
313#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
314#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300315#define CFG_PCI1_IO_BASE 0x00000000
316#define CFG_PCI1_IO_PHYS 0xe2000000
317#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000318
319#if defined(CONFIG_PCI)
320
wdenk42d1f032003-10-15 23:53:47 +0000321#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200322#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000323
324#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000325#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000326
327#if !defined(CONFIG_PCI_PNP)
328 #define PCI_ENET0_IOADDR 0xe0000000
329 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200330 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000331#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000332
333#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
335
336#endif /* CONFIG_PCI */
337
338
Andy Flemingccc091a2007-05-08 17:27:43 -0500339#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000340
341#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200342#define CONFIG_NET_MULTI 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000343#endif
344
Andy Flemingccc091a2007-05-08 17:27:43 -0500345#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000346#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500347#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500348#define CONFIG_TSEC1 1
349#define CONFIG_TSEC1_NAME "TSEC0"
350#define CONFIG_TSEC2 1
351#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000352#define TSEC1_PHY_ADDR 0
353#define TSEC2_PHY_ADDR 1
354#define TSEC1_PHYIDX 0
355#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500356#define TSEC1_FLAGS TSEC_GIGABIT
357#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500358
359/* Options are: TSEC[0-1] */
360#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000361
Andy Flemingccc091a2007-05-08 17:27:43 -0500362#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000363
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200364#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500365
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200366#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000367#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
368
369#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000370 /*
371 * - Rx-CLK is CLK13
372 * - Tx-CLK is CLK14
373 * - Select bus for bd/buffers
374 * - Full duplex
375 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000376 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
377 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
378 #define CFG_CPMFCR_RAMTYPE 0
379 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000380 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000381#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000382 /* need more definitions here for FE3 */
383 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200384#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000385
Andy Flemingccc091a2007-05-08 17:27:43 -0500386#ifndef CONFIG_MII
387#define CONFIG_MII 1 /* MII PHY management */
388#endif
389
wdenk0ac6f8b2004-07-09 23:27:13 +0000390#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
391
wdenk42d1f032003-10-15 23:53:47 +0000392/*
393 * GPIO pins used for bit-banged MII communications
394 */
395#define MDIO_PORT 2 /* Port C */
396#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
397#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
398#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
399
400#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
401 else iop->pdat &= ~0x00400000
402
403#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
404 else iop->pdat &= ~0x00200000
405
406#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000407
wdenk42d1f032003-10-15 23:53:47 +0000408#endif
409
wdenk0ac6f8b2004-07-09 23:27:13 +0000410
411/*
412 * Environment
413 */
wdenk42d1f032003-10-15 23:53:47 +0000414#ifndef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000415 #define CFG_ENV_IS_IN_FLASH 1
416 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
wdenk0ac6f8b2004-07-09 23:27:13 +0000417 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
wdenk42d1f032003-10-15 23:53:47 +0000418 #define CFG_ENV_SIZE 0x2000
419#else
wdenk9aea9532004-08-01 23:02:45 +0000420 #define CFG_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200421 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
wdenk9aea9532004-08-01 23:02:45 +0000422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
423 #define CFG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000424#endif
425
wdenk0ac6f8b2004-07-09 23:27:13 +0000426#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
427#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000428
Jon Loeliger2835e512007-06-13 13:22:08 -0500429/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500430 * BOOTP options
431 */
432#define CONFIG_BOOTP_BOOTFILESIZE
433#define CONFIG_BOOTP_BOOTPATH
434#define CONFIG_BOOTP_GATEWAY
435#define CONFIG_BOOTP_HOSTNAME
436
437
438/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500439 * Command line configuration.
440 */
441#include <config_cmd_default.h>
442
443#define CONFIG_CMD_PING
444#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600445#define CONFIG_CMD_ELF
Jon Loeliger2835e512007-06-13 13:22:08 -0500446
447#if defined(CONFIG_PCI)
448 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000449#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000450
Jon Loeliger2835e512007-06-13 13:22:08 -0500451#if defined(CONFIG_ETHER_ON_FCC)
452 #define CONFIG_CMD_MII
453#endif
454
455#if defined(CFG_RAMBOOT)
456 #undef CONFIG_CMD_ENV
457 #undef CONFIG_CMD_LOADS
458#endif
459
wdenk42d1f032003-10-15 23:53:47 +0000460
wdenk0ac6f8b2004-07-09 23:27:13 +0000461#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000462
463/*
464 * Miscellaneous configurable options
465 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000466#define CFG_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600467#define CONFIG_CMDLINE_EDITING /* Command-line editing */
wdenk42d1f032003-10-15 23:53:47 +0000468#define CFG_LOAD_ADDR 0x1000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000469#define CFG_PROMPT "=> " /* Monitor Command Prompt */
470
Jon Loeliger2835e512007-06-13 13:22:08 -0500471#if defined(CONFIG_CMD_KGDB)
wdenk0ac6f8b2004-07-09 23:27:13 +0000472 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
473#else
474 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
475#endif
476
477#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
478#define CFG_MAXARGS 16 /* max number of command args */
479#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
480#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000481
482/*
483 * For booting Linux, the board info and command line data
484 * have to be in the first 8 MB of memory, since this is
485 * the maximum mapped by the Linux kernel during initialization.
486 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000487#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk42d1f032003-10-15 23:53:47 +0000488
wdenk42d1f032003-10-15 23:53:47 +0000489/*
490 * Internal Definitions
491 *
492 * Boot Flags
493 */
494#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk0ac6f8b2004-07-09 23:27:13 +0000495#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk42d1f032003-10-15 23:53:47 +0000496
Jon Loeliger2835e512007-06-13 13:22:08 -0500497#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000498#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
499#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
500#endif
501
wdenk9aea9532004-08-01 23:02:45 +0000502
503/*
504 * Environment Configuration
505 */
506
wdenk0ac6f8b2004-07-09 23:27:13 +0000507/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000508#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500509#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000510#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000511#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000512#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000513#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000514#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Gala5ce71582007-11-28 22:40:31 -0600515#define CONFIG_HAS_ETH3
516#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk42d1f032003-10-15 23:53:47 +0000517#endif
518
wdenk0ac6f8b2004-07-09 23:27:13 +0000519#define CONFIG_IPADDR 192.168.1.253
520
521#define CONFIG_HOSTNAME unknown
522#define CONFIG_ROOTPATH /nfsroot
523#define CONFIG_BOOTFILE your.uImage
524
525#define CONFIG_SERVERIP 192.168.1.1
526#define CONFIG_GATEWAYIP 192.168.1.1
527#define CONFIG_NETMASK 255.255.255.0
528
529#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
530
wdenk9aea9532004-08-01 23:02:45 +0000531#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000532#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
533
534#define CONFIG_BAUDRATE 115200
535
wdenk9aea9532004-08-01 23:02:45 +0000536#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500537 "netdev=eth0\0" \
538 "consoledev=ttyCPM\0" \
539 "ramdiskaddr=1000000\0" \
540 "ramdiskfile=your.ramdisk.u-boot\0" \
541 "fdtaddr=400000\0" \
542 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000543
wdenk9aea9532004-08-01 23:02:45 +0000544#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500545 "setenv bootargs root=/dev/nfs rw " \
546 "nfsroot=$serverip:$rootpath " \
547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
548 "console=$consoledev,$baudrate $othbootargs;" \
549 "tftp $loadaddr $bootfile;" \
550 "tftp $fdtaddr $fdtfile;" \
551 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000552
553#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500554 "setenv bootargs root=/dev/ram rw " \
555 "console=$consoledev,$baudrate $othbootargs;" \
556 "tftp $ramdiskaddr $ramdiskfile;" \
557 "tftp $loadaddr $bootfile;" \
558 "tftp $fdtaddr $fdtfile;" \
559 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000560
561#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000562
563#endif /* __CONFIG_H */