wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Josef Baumgartner <josef.baumgartner@telex.de> |
| 4 | * |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 5 | * MCF5282 additionals |
| 6 | * (C) Copyright 2005 |
| 7 | * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> |
Michael Durrant | dfc2b76 | 2010-01-20 19:33:02 -0600 | [diff] [blame] | 8 | * (c) Copyright 2010 |
| 9 | * Arcturus Networks Inc. <www.arcturusnetworks.com> |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 10 | * |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 11 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 12 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 13 | * Hayden Fraser (Hayden.Fraser@freescale.com) |
| 14 | * |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 15 | * MCF5275 additions |
| 16 | * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) |
| 17 | * |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 18 | * See file CREDITS for list of people who contributed to this |
| 19 | * project. |
| 20 | * |
| 21 | * This program is free software; you can redistribute it and/or |
| 22 | * modify it under the terms of the GNU General Public License as |
| 23 | * published by the Free Software Foundation; either version 2 of |
| 24 | * the License, or (at your option) any later version. |
| 25 | * |
| 26 | * This program is distributed in the hope that it will be useful, |
| 27 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Wolfgang Denk | 977b50f | 2006-05-10 17:43:20 +0200 | [diff] [blame] | 28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 29 | * GNU General Public License for more details. |
| 30 | * |
| 31 | * You should have received a copy of the GNU General Public License |
| 32 | * along with this program; if not, write to the Free Software |
| 33 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 34 | * MA 02111-1307 USA |
| 35 | */ |
| 36 | |
| 37 | #include <common.h> |
| 38 | #include <watchdog.h> |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 39 | #include <asm/immap.h> |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 40 | #include <asm/io.h> |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 41 | |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 42 | #if defined(CONFIG_CMD_NET) |
| 43 | #include <config.h> |
| 44 | #include <net.h> |
| 45 | #include <asm/fec.h> |
| 46 | #endif |
| 47 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 48 | #ifndef CONFIG_M5272 |
| 49 | /* Only 5272 Flexbus chipselect is different from the rest */ |
| 50 | void init_fbcs(void) |
| 51 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 52 | fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 53 | |
| 54 | #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ |
| 55 | && defined(CONFIG_SYS_CS0_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 56 | out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); |
| 57 | out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); |
| 58 | out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 59 | #else |
| 60 | #warning "Chip Select 0 are not initialized/used" |
| 61 | #endif |
| 62 | #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ |
| 63 | && defined(CONFIG_SYS_CS1_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 64 | out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); |
| 65 | out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); |
| 66 | out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 67 | #endif |
| 68 | #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ |
| 69 | && defined(CONFIG_SYS_CS2_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 70 | out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); |
| 71 | out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); |
| 72 | out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 73 | #endif |
| 74 | #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ |
| 75 | && defined(CONFIG_SYS_CS3_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 76 | out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); |
| 77 | out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); |
| 78 | out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 79 | #endif |
| 80 | #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ |
| 81 | && defined(CONFIG_SYS_CS4_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 82 | out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); |
| 83 | out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); |
| 84 | out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 85 | #endif |
| 86 | #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ |
| 87 | && defined(CONFIG_SYS_CS5_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 88 | out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); |
| 89 | out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); |
| 90 | out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 91 | #endif |
| 92 | #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ |
| 93 | && defined(CONFIG_SYS_CS6_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 94 | out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); |
| 95 | out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); |
| 96 | out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 97 | #endif |
| 98 | #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ |
| 99 | && defined(CONFIG_SYS_CS7_CTRL)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 100 | out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); |
| 101 | out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); |
| 102 | out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 103 | #endif |
| 104 | } |
| 105 | #endif |
| 106 | |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 107 | #if defined(CONFIG_M5208) |
| 108 | void cpu_init_f(void) |
| 109 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 110 | scm1_t *scm1 = (scm1_t *) MMAP_SCM1; |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 111 | |
| 112 | #ifndef CONFIG_WATCHDOG |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 113 | wdog_t *wdg = (wdog_t *) MMAP_WDOG; |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 114 | |
| 115 | /* Disable the watchdog if we aren't using it */ |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 116 | out_be16(&wdg->cr, 0); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 117 | #endif |
| 118 | |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 119 | out_be32(&scm1->mpr, 0x77777777); |
| 120 | out_be32(&scm1->pacra, 0); |
| 121 | out_be32(&scm1->pacrb, 0); |
| 122 | out_be32(&scm1->pacrc, 0); |
| 123 | out_be32(&scm1->pacrd, 0); |
| 124 | out_be32(&scm1->pacre, 0); |
| 125 | out_be32(&scm1->pacrf, 0); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 126 | |
| 127 | /* FlexBus Chipselect */ |
| 128 | init_fbcs(); |
| 129 | |
| 130 | icache_enable(); |
| 131 | } |
| 132 | |
| 133 | /* initialize higher level parts of CPU like timers */ |
| 134 | int cpu_init_r(void) |
| 135 | { |
| 136 | return (0); |
| 137 | } |
| 138 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 139 | void uart_port_conf(int port) |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 140 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 141 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 142 | |
| 143 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 144 | switch (port) { |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 145 | case 0: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 146 | clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); |
| 147 | setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 148 | break; |
| 149 | case 1: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 150 | clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); |
| 151 | setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 152 | break; |
| 153 | case 2: |
| 154 | #ifdef CONFIG_SYS_UART2_PRI_GPIO |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 155 | clrbits_8(&gpio->par_timer, |
| 156 | ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); |
| 157 | setbits_8(&gpio->par_timer, |
| 158 | GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 159 | #endif |
| 160 | #ifdef CONFIG_SYS_UART2_ALT1_GPIO |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 161 | clrbits_8(&gpio->par_feci2c, |
| 162 | ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); |
| 163 | setbits_8(&gpio->par_feci2c, |
| 164 | GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 165 | #endif |
| 166 | #ifdef CONFIG_SYS_UART2_ALT1_GPIO |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 167 | clrbits_8(&gpio->par_feci2c, |
| 168 | ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); |
| 169 | setbits_8(&gpio->par_feci2c, |
| 170 | GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 171 | #endif |
| 172 | break; |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | #if defined(CONFIG_CMD_NET) |
| 177 | int fecpin_setclear(struct eth_device *dev, int setclear) |
| 178 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 179 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 180 | |
| 181 | if (setclear) { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 182 | setbits_8(&gpio->par_fec, |
| 183 | GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); |
| 184 | setbits_8(&gpio->par_feci2c, |
| 185 | GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 186 | } else { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 187 | clrbits_8(&gpio->par_fec, |
| 188 | ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); |
| 189 | clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); |
TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 190 | } |
| 191 | return 0; |
| 192 | } |
| 193 | #endif /* CONFIG_CMD_NET */ |
| 194 | #endif /* CONFIG_M5208 */ |
| 195 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 196 | #if defined(CONFIG_M5253) |
| 197 | /* |
| 198 | * Breath some life into the CPU... |
| 199 | * |
| 200 | * Set up the memory map, |
| 201 | * initialize a bunch of registers, |
| 202 | * initialize the UPM's |
| 203 | */ |
| 204 | void cpu_init_f(void) |
| 205 | { |
| 206 | mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ |
| 207 | mbar_writeByte(MCFSIM_SYPCR, 0x00); |
| 208 | mbar_writeByte(MCFSIM_SWIVR, 0x0f); |
| 209 | mbar_writeByte(MCFSIM_SWSR, 0x00); |
| 210 | mbar_writeByte(MCFSIM_SWDICR, 0x00); |
| 211 | mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); |
| 212 | mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); |
| 213 | mbar_writeByte(MCFSIM_I2CICR, 0x00); |
| 214 | mbar_writeByte(MCFSIM_UART1ICR, 0x00); |
| 215 | mbar_writeByte(MCFSIM_UART2ICR, 0x00); |
| 216 | mbar_writeByte(MCFSIM_ICR6, 0x00); |
| 217 | mbar_writeByte(MCFSIM_ICR7, 0x00); |
| 218 | mbar_writeByte(MCFSIM_ICR8, 0x00); |
| 219 | mbar_writeByte(MCFSIM_ICR9, 0x00); |
| 220 | mbar_writeByte(MCFSIM_QSPIICR, 0x00); |
| 221 | |
| 222 | mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); |
| 223 | mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ |
| 224 | mbar2_writeByte(MCFSIM_SPURVEC, 0x00); |
| 225 | |
Wolfgang Denk | 455ae7e | 2008-12-16 01:02:17 +0100 | [diff] [blame] | 226 | /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 227 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 228 | /* FlexBus Chipselect */ |
| 229 | init_fbcs(); |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 230 | |
TsiChung Liew | eec567a | 2008-08-19 03:01:19 +0600 | [diff] [blame] | 231 | #ifdef CONFIG_FSL_I2C |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 232 | CONFIG_SYS_I2C_PINMUX_REG = |
| 233 | CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; |
| 235 | #ifdef CONFIG_SYS_I2C2_OFFSET |
| 236 | CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; |
| 237 | CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; |
TsiChung Liew | eec567a | 2008-08-19 03:01:19 +0600 | [diff] [blame] | 238 | #endif |
| 239 | #endif |
| 240 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 241 | /* enable instruction cache now */ |
| 242 | icache_enable(); |
| 243 | } |
| 244 | |
| 245 | /*initialize higher level parts of CPU like timers */ |
| 246 | int cpu_init_r(void) |
| 247 | { |
| 248 | return (0); |
| 249 | } |
| 250 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 251 | void uart_port_conf(int port) |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 252 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 253 | u32 *par = (u32 *) MMAP_PAR; |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 254 | |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 255 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 256 | switch (port) { |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 257 | case 1: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 258 | clrbits_be32(par, 0x00180000); |
| 259 | setbits_be32(par, 0x00180000); |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 260 | break; |
| 261 | case 2: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 262 | clrbits_be32(par, 0x00000003); |
| 263 | clrbits_be32(par, 0xFFFFFFFC); |
TsiChungLiew | a1436a8 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 264 | break; |
| 265 | } |
| 266 | } |
| 267 | #endif /* #if defined(CONFIG_M5253) */ |
| 268 | |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 269 | #if defined(CONFIG_M5271) |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 270 | void cpu_init_f(void) |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 271 | { |
| 272 | #ifndef CONFIG_WATCHDOG |
| 273 | /* Disable the watchdog if we aren't using it */ |
| 274 | mbar_writeShort(MCF_WTM_WCR, 0); |
| 275 | #endif |
| 276 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 277 | /* FlexBus Chipselect */ |
| 278 | init_fbcs(); |
| 279 | |
Richard Retanubun | e0db344 | 2009-01-29 14:36:06 -0500 | [diff] [blame] | 280 | #ifdef CONFIG_SYS_MCF_SYNCR |
| 281 | /* Set clockspeed according to board header file */ |
| 282 | mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); |
| 283 | #else |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 284 | /* Set clockspeed to 100MHz */ |
Richard Retanubun | e0db344 | 2009-01-29 14:36:06 -0500 | [diff] [blame] | 285 | mbar_writeLong(MCF_FMPLL_SYNCR, |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 286 | MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); |
Richard Retanubun | e0db344 | 2009-01-29 14:36:06 -0500 | [diff] [blame] | 287 | #endif |
Mike Frysinger | 65f0d12 | 2011-10-15 10:10:42 +0000 | [diff] [blame] | 288 | while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ; |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | /* |
| 292 | * initialize higher level parts of CPU like timers |
| 293 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 294 | int cpu_init_r(void) |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 295 | { |
| 296 | return (0); |
| 297 | } |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 298 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 299 | void uart_port_conf(int port) |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 300 | { |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 301 | u16 temp; |
| 302 | |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 303 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 304 | switch (port) { |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 305 | case 0: |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 306 | temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3; |
| 307 | temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); |
| 308 | mbar_writeShort(MCF_GPIO_PAR_UART, temp); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 309 | break; |
| 310 | case 1: |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 311 | temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF; |
| 312 | temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1); |
| 313 | mbar_writeShort(MCF_GPIO_PAR_UART, temp); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 314 | break; |
| 315 | case 2: |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 316 | temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF; |
| 317 | temp |= (0x3000); |
| 318 | mbar_writeShort(MCF_GPIO_PAR_UART, temp); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 319 | break; |
| 320 | } |
| 321 | } |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 322 | |
| 323 | #if defined(CONFIG_CMD_NET) |
| 324 | int fecpin_setclear(struct eth_device *dev, int setclear) |
| 325 | { |
| 326 | if (setclear) { |
| 327 | /* Enable Ethernet pins */ |
Richard Retanubun | d1ef25d | 2009-01-23 10:47:13 -0500 | [diff] [blame] | 328 | mbar_writeByte(MCF_GPIO_PAR_FECI2C, |
| 329 | (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 330 | } else { |
| 331 | } |
| 332 | |
| 333 | return 0; |
| 334 | } |
| 335 | #endif /* CONFIG_CMD_NET */ |
Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 336 | #endif |
| 337 | |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 338 | #if defined(CONFIG_M5272) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 339 | /* |
| 340 | * Breath some life into the CPU... |
| 341 | * |
| 342 | * Set up the memory map, |
| 343 | * initialize a bunch of registers, |
| 344 | * initialize the UPM's |
| 345 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 346 | void cpu_init_f(void) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 347 | { |
| 348 | /* if we come from RAM we assume the CPU is |
| 349 | * already initialized. |
| 350 | */ |
| 351 | #ifndef CONFIG_MONITOR_IS_IN_RAM |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 352 | sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); |
| 353 | gpio_t *gpio = (gpio_t *) (MMAP_GPIO); |
| 354 | csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 355 | |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 356 | out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); |
| 357 | out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 358 | |
Wolfgang Denk | 977b50f | 2006-05-10 17:43:20 +0200 | [diff] [blame] | 359 | /* Setup Ports: */ |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 360 | out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); |
| 361 | out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); |
| 362 | out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); |
| 363 | out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); |
| 364 | out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); |
| 365 | out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); |
| 366 | out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 367 | |
| 368 | /* Memory Controller: */ |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 369 | out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); |
| 370 | out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 371 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 373 | out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); |
| 374 | out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 375 | #endif |
| 376 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 377 | #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 378 | out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); |
| 379 | out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 380 | #endif |
| 381 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 382 | #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 383 | out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); |
| 384 | out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 385 | #endif |
| 386 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 387 | #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 388 | out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); |
| 389 | out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 390 | #endif |
| 391 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 392 | #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 393 | out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); |
| 394 | out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 395 | #endif |
| 396 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 397 | #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 398 | out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); |
| 399 | out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 400 | #endif |
| 401 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 402 | #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 403 | out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); |
| 404 | out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 405 | #endif |
| 406 | |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 407 | #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 408 | |
Wolfgang Denk | 977b50f | 2006-05-10 17:43:20 +0200 | [diff] [blame] | 409 | /* enable instruction cache now */ |
| 410 | icache_enable(); |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 411 | |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * initialize higher level parts of CPU like timers |
| 416 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 417 | int cpu_init_r(void) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 418 | { |
| 419 | return (0); |
| 420 | } |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 421 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 422 | void uart_port_conf(int port) |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 423 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 424 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 425 | |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 426 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 427 | switch (port) { |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 428 | case 0: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 429 | clrbits_be32(&gpio->gpio_pbcnt, |
| 430 | GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); |
| 431 | setbits_be32(&gpio->gpio_pbcnt, |
| 432 | GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 433 | break; |
| 434 | case 1: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 435 | clrbits_be32(&gpio->gpio_pdcnt, |
| 436 | GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); |
| 437 | setbits_be32(&gpio->gpio_pdcnt, |
| 438 | GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 439 | break; |
| 440 | } |
| 441 | } |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 442 | |
| 443 | #if defined(CONFIG_CMD_NET) |
| 444 | int fecpin_setclear(struct eth_device *dev, int setclear) |
| 445 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 446 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 447 | |
| 448 | if (setclear) { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 449 | setbits_be32(&gpio->gpio_pbcnt, |
| 450 | GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | |
| 451 | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | |
| 452 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | |
| 453 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 454 | } else { |
| 455 | } |
| 456 | return 0; |
| 457 | } |
| 458 | #endif /* CONFIG_CMD_NET */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 459 | #endif /* #if defined(CONFIG_M5272) */ |
| 460 | |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 461 | #if defined(CONFIG_M5275) |
| 462 | |
| 463 | /* |
| 464 | * Breathe some life into the CPU... |
| 465 | * |
| 466 | * Set up the memory map, |
| 467 | * initialize a bunch of registers, |
| 468 | * initialize the UPM's |
| 469 | */ |
| 470 | void cpu_init_f(void) |
| 471 | { |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 472 | /* |
| 473 | * if we come from RAM we assume the CPU is |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 474 | * already initialized. |
| 475 | */ |
| 476 | |
| 477 | #ifndef CONFIG_MONITOR_IS_IN_RAM |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 478 | wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); |
| 479 | gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 480 | |
| 481 | /* Kill watchdog so we can initialize the PLL */ |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 482 | out_be16(&wdog_reg->wcr, 0); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 483 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 484 | /* FlexBus Chipselect */ |
| 485 | init_fbcs(); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 486 | #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ |
| 487 | |
| 488 | #ifdef CONFIG_FSL_I2C |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 489 | CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; |
| 490 | CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 491 | #endif |
| 492 | |
| 493 | /* enable instruction cache now */ |
| 494 | icache_enable(); |
| 495 | } |
| 496 | |
| 497 | /* |
| 498 | * initialize higher level parts of CPU like timers |
| 499 | */ |
| 500 | int cpu_init_r(void) |
| 501 | { |
| 502 | return (0); |
| 503 | } |
| 504 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 505 | void uart_port_conf(int port) |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 506 | { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 507 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 508 | |
| 509 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 510 | switch (port) { |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 511 | case 0: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 512 | clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); |
| 513 | setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 514 | break; |
| 515 | case 1: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 516 | clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); |
| 517 | setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 518 | break; |
| 519 | case 2: |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 520 | clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); |
| 521 | setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 522 | break; |
| 523 | } |
| 524 | } |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 525 | |
| 526 | #if defined(CONFIG_CMD_NET) |
| 527 | int fecpin_setclear(struct eth_device *dev, int setclear) |
| 528 | { |
| 529 | struct fec_info_s *info = (struct fec_info_s *) dev->priv; |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 530 | gpio_t *gpio = (gpio_t *)MMAP_GPIO; |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 531 | |
| 532 | if (setclear) { |
| 533 | /* Enable Ethernet pins */ |
| 534 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 535 | setbits_be16(&gpio->par_feci2c, 0x0f00); |
| 536 | setbits_8(&gpio->par_fec0hl, 0xc0); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 537 | } else { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 538 | setbits_be16(&gpio->par_feci2c, 0x00a0); |
| 539 | setbits_8(&gpio->par_fec1hl, 0xc0); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 540 | } |
| 541 | } else { |
| 542 | if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 543 | clrbits_be16(&gpio->par_feci2c, 0x0f00); |
| 544 | clrbits_8(&gpio->par_fec0hl, 0xc0); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 545 | } else { |
Alison Wang | 32dbaaf | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 546 | clrbits_be16(&gpio->par_feci2c, 0x00a0); |
| 547 | clrbits_8(&gpio->par_fec1hl, 0xc0); |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 548 | } |
| 549 | } |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | #endif /* CONFIG_CMD_NET */ |
Matthew Fettke | f71d9d9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 554 | #endif /* #if defined(CONFIG_M5275) */ |
| 555 | |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 556 | #if defined(CONFIG_M5282) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 557 | /* |
| 558 | * Breath some life into the CPU... |
| 559 | * |
| 560 | * Set up the memory map, |
| 561 | * initialize a bunch of registers, |
| 562 | * initialize the UPM's |
| 563 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 564 | void cpu_init_f(void) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 565 | { |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 566 | #ifndef CONFIG_WATCHDOG |
| 567 | /* disable watchdog if we aren't using it */ |
| 568 | MCFWTM_WCR = 0; |
| 569 | #endif |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 570 | |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 571 | #ifndef CONFIG_MONITOR_IS_IN_RAM |
| 572 | /* Set speed /PLL */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 573 | MCFCLOCK_SYNCR = |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 574 | MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | |
| 575 | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 576 | while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; |
| 577 | |
| 578 | MCFGPIO_PBCDPAR = 0xc0; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 579 | |
| 580 | /* Set up the GPIO ports */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 581 | #ifdef CONFIG_SYS_PEPAR |
| 582 | MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 583 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 584 | #ifdef CONFIG_SYS_PFPAR |
| 585 | MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 586 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 587 | #ifdef CONFIG_SYS_PJPAR |
| 588 | MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 589 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 590 | #ifdef CONFIG_SYS_PSDPAR |
| 591 | MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 592 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 593 | #ifdef CONFIG_SYS_PASPAR |
| 594 | MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 595 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 596 | #ifdef CONFIG_SYS_PEHLPAR |
| 597 | MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 598 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 599 | #ifdef CONFIG_SYS_PQSPAR |
| 600 | MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 601 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 602 | #ifdef CONFIG_SYS_PTCPAR |
| 603 | MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 604 | #endif |
Michael Durrant | dfc2b76 | 2010-01-20 19:33:02 -0600 | [diff] [blame] | 605 | #if defined(CONFIG_SYS_PORTTC) |
| 606 | MCFGPIO_PORTTC = CONFIG_SYS_PORTTC; |
| 607 | #endif |
| 608 | #if defined(CONFIG_SYS_DDRTC) |
| 609 | MCFGPIO_DDRTC = CONFIG_SYS_DDRTC; |
| 610 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 611 | #ifdef CONFIG_SYS_PTDPAR |
| 612 | MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 613 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 614 | #ifdef CONFIG_SYS_PUAPAR |
| 615 | MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 616 | #endif |
| 617 | |
Michael Durrant | dfc2b76 | 2010-01-20 19:33:02 -0600 | [diff] [blame] | 618 | #if defined(CONFIG_SYS_DDRD) |
| 619 | MCFGPIO_DDRD = CONFIG_SYS_DDRD; |
| 620 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 621 | #ifdef CONFIG_SYS_DDRUA |
| 622 | MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 623 | #endif |
| 624 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 625 | /* FlexBus Chipselect */ |
| 626 | init_fbcs(); |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 627 | |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 628 | #endif /* CONFIG_MONITOR_IS_IN_RAM */ |
Heiko Schocher | 9acb626 | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 629 | |
| 630 | /* defer enabling cache until boot (see do_go) */ |
| 631 | /* icache_enable(); */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | /* |
| 635 | * initialize higher level parts of CPU like timers |
| 636 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 637 | int cpu_init_r(void) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 638 | { |
| 639 | return (0); |
| 640 | } |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 641 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 642 | void uart_port_conf(int port) |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 643 | { |
| 644 | /* Setup Ports: */ |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 645 | switch (port) { |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 646 | case 0: |
| 647 | MCFGPIO_PUAPAR &= 0xFc; |
| 648 | MCFGPIO_PUAPAR |= 0x03; |
| 649 | break; |
| 650 | case 1: |
| 651 | MCFGPIO_PUAPAR &= 0xF3; |
| 652 | MCFGPIO_PUAPAR |= 0x0C; |
| 653 | break; |
| 654 | case 2: |
| 655 | MCFGPIO_PASPAR &= 0xFF0F; |
| 656 | MCFGPIO_PASPAR |= 0x00A0; |
| 657 | break; |
| 658 | } |
| 659 | } |
TsiChung Liew | f3962d3 | 2008-10-21 13:47:54 +0000 | [diff] [blame] | 660 | |
| 661 | #if defined(CONFIG_CMD_NET) |
| 662 | int fecpin_setclear(struct eth_device *dev, int setclear) |
| 663 | { |
| 664 | if (setclear) { |
| 665 | MCFGPIO_PASPAR |= 0x0F00; |
| 666 | MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; |
| 667 | } else { |
| 668 | MCFGPIO_PASPAR &= 0xF0FF; |
| 669 | MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; |
| 670 | } |
| 671 | return 0; |
| 672 | } |
| 673 | #endif /* CONFIG_CMD_NET */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 674 | #endif |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 675 | |
| 676 | #if defined(CONFIG_M5249) |
| 677 | /* |
| 678 | * Breath some life into the CPU... |
| 679 | * |
| 680 | * Set up the memory map, |
| 681 | * initialize a bunch of registers, |
| 682 | * initialize the UPM's |
| 683 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 684 | void cpu_init_f(void) |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 685 | { |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 686 | /* |
| 687 | * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 688 | * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins |
| 689 | * which is their primary function. |
| 690 | * ~Jeremy |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 691 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 692 | mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); |
| 693 | mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); |
| 694 | mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); |
| 695 | mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); |
| 696 | mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); |
| 697 | mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 698 | |
| 699 | /* |
| 700 | * dBug Compliance: |
| 701 | * You can verify these values by using dBug's 'ird' |
| 702 | * (Internal Register Display) command |
| 703 | * ~Jeremy |
| 704 | * |
Wolfgang Denk | 977b50f | 2006-05-10 17:43:20 +0200 | [diff] [blame] | 705 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 706 | mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 707 | mbar_writeByte(MCFSIM_SYPCR, 0x00); |
| 708 | mbar_writeByte(MCFSIM_SWIVR, 0x0f); |
| 709 | mbar_writeByte(MCFSIM_SWSR, 0x00); |
| 710 | mbar_writeLong(MCFSIM_IMR, 0xfffffbff); |
| 711 | mbar_writeByte(MCFSIM_SWDICR, 0x00); |
| 712 | mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); |
| 713 | mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); |
| 714 | mbar_writeByte(MCFSIM_I2CICR, 0x00); |
| 715 | mbar_writeByte(MCFSIM_UART1ICR, 0x00); |
| 716 | mbar_writeByte(MCFSIM_UART2ICR, 0x00); |
| 717 | mbar_writeByte(MCFSIM_ICR6, 0x00); |
| 718 | mbar_writeByte(MCFSIM_ICR7, 0x00); |
| 719 | mbar_writeByte(MCFSIM_ICR8, 0x00); |
| 720 | mbar_writeByte(MCFSIM_ICR9, 0x00); |
| 721 | mbar_writeByte(MCFSIM_QSPIICR, 0x00); |
| 722 | |
| 723 | mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); |
Wolfgang Denk | 977b50f | 2006-05-10 17:43:20 +0200 | [diff] [blame] | 724 | mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 725 | mbar2_writeByte(MCFSIM_SPURVEC, 0x00); |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 726 | mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 727 | |
| 728 | /* Setup interrupt priorities for gpio7 */ |
| 729 | /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ |
| 730 | |
| 731 | /* IDE Config registers */ |
| 732 | mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); |
| 733 | mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); |
| 734 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 735 | /* FlexBus Chipselect */ |
| 736 | init_fbcs(); |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 737 | |
| 738 | /* enable instruction cache now */ |
| 739 | icache_enable(); |
| 740 | } |
| 741 | |
| 742 | /* |
| 743 | * initialize higher level parts of CPU like timers |
| 744 | */ |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 745 | int cpu_init_r(void) |
stroese | 8c725b9 | 2004-12-16 18:09:49 +0000 | [diff] [blame] | 746 | { |
| 747 | return (0); |
| 748 | } |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 749 | |
TsiChung Liew | 52affe0 | 2010-03-09 19:17:52 -0600 | [diff] [blame] | 750 | void uart_port_conf(int port) |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 751 | { |
TsiChungLiew | 83ec20b | 2007-08-15 19:21:21 -0500 | [diff] [blame] | 752 | } |
| 753 | #endif /* #if defined(CONFIG_M5249) */ |