blob: 6ea58074bb5b260b1ccf55a6d30e0b36466832ff [file] [log] [blame]
Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42#define CONFIG_CPM2 1 /* has CPM2 */
43#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050044#define CONFIG_MPC8560 1
Dan Malek35171dc2007-01-05 09:15:34 +010045
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
47
Wolfgang Denkf1152f82007-07-06 02:50:19 +020048#define CONFIG_PCI /* PCI ethernet support */
49#define CONFIG_TSEC_ENET /* tsec ethernet support*/
50#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
Dan Malek35171dc2007-01-05 09:15:34 +010051#define CONFIG_ENV_OVERWRITE
Dan Malek35171dc2007-01-05 09:15:34 +010052
Kumar Gala572b13a2008-01-16 09:11:53 -060053#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Dan Malek35171dc2007-01-05 09:15:34 +010054
55/* sysclk for MPC85xx
56 */
57
Wolfgang Denkf1152f82007-07-06 02:50:19 +020058#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
Dan Malek35171dc2007-01-05 09:15:34 +010059
60/* Blinkin' LEDs for Robert :-)
61*/
62#define CONFIG_SHOW_ACTIVITY 1
63
64/*
65 * These can be toggled for performance analysis, otherwise use default.
66 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020067#define CONFIG_L2_CACHE /* toggle L2 cache */
68#define CONFIG_BTB /* toggle branch predition */
Dan Malek35171dc2007-01-05 09:15:34 +010069
Wolfgang Denk53677ef2008-05-20 16:00:29 +020070#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Dan Malek35171dc2007-01-05 09:15:34 +010071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
73#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
74#define CONFIG_SYS_MEMTEST_END 0x00400000
Dan Malek35171dc2007-01-05 09:15:34 +010075
76
Wolfgang Denkf1152f82007-07-06 02:50:19 +020077/* Localbus connector. There are many options that can be
Dan Malek35171dc2007-01-05 09:15:34 +010078 * connected here, including sdram or lots of flash.
79 * This address, however, is used to configure a 256M local bus
80 * window that includes the Config latch below.
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
83#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
Dan Malek35171dc2007-01-05 09:15:34 +010084
85/* There are various flash options used, we configure for the largest,
86 * which is 64Mbytes. The CFI works fine and will discover the proper
87 * sizes.
88 */
Wolfgang Denkee152982007-05-31 17:20:09 +020089#ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020091#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020093#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
95#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
Dan Malek35171dc2007-01-05 09:15:34 +010096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020098#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
100#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
101#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
Dan Malek35171dc2007-01-05 09:15:34 +0100102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Dan Malek35171dc2007-01-05 09:15:34 +0100104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_FLASH_PROTECTION
Dan Malek35171dc2007-01-05 09:15:34 +0100106
107/* The configuration latch is Chip Select 1.
108 * It's an 8-bit latch in the lower 8 bits of the word.
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
111#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
112#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
Dan Malek35171dc2007-01-05 09:15:34 +0100113
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200114#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dan Malek35171dc2007-01-05 09:15:34 +0100115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
117#define CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100118#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#undef CONFIG_SYS_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100120#endif
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#ifdef CONFIG_SYS_RAMBOOT
123#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
Dan Malek35171dc2007-01-05 09:15:34 +0100124#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Dan Malek35171dc2007-01-05 09:15:34 +0100126#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
128#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
129#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Dan Malek35171dc2007-01-05 09:15:34 +0100130
Kumar Gala0e7927d2008-08-27 01:04:07 -0500131/* DDR Setup */
132#define CONFIG_FSL_DDR1
133#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
134#define CONFIG_DDR_SPD
135#undef CONFIG_FSL_DDR_INTERACTIVE
Dan Malek35171dc2007-01-05 09:15:34 +0100136
Kumar Gala0e7927d2008-08-27 01:04:07 -0500137#undef CONFIG_DDR_ECC /* only for ECC DDR module */
138#undef CONFIG_DDR_DLL /* possible DLL fix needed */
139#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
Dan Malek35171dc2007-01-05 09:15:34 +0100140
Kumar Gala0e7927d2008-08-27 01:04:07 -0500141#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
144#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Dan Malek35171dc2007-01-05 09:15:34 +0100145
Kumar Gala0e7927d2008-08-27 01:04:07 -0500146#define CONFIG_NUM_DDR_CONTROLLERS 1
147#define CONFIG_DIMM_SLOTS_PER_CTLR 1
148#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
149
150/* I2C addresses of SPD EEPROMs */
151#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
Dan Malek35171dc2007-01-05 09:15:34 +0100152
153#undef CONFIG_CLOCKS_IN_MHZ
154
155/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
157#define CONFIG_SYS_OR2_PRELIM 0xfc006901
158#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
159#define CONFIG_SYS_LBC_LBCR 0x00000000
160#define CONFIG_SYS_LBC_LSRT 0x20000000
161#define CONFIG_SYS_LBC_MRTPR 0x20000000
162#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
163#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
164#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
165#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
166#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
Dan Malek35171dc2007-01-05 09:15:34 +0100167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_INIT_RAM_LOCK 1
169#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
170#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Dan Malek35171dc2007-01-05 09:15:34 +0100171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Dan Malek35171dc2007-01-05 09:15:34 +0100175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
177#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dan Malek35171dc2007-01-05 09:15:34 +0100178
179/* Serial Port */
180#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_NS16550
182#define CONFIG_SYS_NS16550_SERIAL
183#define CONFIG_SYS_NS16550_REG_SIZE 1
184#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dan Malek35171dc2007-01-05 09:15:34 +0100185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BAUDRATE_TABLE \
Dan Malek35171dc2007-01-05 09:15:34 +0100187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
190#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Dan Malek35171dc2007-01-05 09:15:34 +0100191
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200192#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500193#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
195#ifdef CONFIG_SYS_HUSH_PARSER
196#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dan Malek35171dc2007-01-05 09:15:34 +0100197#endif
198
Wolfgang Denke1893812007-10-12 15:49:39 +0200199/*
200 * I2C
201 */
Dan Malek35171dc2007-01-05 09:15:34 +0100202#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200203#define CONFIG_HARD_I2C /* I2C with hardware support*/
Dan Malek35171dc2007-01-05 09:15:34 +0100204#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
206#define CONFIG_SYS_I2C_SLAVE 0x7F
207#undef CONFIG_SYS_I2C_NOPROBES
208#define CONFIG_SYS_I2C_OFFSET 0x3000
Dan Malek35171dc2007-01-05 09:15:34 +0100209
Wolfgang Denke1893812007-10-12 15:49:39 +0200210/* I2C RTC */
211#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Wolfgang Denke1893812007-10-12 15:49:39 +0200213
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200214/* I2C EEPROM. AT24C32, we keep our environment in here.
Dan Malek35171dc2007-01-05 09:15:34 +0100215*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
217#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
218#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
219#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Dan Malek35171dc2007-01-05 09:15:34 +0100220
221/*
222 * Standard 8555 PCI mapping.
223 * Addresses are mapped 1-1.
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
226#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
227#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
228#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
229#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
230#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
233#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
234#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
235#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
236#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
237#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Dan Malek35171dc2007-01-05 09:15:34 +0100238
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200239#if defined(CONFIG_PCI) /* PCI Ethernet card */
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200240#define CONFIG_MPC85XX_PCI2 1
Dan Malek35171dc2007-01-05 09:15:34 +0100241#define CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200242#define CONFIG_PCI_PNP /* do pci plug-and-play */
Dan Malek35171dc2007-01-05 09:15:34 +0100243
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200244#define CONFIG_EEPRO100
245#define CONFIG_TULIP
Dan Malek35171dc2007-01-05 09:15:34 +0100246
247#if !defined(CONFIG_PCI_PNP)
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200248 #define PCI_ENET0_IOADDR 0xe0000000
249 #define PCI_ENET0_MEMADDR 0xe0000000
250 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Dan Malek35171dc2007-01-05 09:15:34 +0100251#endif
252
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200253#define CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Dan Malek35171dc2007-01-05 09:15:34 +0100255
256#endif /* CONFIG_PCI */
257
258#if defined(CONFIG_TSEC_ENET)
259
260#ifndef CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200261#define CONFIG_NET_MULTI 1
Dan Malek35171dc2007-01-05 09:15:34 +0100262#endif
263
264#define CONFIG_MII 1 /* MII PHY management */
265
Kim Phillips255a35772007-05-16 16:52:19 -0500266#define CONFIG_TSEC1 1
267#define CONFIG_TSEC1_NAME "TSEC0"
268#define CONFIG_TSEC2 1
269#define CONFIG_TSEC2_NAME "TSEC1"
Dan Malek35171dc2007-01-05 09:15:34 +0100270
271#define TSEC1_PHY_ADDR 2
272#define TSEC2_PHY_ADDR 4
273#define TSEC1_PHYIDX 0
274#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500275#define TSEC1_FLAGS TSEC_GIGABIT
276#define TSEC2_FLAGS TSEC_GIGABIT
Dan Malek35171dc2007-01-05 09:15:34 +0100277#define CONFIG_ETHPRIME "TSEC0"
278
279#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
280
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200281#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
282#undef CONFIG_ETHER_NONE /* define if ether on something else */
283#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
Dan Malek35171dc2007-01-05 09:15:34 +0100284
285#if (CONFIG_ETHER_INDEX == 2)
286 /*
287 * - Rx-CLK is CLK13
288 * - Tx-CLK is CLK14
289 * - Select bus for bd/buffers
290 * - Full duplex
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
293 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
294 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
Dan Malek35171dc2007-01-05 09:15:34 +0100295#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
Dan Malek35171dc2007-01-05 09:15:34 +0100297#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 #define CONFIG_SYS_FCC_PSMR 0
Dan Malek35171dc2007-01-05 09:15:34 +0100299#endif
300 #define FETH2_RST 0x01
301#elif (CONFIG_ETHER_INDEX == 3)
302 /* need more definitions here for FE3 */
303 #define FETH3_RST 0x80
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200304#endif /* CONFIG_ETHER_INDEX */
Dan Malek35171dc2007-01-05 09:15:34 +0100305
306/* MDIO is done through the TSEC0 control.
307*/
308#define CONFIG_MII /* MII PHY management */
309#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
310
311#endif
312
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200313/* Environment - default config is in flash, see below */
314#if 0 /* in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200315# define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200316# define CONFIG_ENV_OFFSET 0
317# define CONFIG_ENV_SIZE 2048
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200318#else /* in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200319# define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkee152982007-05-31 17:20:09 +0200320# ifdef CONFIG_STXSSA_4M
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200321# define CONFIG_ENV_SECT_SIZE 0x20000
Wolfgang Denkee152982007-05-31 17:20:09 +0200322# else /* default configuration - 64 MiB flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200323# define CONFIG_ENV_SECT_SIZE 0x40000
Wolfgang Denkee152982007-05-31 17:20:09 +0200324# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200326# define CONFIG_ENV_SIZE 0x4000
327# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
328# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Dan Malek35171dc2007-01-05 09:15:34 +0100329#endif
330
Dan Malek35171dc2007-01-05 09:15:34 +0100331#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dan Malek35171dc2007-01-05 09:15:34 +0100333
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200334#define CONFIG_TIMESTAMP /* Print image info with ts */
335
Jon Loeliger2835e512007-06-13 13:22:08 -0500336
337/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500338 * BOOTP options
339 */
340#define CONFIG_BOOTP_BOOTFILESIZE
341#define CONFIG_BOOTP_BOOTPATH
342#define CONFIG_BOOTP_GATEWAY
343#define CONFIG_BOOTP_HOSTNAME
344
345
346/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500347 * Command line configuration.
348 */
349#include <config_cmd_default.h>
350
Wolfgang Denke1893812007-10-12 15:49:39 +0200351#define CONFIG_CMD_DATE
352#define CONFIG_CMD_DHCP
353#define CONFIG_CMD_EEPROM
Jon Loeliger2835e512007-06-13 13:22:08 -0500354#define CONFIG_CMD_I2C
Wolfgang Denke1893812007-10-12 15:49:39 +0200355#define CONFIG_CMD_NFS
356#define CONFIG_CMD_PING
357#define CONFIG_CMD_SNTP
Becky Bruce199e2622010-06-17 11:37:25 -0500358#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500359
360#if defined(CONFIG_PCI)
361 #define CONFIG_CMD_PCI
Dan Malek35171dc2007-01-05 09:15:34 +0100362#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500363
364#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
365 #define CONFIG_CMD_MII
366#endif
367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500369 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500370 #undef CONFIG_CMD_LOADS
371#else
372 #define CONFIG_CMD_ELF
373#endif
374
Dan Malek35171dc2007-01-05 09:15:34 +0100375
376#undef CONFIG_WATCHDOG /* watchdog disabled */
377
378/*
379 * Miscellaneous configurable options
380 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_LONGHELP /* undef to save memory */
382#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
Jon Loeligeref0df522007-07-04 22:31:07 -0500383#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100385#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dan Malek35171dc2007-01-05 09:15:34 +0100387#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
389#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
390#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
391#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
392#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Dan Malek35171dc2007-01-05 09:15:34 +0100393
394/*
395 * For booting Linux, the board info and command line data
396 * have to be in the first 8 MB of memory, since this is
397 * the maximum mapped by the Linux kernel during initialization.
398 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dan Malek35171dc2007-01-05 09:15:34 +0100400
Jon Loeligeref0df522007-07-04 22:31:07 -0500401#if defined(CONFIG_CMD_KGDB)
Dan Malek35171dc2007-01-05 09:15:34 +0100402#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
403#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
404#endif
405
406/*Note: change below for your network setting!!! */
407#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500408#define CONFIG_HAS_ETH0
Dan Malek35171dc2007-01-05 09:15:34 +0100409#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
410#define CONFIG_HAS_ETH1
411#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
412#define CONFIG_HAS_ETH2
413#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
414#endif
415
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200416/*
417 * Environment in EEPROM is compatible with different flash sector sizes,
418 * but only little space is available, so we use a very simple setup.
419 * With environment in flash, we use a more powerful default configuration.
420 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200421#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200422
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200423#define CONFIG_BAUDRATE 38400
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200424
425#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
426#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
427#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200428#define CONFIG_SERVERIP 192.168.85.1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200429#define CONFIG_IPADDR 192.168.85.60
Dan Malek35171dc2007-01-05 09:15:34 +0100430#define CONFIG_GATEWAYIP 192.168.85.1
431#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200432#define CONFIG_HOSTNAME STX_SSA
433#define CONFIG_ROOTPATH /gppproot
434#define CONFIG_BOOTFILE uImage
Dan Malek35171dc2007-01-05 09:15:34 +0100435#define CONFIG_LOADADDR 0x1000000
436
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200437#else /* ENV IS IN FLASH -- use a full-blown envionment */
438
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200439#define CONFIG_BAUDRATE 115200
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200440
441#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
442
443#define CONFIG_PREBOOT "echo;" \
444 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
445 "echo"
446
447#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
448
449#define CONFIG_EXTRA_ENV_SETTINGS \
450 "hostname=gp3ssa\0" \
451 "bootfile=/tftpboot/gp3ssa/uImage\0" \
452 "loadaddr=400000\0" \
453 "netdev=eth0\0" \
454 "consdev=ttyS1\0" \
455 "nfsargs=setenv bootargs root=/dev/nfs rw " \
456 "nfsroot=$serverip:$rootpath\0" \
457 "ramargs=setenv bootargs root=/dev/ram rw\0" \
458 "addip=setenv bootargs $bootargs " \
459 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
460 ":$hostname:$netdev:off panic=1\0" \
461 "addcons=setenv bootargs $bootargs " \
462 "console=$consdev,$baudrate\0" \
463 "flash_nfs=run nfsargs addip addcons;" \
464 "bootm $kernel_addr\0" \
465 "flash_self=run ramargs addip addcons;" \
466 "bootm $kernel_addr $ramdisk_addr\0" \
467 "net_nfs=tftp $loadaddr $bootfile;" \
468 "run nfsargs addip addcons;bootm\0" \
469 "rootpath=/opt/eldk/ppc_85xx\0" \
470 "kernel_addr=FC000000\0" \
471 "ramdisk_addr=FC200000\0" \
472 ""
473#define CONFIG_BOOTCOMMAND "run flash_self"
474
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200475#endif /* CONFIG_ENV_IS_IN_EEPROM */
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200476
Dan Malek35171dc2007-01-05 09:15:34 +0100477#endif /* __CONFIG_H */