Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / ee6b3c54e96917411e10f7eb3f249e339d1536c3 / . / arch / arm / dts / zynqmp-m-a2197-03-revA.dts
blob: 25d87532be770e196cbf7ed44f92aaa8a36c70ac [file] [log] [blame]
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
17 compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA",
18 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci0;
26 mmc1 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = <&eeprom>;
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
45 };
46
47 ina226-vcc-aux {
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
50 };
51 ina226-vcc-ram {
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
54 };
55 ina226-vcc1v1-lp4 {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
58 };
59 ina226-vcc1v2-lp4 {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
62 };
63 ina226-vdd1-1v8-lp4 {
64 compatible = "iio-hwmon";
65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
66 };
67};
68
69&qspi {
70 status = "okay";
71 is-dual = <1>;
72 flash@0 {
73 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x0>;
77 spi-tx-bus-width = <1>;
78 spi-rx-bus-width = <4>;
79 spi-max-frequency = <108000000>;
80 };
81};
82
83&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
84 status = "okay";
85 non-removable;
86 disable-wp;
87 bus-width = <8>;
Michal Simek01a6da12020-07-22 17:42:43 +0200[diff] [blame]88 xlnx,mio-bank = <0>; /* FIXME tap delay */
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]89};
90
91&uart0 { /* uart0 MIO38-39 */
92 status = "okay";
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]93};
94
95&uart1 { /* uart1 MIO40-41 */
96 status = "okay";
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]97};
98
99&sdhci1 { /* sd1 MIO45-51 cd in place */
100 status = "disable";
101 no-1-8-v;
102 disable-wp;
Michal Simek01a6da12020-07-22 17:42:43 +0200[diff] [blame]103 xlnx,mio-bank = <1>;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]104};
105
106&gem0 {
107 status = "okay";
108 phy-handle = <&phy0>;
109 phy-mode = "sgmii";
110 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
111 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
112 reg = <0>;
113 };
114};
115
116&gpio {
117 status = "okay";
118 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
119 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
120 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
121 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
122 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
123 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
124 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
125 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
126 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
127 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
128 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
129 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
130 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
131 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
132 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
133 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
134 "", "", "", "", "", /* 78 - 79 */
135 "", "", "", "", "", /* 80 - 84 */
136 "", "", "", "", "", /* 85 -89 */
137 "", "", "", "", "", /* 90 - 94 */
138 "", "", "", "", "", /* 95 - 99 */
139 "", "", "", "", "", /* 100 - 104 */
140 "", "", "", "", "", /* 105 - 109 */
141 "", "", "", "", "", /* 110 - 114 */
142 "", "", "", "", "", /* 115 - 119 */
143 "", "", "", "", "", /* 120 - 124 */
144 "", "", "", "", "", /* 125 - 129 */
145 "", "", "", "", "", /* 130 - 134 */
146 "", "", "", "", "", /* 135 - 139 */
147 "", "", "", "", "", /* 140 - 144 */
148 "", "", "", "", "", /* 145 - 149 */
149 "", "", "", "", "", /* 150 - 154 */
150 "", "", "", "", "", /* 155 - 159 */
151 "", "", "", "", "", /* 160 - 164 */
152 "", "", "", "", "", /* 165 - 169 */
153 "", "", "", ""; /* 170 - 174 */
154};
155
156&i2c0 { /* MIO 34-35 - can't stay here */
157 status = "okay";
158 clock-frequency = <400000>;
159 i2c-mux@74 { /* u46 */
160 compatible = "nxp,pca9548";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <0x74>;
164 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
165 i2c@0 { /* PMBUS must be enabled via SW21 */
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <0>;
169 reg_vcc1v2_lp4: tps544@15 { /* u97 */
170 compatible = "ti,tps544b25";
171 reg = <0x15>;
172 };
173 reg_vcc1v1_lp4: tps544@16 { /* u95 */
174 compatible = "ti,tps544b25";
175 reg = <0x16>;
176 };
177 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
178 compatible = "ti,tps544b25";
179 reg = <0x17>;
180 };
181 /* UTIL_PMBUS connection */
182 reg_vcc1v8: tps544@13 { /* u92 */
183 compatible = "ti,tps544b25";
184 reg = <0x13>;
185 };
186 reg_vcc3v3: tps544@14 { /* u93 */
187 compatible = "ti,tps544b25";
188 reg = <0x14>;
189 };
190 reg_vcc5v0: tps544@1e { /* u94 */
191 compatible = "ti,tps544b25";
192 reg = <0x1e>;
193 };
194 reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */
195 compatible = "ti,tps544b25";
196 reg = <0x17>; /* FIXME wrong in schematics */
197 };
198 };
199 i2c@1 { /* PMBUS_INA226 */
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <1>;
203 vcc_aux: ina226@42 { /* u86 */
204 compatible = "ti,ina226";
205 #io-channel-cells = <1>;
206 label = "ina226-vcc-aux";
207 reg = <0x42>;
208 shunt-resistor = <5000>;
209 };
210 vcc_ram: ina226@43 { /* u81 */
211 compatible = "ti,ina226";
212 #io-channel-cells = <1>;
213 label = "ina226-vcc-ram";
214 reg = <0x43>;
215 shunt-resistor = <5000>;
216 };
217 vcc1v1_lp4: ina226@46 { /* u96 */
218 compatible = "ti,ina226";
219 #io-channel-cells = <1>;
220 label = "ina226-vcc1v1-lp4";
221 reg = <0x46>;
222 shunt-resistor = <5000>;
223 };
224 vcc1v2_lp4: ina226@47 { /* u98 */
225 compatible = "ti,ina226";
226 #io-channel-cells = <1>;
227 label = "ina226-vcc1v2-lp4";
228 reg = <0x47>;
229 shunt-resistor = <5000>;
230 };
231 vdd1_1v8_lp4: ina226@48 { /* u100 */
232 compatible = "ti,ina226";
233 #io-channel-cells = <1>;
234 label = "ina226-vdd1-1v8-lp4";
235 reg = <0x48>;
236 shunt-resistor = <5000>;
237 };
238 };
239 i2c@2 { /* PMBUS1 */
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <2>;
243 reg_vccint: tps53681@c0 { /* u69 */
244 compatible = "ti,tps53681", "ti,tps53679";
245 reg = <0xc0>;
246 };
247 reg_vcc_pmc: tps544@7 { /* u80 */
248 compatible = "ti,tps544b25";
249 reg = <0x7>;
250 };
251 reg_vcc_ram: tps544@8 { /* u82 */
252 compatible = "ti,tps544b25";
253 reg = <0x8>;
254 };
255 reg_vcc_pslp: tps544@9 { /* u83 */
256 compatible = "ti,tps544b25";
257 reg = <0x9>;
258 };
259 reg_vcc_psfp: tps544@a { /* u84 */
260 compatible = "ti,tps544b25";
261 reg = <0xa>;
262 };
263 reg_vccaux: tps544@d { /* u85 */
264 compatible = "ti,tps544b25";
265 reg = <0xd>;
266 };
267 reg_vccaux_pmc: tps544@e { /* u87 */
268 compatible = "ti,tps544b25";
269 reg = <0xe>;
270 };
271 reg_vcco_500: tps544@f { /* u88 */
272 compatible = "ti,tps544b25";
273 reg = <0xf>;
274 };
275 reg_vcco_501: tps544@10 { /* u89 */
276 compatible = "ti,tps544b25";
277 reg = <0x10>;
278 };
279 reg_vcco_502: tps544@11 { /* u90 */
280 compatible = "ti,tps544b25";
281 reg = <0x11>;
282 };
283 reg_vcco_503: tps544@12 { /* u91 */
284 compatible = "ti,tps544b25";
285 reg = <0x12>;
286 };
287 };
288 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
289 #address-cells = <1>;
290 #size-cells = <0>;
291 /* reg = <3>; */
292 };
293 i2c@4 { /* LP_I2C_SM */
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <4>;
297 /* connected to U20G */
298 };
299 i2c@5 { /* DDR4_SODIMM */
300 #address-cells = <1>;
301 #size-cells = <0>;
302 reg = <5>;
303 };
304 };
305};
306
307/* TODO sysctrl via J239 */
308/* TODO samtec J212G/H via J242 */
309/* TODO teensy via U30 PCA9543A bus 1 */
310&i2c1 { /* i2c1 MIO 36-37 */
311 status = "okay";
312 clock-frequency = <400000>;
313
314 /* Must be enabled via J242 */
315 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
316 compatible = "atmel,24c02";
317 reg = <0x51>;
318 };
319
320 i2c-mux@74 { /* u47 */
321 compatible = "nxp,pca9548";
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <0x74>;
325 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
326 dc_i2c: i2c@0 { /* DC_I2C */
327 #address-cells = <1>;
328 #size-cells = <0>;
329 reg = <0>;
330 /* Use for storing information about SC board */
331 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
332 compatible = "atmel,24c08";
333 reg = <0x54>;
334 };
335 si570_ref_clk: clock-generator@5d { /* u26 */
336 #clock-cells = <0>;
337 compatible = "silabs,si570";
338 reg = <0x5d>; /* FIXME addr */
339 temperature-stability = <50>;
Michal Simeka34a12f2021-03-09 12:43:42 +0100[diff] [blame]340 factory-fout = <33333333>;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]341 clock-frequency = <33333333>;
342 clock-output-names = "REF_CLK"; /* FIXME */
Michal Simeka34a12f2021-03-09 12:43:42 +0100[diff] [blame]343 silabs,skip-recall;
Michal Simek3d5c9062019-06-28 13:53:45 +0200[diff] [blame]344 };
345 /* Connection via Samtec U20D */
346 /* Use for storing information about X-PRC card */
347 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
348 compatible = "atmel,24c02";
349 reg = <0x52>;
350 };
351
352 /* Use for setting up certain features on X-PRC card */
353 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
354 compatible = "nxp,pca9534";
355 reg = <0x22>;
356 gpio-controller; /* IRQ not connected */
357 #gpio-cells = <2>;
358 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
359 "", "", "", "";
360 gtr_sel0 {
361 gpio-hog;
362 gpios = <0 0>;
363 input; /* FIXME add meaning */
364 line-name = "sw4_1";
365 };
366 gtr_sel1 {
367 gpio-hog;
368 gpios = <1 0>;
369 input; /* FIXME add meaning */
370 line-name = "sw4_2";
371 };
372 gtr_sel2 {
373 gpio-hog;
374 gpios = <2 0>;
375 input; /* FIXME add meaning */
376 line-name = "sw4_3";
377 };
378 gtr_sel3 {
379 gpio-hog;
380 gpios = <3 0>;
381 input; /* FIXME add meaning */
382 line-name = "sw4_4";
383 };
384 };
385 };
386 i2c@2 { /* C0_DDR4 */
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <2>;
390 si570_c0_ddr4: clock-generator@55 { /* u4 */
391 #clock-cells = <0>;
392 compatible = "silabs,si570";
393 reg = <0x55>;
394 temperature-stability = <50>;
395 factory-fout = <30000000>;
396 clock-frequency = <30000000>;
397 clock-output-names = "C0_DD4_SI570_CLK";
398 };
399 };
400 i2c@3 { /* C1_SODIMM */
401 #address-cells = <1>;
402 #size-cells = <0>;
403 reg = <3>;
404 si570_c1_lp4: clock-generator@55 { /* u7 */
405 #clock-cells = <0>;
406 compatible = "silabs,si570";
407 reg = <0x55>;
408 temperature-stability = <50>;
409 factory-fout = <30000000>;
410 clock-frequency = <30000000>;
411 clock-output-names = "C1_SODIMM_SI570_CLK";
412 };
413 };
414 i2c@4 { /* C2_QDRIV */
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <4>;
418 si570_c2_lp4: clock-generator@55 { /* u10 */
419 #clock-cells = <0>;
420 compatible = "silabs,si570";
421 reg = <0x55>;
422 temperature-stability = <50>;
423 factory-fout = <30000000>;
424 clock-frequency = <30000000>;
425 clock-output-names = "C2_QDRIV_SI570_CLK";
426 };
427 };
428 i2c@5 { /* C3_DDR4 */
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <5>;
432 si570_c3_lp4: clock-generator@55 { /* u15 */
433 #clock-cells = <0>;
434 compatible = "silabs,si570";
435 reg = <0x55>;
436 temperature-stability = <50>;
437 factory-fout = <30000000>;
438 clock-frequency = <30000000>;
439 clock-output-names = "C3_LP4_SI570_CLK";
440 };
441 };
442 i2c@6 { /* HSDP_SI570 */
443 #address-cells = <1>;
444 #size-cells = <0>;
445 reg = <6>;
446 si570_hsdp: clock-generator@5d { /* u19 */
447 #clock-cells = <0>;
448 compatible = "silabs,si570";
449 reg = <0x5d>;
450 temperature-stability = <50>;
451 factory-fout = <156250000>;
452 clock-frequency = <156250000>;
453 clock-output-names = "HSDP_SI570";
454 };
455 };
456 };
457};
458
459&usb0 {
460 status = "okay";
461 xlnx,usb-polarity = <0>;
462 xlnx,usb-reset-mode = <0>;
463};
464
465&dwc3_0 {
466 status = "okay";
467 dr_mode = "host";
468 /* dr_mode = "peripheral"; */
469 maximum-speed = "high-speed";
470};
471
472&usb1 {
473 status = "disabled"; /* not at mem board */
474 xlnx,usb-polarity = <0>;
475 xlnx,usb-reset-mode = <0>;
476};
477
478&dwc3_1 {
479 /delete-property/ phy-names ;
480 /delete-property/ phys ;
481 maximum-speed = "high-speed";
482 snps,dis_u2_susphy_quirk ;
483 snps,dis_u3_susphy_quirk ;
484 status = "disabled";
485};