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Valentin Longchamp877bfe32013-10-18 11:47:24 +02001/*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * Copyright 2009-2011 Freescale Semiconductor, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <i2c.h>
12#include <hwconfig.h>
13#include <asm/mmu.h>
York Sun5614e712013-09-30 09:22:09 -070014#include <fsl_ddr_sdram.h>
15#include <fsl_ddr_dimm_params.h>
Valentin Longchamp877bfe32013-10-18 11:47:24 +020016
17void fsl_ddr_board_options(memctl_options_t *popts,
18 dimm_params_t *pdimm,
19 unsigned int ctrl_num)
20{
21 if (ctrl_num) {
22 printf("Wrong parameter for controller number %d", ctrl_num);
23 return;
24 }
25
26 /* automatic calibration for nb of cycles between read and DQS pre */
27 popts->cpo_override = 0xFF;
28
29 /* 1/2 clk delay between wr command and data strobe */
30 popts->write_data_delay = 4;
31 /* clk lauched 1/2 applied cylcle after address command */
32 popts->clk_adjust = 4;
33 /* 1T timing: command/address held for only 1 cycle */
34 popts->twot_en = 0;
35
36 /* we have only one module, half str should be OK */
37 popts->half_strength_driver_enable = 1;
38
Robert P. J. Day62a3b7d2016-07-15 13:44:45 -040039 /* wrlvl values overridden as recommended by ddr init func */
Valentin Longchamp877bfe32013-10-18 11:47:24 +020040 popts->wrlvl_override = 1;
41 popts->wrlvl_sample = 0xf;
42 popts->wrlvl_start = 0x6;
43
44 /* Enable ZQ calibration */
45 popts->zq_en = 1;
46
47 /* DHC_EN =1, ODT = 75 Ohm */
48 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
49}
50
51phys_size_t initdram(int board_type)
52{
53 phys_size_t dram_size = 0;
54
55 puts("Initializing with SPD\n");
56
57 dram_size = fsl_ddr_sdram();
58
59 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
60 dram_size *= 0x100000;
61
62 debug(" DDR: ");
63 return dram_size;
64}