Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Common functions for OMAP4 based boards |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Author : |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | #include <common.h> |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 31 | #include <asm/armv7.h> |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 32 | #include <asm/arch/cpu.h> |
| 33 | #include <asm/arch/sys_proto.h> |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 34 | #include <asm/sizes.h> |
Aneesh V | 095aea2 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 35 | #include <asm/arch/emif.h> |
Aneesh V | 080a46e | 2011-07-31 20:30:53 +0000 | [diff] [blame] | 36 | #include <asm/arch/gpio.h> |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 37 | #include "omap4_mux_data.h" |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 38 | |
Nishanth Menon | 93e3568 | 2010-11-19 11:19:40 -0500 | [diff] [blame] | 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 41 | u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; |
| 42 | |
Aneesh V | 25223a6 | 2011-07-21 09:29:29 -0400 | [diff] [blame] | 43 | static const struct gpio_bank gpio_bank_44xx[6] = { |
| 44 | { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, |
| 45 | { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX }, |
| 46 | { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX }, |
| 47 | { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX }, |
| 48 | { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX }, |
| 49 | { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX }, |
| 50 | }; |
| 51 | |
| 52 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; |
| 53 | |
Aneesh V | 8cf686e | 2011-07-21 09:10:27 -0400 | [diff] [blame] | 54 | #ifdef CONFIG_SPL_BUILD |
| 55 | /* |
| 56 | * We use static variables because global data is not ready yet. |
| 57 | * Initialized data is available in SPL right from the beginning. |
| 58 | * We would not typically need to save these parameters in regular |
| 59 | * U-Boot. This is needed only in SPL at the moment. |
| 60 | */ |
| 61 | u32 omap4_boot_device = BOOT_DEVICE_MMC1; |
| 62 | u32 omap4_boot_mode = MMCSD_MODE_FAT; |
| 63 | |
| 64 | u32 omap_boot_device(void) |
| 65 | { |
| 66 | return omap4_boot_device; |
| 67 | } |
| 68 | |
| 69 | u32 omap_boot_mode(void) |
| 70 | { |
| 71 | return omap4_boot_mode; |
| 72 | } |
| 73 | #endif |
| 74 | |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 75 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
| 76 | { |
| 77 | int i; |
| 78 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; |
| 79 | |
| 80 | for (i = 0; i < size; i++, pad++) |
| 81 | writew(pad->val, base + pad->offset); |
| 82 | } |
| 83 | |
| 84 | static void set_muxconf_regs_essential(void) |
| 85 | { |
| 86 | do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, |
| 87 | sizeof(core_padconf_array_essential) / |
| 88 | sizeof(struct pad_conf_entry)); |
| 89 | |
| 90 | do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, |
| 91 | sizeof(wkup_padconf_array_essential) / |
| 92 | sizeof(struct pad_conf_entry)); |
Aneesh V | d506719 | 2011-07-21 09:29:32 -0400 | [diff] [blame] | 93 | |
| 94 | /* gpio_wk7 is used for controlling TPS on 4460 */ |
| 95 | if (omap_revision() >= OMAP4460_ES1_0) |
| 96 | writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ); |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static void set_mux_conf_regs(void) |
| 100 | { |
| 101 | switch (omap4_hw_init_context()) { |
| 102 | case OMAP_INIT_CONTEXT_SPL: |
| 103 | set_muxconf_regs_essential(); |
| 104 | break; |
| 105 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: |
| 106 | set_muxconf_regs_non_essential(); |
| 107 | break; |
| 108 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 109 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 110 | set_muxconf_regs_essential(); |
| 111 | set_muxconf_regs_non_essential(); |
| 112 | break; |
| 113 | } |
| 114 | } |
| 115 | |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 116 | static u32 cortex_a9_rev(void) |
| 117 | { |
| 118 | |
| 119 | unsigned int rev; |
| 120 | |
| 121 | /* Read Main ID Register (MIDR) */ |
| 122 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); |
| 123 | |
| 124 | return rev; |
| 125 | } |
| 126 | |
| 127 | static void init_omap4_revision(void) |
| 128 | { |
| 129 | /* |
| 130 | * For some of the ES2/ES1 boards ID_CODE is not reliable: |
| 131 | * Also, ES1 and ES2 have different ARM revisions |
| 132 | * So use ARM revision for identification |
| 133 | */ |
| 134 | unsigned int arm_rev = cortex_a9_rev(); |
| 135 | |
| 136 | switch (arm_rev) { |
| 137 | case MIDR_CORTEX_A9_R0P1: |
| 138 | *omap4_revision = OMAP4430_ES1_0; |
| 139 | break; |
| 140 | case MIDR_CORTEX_A9_R1P2: |
| 141 | switch (readl(CONTROL_ID_CODE)) { |
| 142 | case OMAP4_CONTROL_ID_CODE_ES2_0: |
| 143 | *omap4_revision = OMAP4430_ES2_0; |
| 144 | break; |
| 145 | case OMAP4_CONTROL_ID_CODE_ES2_1: |
| 146 | *omap4_revision = OMAP4430_ES2_1; |
| 147 | break; |
| 148 | case OMAP4_CONTROL_ID_CODE_ES2_2: |
| 149 | *omap4_revision = OMAP4430_ES2_2; |
| 150 | break; |
| 151 | default: |
| 152 | *omap4_revision = OMAP4430_ES2_0; |
| 153 | break; |
| 154 | } |
| 155 | break; |
| 156 | case MIDR_CORTEX_A9_R1P3: |
| 157 | *omap4_revision = OMAP4430_ES2_3; |
| 158 | break; |
Aneesh V | 5ab12a9 | 2011-07-21 09:29:23 -0400 | [diff] [blame] | 159 | case MIDR_CORTEX_A9_R2P10: |
| 160 | *omap4_revision = OMAP4460_ES1_0; |
| 161 | break; |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 162 | default: |
| 163 | *omap4_revision = OMAP4430_SILICON_ID_INVALID; |
| 164 | break; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | void omap_rev_string(char *omap4_rev_string) |
| 169 | { |
| 170 | u32 omap4_rev = omap_revision(); |
| 171 | u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16; |
| 172 | u32 major_rev = (omap4_rev & 0x00000F00) >> 8; |
| 173 | u32 minor_rev = (omap4_rev & 0x000000F0) >> 4; |
| 174 | |
| 175 | sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev, |
| 176 | minor_rev); |
| 177 | } |
| 178 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 179 | /* |
| 180 | * Routine: s_init |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 181 | * Description: Does early system init of watchdog, muxing, andclocks |
| 182 | * Watchdog disable is done always. For the rest what gets done |
| 183 | * depends on the boot mode in which this function is executed |
| 184 | * 1. s_init of SPL running from SRAM |
| 185 | * 2. s_init of U-Boot running from FLASH |
| 186 | * 3. s_init of U-Boot loaded to SDRAM by SPL |
| 187 | * 4. s_init of U-Boot loaded to SDRAM by ROM code using the |
| 188 | * Configuration Header feature |
| 189 | * Please have a look at the respective functions to see what gets |
| 190 | * done in each of these cases |
| 191 | * This function is called with SRAM stack. |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 192 | */ |
| 193 | void s_init(void) |
| 194 | { |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 195 | init_omap4_revision(); |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 196 | watchdog_init(); |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 197 | set_mux_conf_regs(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 198 | #ifdef CONFIG_SPL_BUILD |
| 199 | preloader_console_init(); |
| 200 | #endif |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 201 | prcm_init(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 202 | #ifdef CONFIG_SPL_BUILD |
| 203 | /* For regular u-boot sdram_init() is called from dram_init() */ |
| 204 | sdram_init(); |
| 205 | #endif |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | /* |
| 209 | * Routine: wait_for_command_complete |
| 210 | * Description: Wait for posting to finish on watchdog |
| 211 | */ |
| 212 | void wait_for_command_complete(struct watchdog *wd_base) |
| 213 | { |
| 214 | int pending = 1; |
| 215 | do { |
| 216 | pending = readl(&wd_base->wwps); |
| 217 | } while (pending); |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Routine: watchdog_init |
| 222 | * Description: Shut down watch dogs |
| 223 | */ |
| 224 | void watchdog_init(void) |
| 225 | { |
| 226 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; |
| 227 | |
| 228 | writel(WD_UNLOCK1, &wd2_base->wspr); |
| 229 | wait_for_command_complete(wd2_base); |
| 230 | writel(WD_UNLOCK2, &wd2_base->wspr); |
| 231 | } |
| 232 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 233 | |
| 234 | /* |
| 235 | * This function finds the SDRAM size available in the system |
| 236 | * based on DMM section configurations |
| 237 | * This is needed because the size of memory installed may be |
| 238 | * different on different versions of the board |
| 239 | */ |
Aneesh V | 2ae610f | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 240 | u32 omap4_sdram_size(void) |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 241 | { |
| 242 | u32 section, i, total_size = 0, size, addr; |
| 243 | for (i = 0; i < 4; i++) { |
Aneesh V | 095aea2 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 244 | section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4); |
| 245 | addr = section & OMAP44XX_SYS_ADDR_MASK; |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 246 | /* See if the address is valid */ |
| 247 | if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && |
| 248 | (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { |
Aneesh V | 095aea2 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 249 | size = ((section & OMAP44XX_SYS_SIZE_MASK) >> |
| 250 | OMAP44XX_SYS_SIZE_SHIFT); |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 251 | size = 1 << size; |
| 252 | size *= SZ_16M; |
| 253 | total_size += size; |
| 254 | } |
| 255 | } |
| 256 | return total_size; |
| 257 | } |
| 258 | |
| 259 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 260 | /* |
| 261 | * Routine: dram_init |
| 262 | * Description: sets uboots idea of sdram size |
| 263 | */ |
| 264 | int dram_init(void) |
| 265 | { |
Aneesh V | 2ae610f | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 266 | sdram_init(); |
| 267 | gd->ram_size = omap4_sdram_size(); |
Steve Sakoman | 57b512b | 2010-09-29 20:59:51 -0700 | [diff] [blame] | 268 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | /* |
| 273 | * Print board information |
| 274 | */ |
| 275 | int checkboard(void) |
| 276 | { |
| 277 | puts(sysinfo.board_string); |
| 278 | return 0; |
| 279 | } |
| 280 | |
Steve Sakoman | 2ad853c | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 281 | /* |
| 282 | * This function is called by start_armboot. You can reliably use static |
| 283 | * data. Any boot-time function that require static data should be |
| 284 | * called from here |
| 285 | */ |
| 286 | int arch_cpu_init(void) |
| 287 | { |
Steve Sakoman | 2ad853c | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 288 | return 0; |
| 289 | } |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 290 | |
| 291 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 292 | void v7_outer_cache_enable(void) |
| 293 | { |
| 294 | set_pl310_ctrl_reg(1); |
| 295 | } |
| 296 | |
| 297 | void v7_outer_cache_disable(void) |
| 298 | { |
| 299 | set_pl310_ctrl_reg(0); |
| 300 | } |
| 301 | #endif |
Aneesh V | 13d4f9b | 2011-08-11 04:35:43 +0000 | [diff] [blame] | 302 | |
| 303 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 304 | void enable_caches(void) |
| 305 | { |
| 306 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 307 | dcache_enable(); |
| 308 | } |
| 309 | #endif |