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wdenk4e5ca3e2003-12-08 01:34:36 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2002
wdenk4e5ca3e2003-12-08 01:34:36 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4e5ca3e2003-12-08 01:34:36 +00006 */
7
8#include <common.h>
TsiChung Liewdd9f0542010-03-11 22:12:53 -06009#include <asm/immap.h>
10#include <asm/cache.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000011
TsiChung Liewdd9f0542010-03-11 22:12:53 -060012volatile int *cf_icache_status = (int *)ICACHE_STATUS;
13volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
14
15void flush_cache(ulong start_addr, ulong size)
wdenk4e5ca3e2003-12-08 01:34:36 +000016{
wdenkbf9e3b32004-02-12 00:47:09 +000017 /* Must be implemented for all M68k processors with copy-back data cache */
wdenk4e5ca3e2003-12-08 01:34:36 +000018}
TsiChung Liewdd9f0542010-03-11 22:12:53 -060019
20int icache_status(void)
21{
22 return *cf_icache_status;
23}
24
25int dcache_status(void)
26{
27 return *cf_dcache_status;
28}
29
30void icache_enable(void)
31{
32 icache_invalid();
33
34 *cf_icache_status = 1;
35
36#ifdef CONFIG_CF_V4
37 __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
38 __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
39#elif defined(CONFIG_CF_V4e)
40 __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
41 __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
42#else
43 __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
44 __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
45#endif
46
47 __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
48}
49
50void icache_disable(void)
51{
52 u32 temp = 0;
53
54 *cf_icache_status = 0;
55 icache_invalid();
56
57#ifdef CONFIG_CF_V4
58 __asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
59 __asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
60#elif defined(CONFIG_CF_V4e)
61 __asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
62 __asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
63#else
64 __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
65 __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
66
67#endif
68}
69
70void icache_invalid(void)
71{
72 u32 temp;
73
74 temp = CONFIG_SYS_ICACHE_INV;
75 if (*cf_icache_status)
76 temp |= CONFIG_SYS_CACHE_ICACR;
77
78 __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
79}
80
81/*
82 * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
83 * the dcache will be dummy in ColdFire V2 and V3
84 */
85void dcache_enable(void)
86{
87 dcache_invalid();
88 *cf_dcache_status = 1;
89
90#ifdef CONFIG_CF_V4
91 __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
92 __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
93#elif defined(CONFIG_CF_V4e)
94 __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
95 __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
96
97#endif
98
99 __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
100}
101
102void dcache_disable(void)
103{
104 u32 temp = 0;
105
106 *cf_dcache_status = 0;
107 dcache_invalid();
108
109 __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
110
111#ifdef CONFIG_CF_V4
112 __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
113 __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
114#elif defined(CONFIG_CF_V4e)
115 __asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
116 __asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
117
118#endif
119}
120
121void dcache_invalid(void)
122{
123#ifdef CONFIG_CF_V4
124 u32 temp;
125
126 temp = CONFIG_SYS_DCACHE_INV;
127 if (*cf_dcache_status)
128 temp |= CONFIG_SYS_CACHE_DCACR;
129 if (*cf_icache_status)
130 temp |= CONFIG_SYS_CACHE_ICACR;
131
132 __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
133#endif
134}