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gerrit.cesnet.cz / github / trini / u-boot / 44e5c5c4f1b46991477140540b73df224eb1e4fc / . / board / pm826 / pm826.c
blob: 3ba8ca990dee737b6a6ada0e0a0bcea1f668b93d [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
40 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
41 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
42 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
43 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
44 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
45 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
46 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
47 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
48 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
49 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
50 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
51 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
52 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
53 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
54 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
55 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
56 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
57 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
58 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
59 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
60 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
61 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
62 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
63 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
64 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
65 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
66 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
67 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
68 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
69 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
70 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
71 },
72
73 /* Port B configuration */
74 { /* conf ppar psor pdir podr pdat */
wdenkaacf9a42003-01-17 16:27:01 +0000[diff] [blame]75 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
76 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
77 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
78#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
79#ifdef CONFIG_ETHER_ON_FCC2
80#error "SCC1 conflicts with FCC2"
81#endif
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]82 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
wdenkaacf9a42003-01-17 16:27:01 +0000[diff] [blame]83#else
84 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
85#endif
86 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
87 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
88 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
89 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
90 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
91 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
92 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
93 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
94 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
95 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]96 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
97 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
98 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
99 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
100 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
101 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
102 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
103 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
104 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
105 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
106 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
107 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
108 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
109 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
110 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
111 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
112 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
113 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 },
115
116 /* Port C */
117 { /* conf ppar psor pdir podr pdat */
118 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
119 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
120 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
121 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
122 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
123 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
124 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
125 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
126 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
127 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
128 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
wdenkaacf9a42003-01-17 16:27:01 +0000[diff] [blame]129 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
130 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
131 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]132 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
133 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
134 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
135 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
136 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
137 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
138 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
139 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
140 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
141 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
142 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
143 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
144 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
145 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
146 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
147 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
148 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
149 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
150 },
151
152 /* Port D */
153 { /* conf ppar psor pdir podr pdat */
154 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
155 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
156 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
157 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
158 /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
159 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
160 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
161 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
162 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
163 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
164 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
165 /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
166 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
167 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
168 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
169 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
170#if defined(CONFIG_SOFT_I2C)
171 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
172 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
173#else
174#if defined(CONFIG_HARD_I2C)
175 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
176 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
177#else /* normal I/O port pins */
178 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
180#endif
181#endif
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 }
197};
198
199/* ------------------------------------------------------------------------- */
200
201/* Check Board Identity:
202 */
203int checkboard (void)
204{
205 puts ("Board: PM826\n");
206 return 0;
207}
208
209/* ------------------------------------------------------------------------- */
210
211
212/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
213 *
214 * This routine performs standard 8260 initialization sequence
215 * and calculates the available memory size. It may be called
216 * several times to try different SDRAM configurations on both
217 * 60x and local buses.
218 */
219static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
220 ulong orx, volatile uchar * base)
221{
222 volatile uchar c = 0xff;
223 volatile ulong cnt, val;
224 volatile ulong *addr;
225 volatile uint *sdmr_ptr;
226 volatile uint *orx_ptr;
227 int i;
228 ulong save[32]; /* to make test non-destructive */
229 ulong maxsize;
230
231 /* We must be able to test a location outsize the maximum legal size
232 * to find out THAT we are outside; but this address still has to be
233 * mapped by the controller. That means, that the initial mapping has
234 * to be (at least) twice as large as the maximum expected size.
235 */
236 maxsize = (1 + (~orx | 0x7fff)) / 2;
237
238 sdmr_ptr = &memctl->memc_psdmr;
239 orx_ptr = &memctl->memc_or2;
240
241 *orx_ptr = orx;
242
243 /*
244 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
245 *
246 * "At system reset, initialization software must set up the
247 * programmable parameters in the memory controller banks registers
248 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
249 * system software should execute the following initialization sequence
250 * for each SDRAM device.
251 *
252 * 1. Issue a PRECHARGE-ALL-BANKS command
253 * 2. Issue eight CBR REFRESH commands
254 * 3. Issue a MODE-SET command to initialize the mode register
255 *
256 * The initial commands are executed by setting P/LSDMR[OP] and
257 * accessing the SDRAM with a single-byte transaction."
258 *
259 * The appropriate BRx/ORx registers have already been set when we
260 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
261 */
262
263 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
264 *base = c;
265
266 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
267 for (i = 0; i < 8; i++)
268 *base = c;
269
270 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
271 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
272
273 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
274 *base = c;
275
276 /*
277 * Check memory range for valid RAM. A simple memory test determines
278 * the actually available RAM size between addresses `base' and
279 * `base + maxsize'. Some (not all) hardware errors are detected:
280 * - short between address lines
281 * - short between data lines
282 */
283 i = 0;
284 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
285 addr = (volatile ulong *) base + cnt; /* pointer arith! */
286 save[i++] = *addr;
287 *addr = ~cnt;
288 }
289
290 addr = (volatile ulong *) base;
291 save[i] = *addr;
292 *addr = 0;
293
294 if ((val = *addr) != 0) {
295 *addr = save[i];
296 return (0);
297 }
298
299 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
300 addr = (volatile ulong *) base + cnt; /* pointer arith! */
301 val = *addr;
302 *addr = save[--i];
303 if (val != ~cnt) {
304 /* Write the actual size to ORx
305 */
306 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
307 return (cnt * sizeof (long));
308 }
309 }
310 return (maxsize);
311}
312
313
314long int initdram (int board_type)
315{
316 volatile immap_t *immap = (immap_t *) CFG_IMMR;
317 volatile memctl8260_t *memctl = &immap->im_memctl;
318
319#ifndef CFG_RAMBOOT
320 ulong size8, size9;
321#endif
322 ulong psize = 32 * 1024 * 1024;
323
324 memctl->memc_psrt = CFG_PSRT;
325 memctl->memc_mptpr = CFG_MPTPR;
326
327#ifndef CFG_RAMBOOT
328 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
329 (uchar *) CFG_SDRAM_BASE);
330 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
331 (uchar *) CFG_SDRAM_BASE);
332
333 if (size8 < size9) {
334 psize = size9;
335 printf ("(60x:9COL) ");
336 } else {
337 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
338 (uchar *) CFG_SDRAM_BASE);
339 printf ("(60x:8COL) ");
340 }
341#endif
342 return (psize);
343}
344
345#if (CONFIG_COMMANDS & CFG_CMD_DOC)
346extern void doc_probe (ulong physadr);
347void doc_init (void)
348{
349 doc_probe (CFG_DOC_BASE);
350}
351#endif