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Eugeniy Paltseve80dac02017-12-10 21:20:08 +03001/*
2 * Synopsys HSDK SDP CGU clock driver
3 *
4 * Copyright (C) 2017 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <common.h>
13#include <clk-uclass.h>
14#include <div64.h>
15#include <dm.h>
16#include <linux/io.h>
17
18/*
19 * Synopsys ARC HSDK clock tree.
20 *
21 * ------------------
22 * | 33.33 MHz xtal |
23 * ------------------
24 * |
25 * | -----------
26 * |-->| ARC PLL |
27 * | -----------
28 * | |
29 * | |-->|CGU_ARC_IDIV|----------->
30 * | |-->|CREG_CORE_IF_DIV|------->
31 * |
32 * | --------------
33 * |-->| SYSTEM PLL |
34 * | --------------
35 * | |
36 * | |-->|CGU_SYS_IDIV_APB|------->
37 * | |-->|CGU_SYS_IDIV_AXI|------->
38 * | |-->|CGU_SYS_IDIV_*|--------->
39 * | |-->|CGU_SYS_IDIV_EBI_REF|--->
40 * |
41 * | --------------
42 * |-->| TUNNEL PLL |
43 * | --------------
44 * | |
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +030045 * | |-->|CGU_TUN_IDIV_TUN|----------->
46 * | |-->|CGU_TUN_IDIV_ROM|----------->
47 * | |-->|CGU_TUN_IDIV_PWM|----------->
Eugeniy Paltseve80dac02017-12-10 21:20:08 +030048 * |
Eugeniy Paltseve80dac02017-12-10 21:20:08 +030049 * | -----------
50 * |-->| DDR PLL |
51 * -----------
52 * |
53 * |---------------------------->
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +030054 *
55 * ------------------
56 * | 27.00 MHz xtal |
57 * ------------------
58 * |
59 * | ------------
60 * |-->| HDMI PLL |
61 * ------------
62 * |
63 * |-->|CGU_HDMI_IDIV_APB|------>
Eugeniy Paltseve80dac02017-12-10 21:20:08 +030064 */
65
Eugeniy Paltseve80dac02017-12-10 21:20:08 +030066#define CGU_ARC_IDIV 0x080
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +030067#define CGU_TUN_IDIV_TUN 0x380
68#define CGU_TUN_IDIV_ROM 0x390
69#define CGU_TUN_IDIV_PWM 0x3A0
Eugeniy Paltsev1dfb2ec2020-04-23 14:50:50 +030070#define CGU_TUN_IDIV_TIMER 0x3B0
Eugeniy Paltseve80dac02017-12-10 21:20:08 +030071#define CGU_HDMI_IDIV_APB 0x480
72#define CGU_SYS_IDIV_APB 0x180
73#define CGU_SYS_IDIV_AXI 0x190
74#define CGU_SYS_IDIV_ETH 0x1A0
75#define CGU_SYS_IDIV_USB 0x1B0
76#define CGU_SYS_IDIV_SDIO 0x1C0
77#define CGU_SYS_IDIV_HDMI 0x1D0
78#define CGU_SYS_IDIV_GFX_CORE 0x1E0
79#define CGU_SYS_IDIV_GFX_DMA 0x1F0
80#define CGU_SYS_IDIV_GFX_CFG 0x200
81#define CGU_SYS_IDIV_DMAC_CORE 0x210
82#define CGU_SYS_IDIV_DMAC_CFG 0x220
83#define CGU_SYS_IDIV_SDIO_REF 0x230
84#define CGU_SYS_IDIV_SPI_REF 0x240
85#define CGU_SYS_IDIV_I2C_REF 0x250
86#define CGU_SYS_IDIV_UART_REF 0x260
87#define CGU_SYS_IDIV_EBI_REF 0x270
88
89#define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
90
91#define CGU_ARC_PLL 0x0
92#define CGU_SYS_PLL 0x10
93#define CGU_DDR_PLL 0x20
94#define CGU_TUN_PLL 0x30
95#define CGU_HDMI_PLL 0x40
96
97#define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
98#define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
99#define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
100#define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
101
102#define CGU_PLL_CTRL_ODIV_SHIFT 2
103#define CGU_PLL_CTRL_IDIV_SHIFT 4
104#define CGU_PLL_CTRL_FBDIV_SHIFT 9
105#define CGU_PLL_CTRL_BAND_SHIFT 20
106
107#define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
108#define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
109#define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
110
111#define CGU_PLL_CTRL_PD BIT(0)
112#define CGU_PLL_CTRL_BYPASS BIT(1)
113
114#define CGU_PLL_STATUS_LOCK BIT(0)
115#define CGU_PLL_STATUS_ERR BIT(1)
116
117#define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
118
119#define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
120#define CORE_IF_CLK_THRESHOLD_HZ 500000000
121#define CREG_CORE_IF_CLK_DIV_1 0x0
122#define CREG_CORE_IF_CLK_DIV_2 0x1
123
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300124#define MIN_PLL_RATE 100000000 /* 100 MHz */
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300125#define PARENT_RATE_33 33333333 /* fixed clock - xtal */
126#define PARENT_RATE_27 27000000 /* fixed clock - xtal */
Eugeniy Paltsev1dfb2ec2020-04-23 14:50:50 +0300127#define CGU_MAX_CLOCKS 27
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300128
129#define CGU_SYS_CLOCKS 16
130#define MAX_AXI_CLOCKS 4
131
Eugeniy Paltsev1dfb2ec2020-04-23 14:50:50 +0300132#define CGU_TUN_CLOCKS 4
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300133#define MAX_TUN_CLOCKS 6
134
135struct hsdk_tun_idiv_cfg {
136 u32 oft;
137 u8 val[MAX_TUN_CLOCKS];
138};
139
140struct hsdk_tun_clk_cfg {
141 const u32 clk_rate[MAX_TUN_CLOCKS];
142 const u32 pll_rate[MAX_TUN_CLOCKS];
143 const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
144};
145
146static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
147 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
Eugeniy Paltsev7b50db82020-04-16 22:35:11 +0300148 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300149 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
150 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
Eugeniy Paltsev1dfb2ec2020-04-23 14:50:50 +0300151 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
152 { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300153 }
154};
155
156struct hsdk_sys_idiv_cfg {
157 u32 oft;
158 u8 val[MAX_AXI_CLOCKS];
159};
160
161struct hsdk_axi_clk_cfg {
162 const u32 clk_rate[MAX_AXI_CLOCKS];
163 const u32 pll_rate[MAX_AXI_CLOCKS];
164 const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
165};
166
167static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
168 { 200000000, 400000000, 600000000, 800000000 },
169 { 800000000, 800000000, 600000000, 800000000 }, {
170 { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
171 { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
172 { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
173 { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
174 { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
175 { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
176 { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
177 { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
178 { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
179 { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
180 { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
181 { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
182 { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
183 { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
184 { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
185 { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
186 }
187};
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300188
189struct hsdk_pll_cfg {
190 u32 rate;
191 u32 idiv;
192 u32 fbdiv;
193 u32 odiv;
194 u32 band;
195};
196
197static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
198 { 100000000, 0, 11, 3, 0 },
199 { 125000000, 0, 14, 3, 0 },
200 { 133000000, 0, 15, 3, 0 },
201 { 150000000, 0, 17, 3, 0 },
202 { 200000000, 1, 47, 3, 0 },
203 { 233000000, 1, 27, 2, 0 },
204 { 300000000, 1, 35, 2, 0 },
205 { 333000000, 1, 39, 2, 0 },
206 { 400000000, 1, 47, 2, 0 },
207 { 500000000, 0, 14, 1, 0 },
208 { 600000000, 0, 17, 1, 0 },
209 { 700000000, 0, 20, 1, 0 },
Eugeniy Paltsev7b50db82020-04-16 22:35:11 +0300210 { 750000000, 1, 44, 1, 0 },
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300211 { 800000000, 0, 23, 1, 0 },
212 { 900000000, 1, 26, 0, 0 },
213 { 1000000000, 1, 29, 0, 0 },
214 { 1100000000, 1, 32, 0, 0 },
215 { 1200000000, 1, 35, 0, 0 },
216 { 1300000000, 1, 38, 0, 0 },
217 { 1400000000, 1, 41, 0, 0 },
218 { 1500000000, 1, 44, 0, 0 },
219 { 1600000000, 1, 47, 0, 0 },
220 {}
221};
222
223static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
224 { 297000000, 0, 21, 2, 0 },
225 { 540000000, 0, 19, 1, 0 },
226 { 594000000, 0, 21, 1, 0 },
227 {}
228};
229
230struct hsdk_cgu_clk {
231 /* CGU block register */
232 void __iomem *cgu_regs;
233 /* CREG block register */
234 void __iomem *creg_regs;
235
236 /* PLLs registers */
237 void __iomem *regs;
238 /* PLLs special registers */
239 void __iomem *spec_regs;
240 /* PLLs devdata */
241 const struct hsdk_pll_devdata *pll_devdata;
242
243 /* Dividers registers */
244 void __iomem *idiv_regs;
245};
246
247struct hsdk_pll_devdata {
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300248 const u32 parent_rate;
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300249 const struct hsdk_pll_cfg *pll_cfg;
250 int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
251 const struct hsdk_pll_cfg *cfg);
252};
253
254static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
255 const struct hsdk_pll_cfg *);
256static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
257 const struct hsdk_pll_cfg *);
258
259static const struct hsdk_pll_devdata core_pll_dat = {
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300260 .parent_rate = PARENT_RATE_33,
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300261 .pll_cfg = asdt_pll_cfg,
262 .update_rate = hsdk_pll_core_update_rate,
263};
264
265static const struct hsdk_pll_devdata sdt_pll_dat = {
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300266 .parent_rate = PARENT_RATE_33,
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300267 .pll_cfg = asdt_pll_cfg,
268 .update_rate = hsdk_pll_comm_update_rate,
269};
270
271static const struct hsdk_pll_devdata hdmi_pll_dat = {
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300272 .parent_rate = PARENT_RATE_27,
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300273 .pll_cfg = hdmi_pll_cfg,
274 .update_rate = hsdk_pll_comm_update_rate,
275};
276
277static ulong idiv_set(struct clk *, ulong);
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300278static ulong cpu_clk_set(struct clk *, ulong);
279static ulong axi_clk_set(struct clk *, ulong);
280static ulong tun_clk_set(struct clk *, ulong);
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300281static ulong idiv_get(struct clk *);
282static int idiv_off(struct clk *);
283static ulong pll_set(struct clk *, ulong);
284static ulong pll_get(struct clk *);
285
286struct hsdk_cgu_clock_map {
287 u32 cgu_pll_oft;
288 u32 creg_div_oft;
289 u32 cgu_div_oft;
290 const struct hsdk_pll_devdata *pll_devdata;
291 ulong (*get_rate)(struct clk *clk);
292 ulong (*set_rate)(struct clk *clk, ulong rate);
293 int (*disable)(struct clk *clk);
294};
295
296static const struct hsdk_cgu_clock_map clock_map[] = {
297 { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300298 { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300299 { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
300 { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
301 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300302 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300303 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
304 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
305 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
306 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
307 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
308 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
309 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
310 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
311 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
312 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
313 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
314 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
315 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
316 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
317 { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300318 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
319 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
320 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
Eugeniy Paltsev1dfb2ec2020-04-23 14:50:50 +0300321 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300322 { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
323 { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
324};
325
326static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
327{
328 iowrite32(val, clk->idiv_regs);
329}
330
331static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
332{
333 return ioread32(clk->idiv_regs);
334}
335
336static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
337{
338 iowrite32(val, clk->regs + reg);
339}
340
341static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
342{
343 return ioread32(clk->regs + reg);
344}
345
346static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
347{
348 iowrite32(val, clk->spec_regs + reg);
349}
350
351static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
352{
353 return ioread32(clk->spec_regs + reg);
354}
355
356static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
357 const struct hsdk_pll_cfg *cfg)
358{
359 u32 val = 0;
360
361 /* Powerdown and Bypass bits should be cleared */
362 val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
363 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
364 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
365 val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
366
367 pr_debug("write configurarion: %#x\n", val);
368
369 hsdk_pll_write(clk, CGU_PLL_CTRL, val);
370}
371
372static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
373{
374 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
375}
376
377static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
378{
379 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
380}
381
382static ulong pll_get(struct clk *sclk)
383{
384 u32 val;
385 u64 rate;
386 u32 idiv, fbdiv, odiv;
387 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300388 u32 parent_rate = clk->pll_devdata->parent_rate;
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300389
390 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
391
392 pr_debug("current configurarion: %#x\n", val);
393
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300394 /* Check if PLL is bypassed */
395 if (val & CGU_PLL_CTRL_BYPASS)
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300396 return parent_rate;
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300397
Eugeniy Paltsevb8f3ce02020-01-29 14:08:29 +0300398 /* Check if PLL is disabled */
399 if (val & CGU_PLL_CTRL_PD)
400 return 0;
401
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300402 /* input divider = reg.idiv + 1 */
403 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
404 /* fb divider = 2*(reg.fbdiv + 1) */
405 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
406 /* output divider = 2^(reg.odiv) */
407 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
408
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300409 rate = (u64)parent_rate * fbdiv;
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300410 do_div(rate, idiv * odiv);
411
412 return rate;
413}
414
415static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
416{
417 int i;
418 unsigned long best_rate;
419 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
420 const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
421
422 if (pll_cfg[0].rate == 0)
423 return -EINVAL;
424
425 best_rate = pll_cfg[0].rate;
426
427 for (i = 1; pll_cfg[i].rate != 0; i++) {
428 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
429 best_rate = pll_cfg[i].rate;
430 }
431
432 pr_debug("chosen best rate: %lu\n", best_rate);
433
434 return best_rate;
435}
436
437static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
438 unsigned long rate,
439 const struct hsdk_pll_cfg *cfg)
440{
441 hsdk_pll_set_cfg(clk, cfg);
442
443 /*
444 * Wait until CGU relocks and check error status.
445 * If after timeout CGU is unlocked yet return error.
446 */
447 udelay(HSDK_PLL_MAX_LOCK_TIME);
448 if (!hsdk_pll_is_locked(clk))
449 return -ETIMEDOUT;
450
451 if (hsdk_pll_is_err(clk))
452 return -EINVAL;
453
454 return 0;
455}
456
457static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
458 unsigned long rate,
459 const struct hsdk_pll_cfg *cfg)
460{
461 /*
462 * When core clock exceeds 500MHz, the divider for the interface
463 * clock must be programmed to div-by-2.
464 */
465 if (rate > CORE_IF_CLK_THRESHOLD_HZ)
466 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
467
468 hsdk_pll_set_cfg(clk, cfg);
469
470 /*
471 * Wait until CGU relocks and check error status.
472 * If after timeout CGU is unlocked yet return error.
473 */
474 udelay(HSDK_PLL_MAX_LOCK_TIME);
475 if (!hsdk_pll_is_locked(clk))
476 return -ETIMEDOUT;
477
478 if (hsdk_pll_is_err(clk))
479 return -EINVAL;
480
481 /*
482 * Program divider to div-by-1 if we succesfuly set core clock below
483 * 500MHz threshold.
484 */
485 if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
486 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
487
488 return 0;
489}
490
491static ulong pll_set(struct clk *sclk, ulong rate)
492{
493 int i;
494 unsigned long best_rate;
495 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
496 const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
497
498 best_rate = hsdk_pll_round_rate(sclk, rate);
499
500 for (i = 0; pll_cfg[i].rate != 0; i++) {
501 if (pll_cfg[i].rate == best_rate) {
502 return clk->pll_devdata->update_rate(clk, best_rate,
503 &pll_cfg[i]);
504 }
505 }
506
Eugeniy Paltsevdefd1e72020-01-29 14:08:30 +0300507 pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
508 clk->pll_devdata->parent_rate);
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300509
510 return -EINVAL;
511}
512
513static int idiv_off(struct clk *sclk)
514{
515 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
516
517 hsdk_idiv_write(clk, 0);
518
519 return 0;
520}
521
522static ulong idiv_get(struct clk *sclk)
523{
524 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
525 ulong parent_rate = pll_get(sclk);
526 u32 div_factor = hsdk_idiv_read(clk);
527
528 div_factor &= CGU_IDIV_MASK;
529
530 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
531
532 if (div_factor == 0)
533 return 0;
534
535 return parent_rate / div_factor;
536}
537
Eugeniy Paltsev075cbae2018-01-16 20:44:25 +0300538/* Special behavior: wen we set this clock we set both idiv and pll */
539static ulong cpu_clk_set(struct clk *sclk, ulong rate)
540{
541 ulong ret;
542
543 ret = pll_set(sclk, rate);
544 idiv_set(sclk, rate);
545
546 return ret;
547}
548
549/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
550static ulong axi_clk_set(struct clk *sclk, ulong rate)
551{
552 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
553 ulong pll_rate;
554 int i, freq_idx = -1;
555 ulong ret = 0;
556
557 pll_rate = pll_get(sclk);
558
559 for (i = 0; i < MAX_AXI_CLOCKS; i++) {
560 if (axi_clk_cfg.clk_rate[i] == rate) {
561 freq_idx = i;
562 break;
563 }
564 }
565
566 if (freq_idx < 0) {
567 pr_err("axi clk: invalid rate=%ld Hz\n", rate);
568 return -EINVAL;
569 }
570
571 /* configure PLL before dividers */
572 if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
573 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
574
575 /* configure SYS dividers */
576 for (i = 0; i < CGU_SYS_CLOCKS; i++) {
577 clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
578 hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
579 }
580
581 /* configure PLL after dividers */
582 if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
583 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
584
585 return ret;
586}
587
588static ulong tun_clk_set(struct clk *sclk, ulong rate)
589{
590 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
591 ulong pll_rate;
592 int i, freq_idx = -1;
593 ulong ret = 0;
594
595 pll_rate = pll_get(sclk);
596
597 for (i = 0; i < MAX_TUN_CLOCKS; i++) {
598 if (tun_clk_cfg.clk_rate[i] == rate) {
599 freq_idx = i;
600 break;
601 }
602 }
603
604 if (freq_idx < 0) {
605 pr_err("tun clk: invalid rate=%ld Hz\n", rate);
606 return -EINVAL;
607 }
608
609 /* configure PLL before dividers */
610 if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
611 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
612
613 /* configure SYS dividers */
614 for (i = 0; i < CGU_TUN_CLOCKS; i++) {
615 clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
616 hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
617 }
618
619 /* configure PLL after dividers */
620 if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
621 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
622
623 return ret;
624}
625
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300626static ulong idiv_set(struct clk *sclk, ulong rate)
627{
628 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
629 ulong parent_rate = pll_get(sclk);
630 u32 div_factor;
631
632 div_factor = parent_rate / rate;
633 if (abs(rate - parent_rate / (div_factor + 1)) <=
634 abs(rate - parent_rate / div_factor)) {
635 div_factor += 1;
636 }
637
638 if (div_factor & ~CGU_IDIV_MASK) {
Eugeniy Paltsev320c8a12018-01-16 20:44:27 +0300639 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300640 rate, parent_rate, div_factor, CGU_IDIV_MASK);
641
642 div_factor = CGU_IDIV_MASK;
643 }
644
645 if (div_factor == 0) {
Eugeniy Paltsev320c8a12018-01-16 20:44:27 +0300646 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300647 rate, parent_rate, div_factor);
648
649 div_factor = 1;
650 }
651
652 hsdk_idiv_write(clk, div_factor);
653
654 return 0;
655}
656
657static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
658{
659 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
660
661 if (sclk->id >= CGU_MAX_CLOCKS)
662 return -EINVAL;
663
664 clk->pll_devdata = clock_map[sclk->id].pll_devdata;
665 clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
666 clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
667 clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
668
669 return 0;
670}
671
672static ulong hsdk_cgu_get_rate(struct clk *sclk)
673{
674 if (hsdk_prepare_clock_tree_branch(sclk))
675 return -EINVAL;
676
677 return clock_map[sclk->id].get_rate(sclk);
678}
679
680static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
681{
682 if (hsdk_prepare_clock_tree_branch(sclk))
683 return -EINVAL;
684
685 return clock_map[sclk->id].set_rate(sclk, rate);
686}
687
688static int hsdk_cgu_disable(struct clk *sclk)
689{
690 if (hsdk_prepare_clock_tree_branch(sclk))
691 return -EINVAL;
692
693 if (clock_map[sclk->id].disable)
694 return clock_map[sclk->id].disable(sclk);
695
696 return -ENOTSUPP;
697}
698
699static const struct clk_ops hsdk_cgu_ops = {
700 .set_rate = hsdk_cgu_set_rate,
701 .get_rate = hsdk_cgu_get_rate,
702 .disable = hsdk_cgu_disable,
703};
704
705static int hsdk_cgu_clk_probe(struct udevice *dev)
706{
707 struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
708
709 BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
710
711 pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
712 if (!pll_clk->cgu_regs)
713 return -EINVAL;
714
715 pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
716 if (!pll_clk->creg_regs)
717 return -EINVAL;
718
719 return 0;
720}
721
722static const struct udevice_id hsdk_cgu_clk_id[] = {
723 { .compatible = "snps,hsdk-cgu-clock" },
724 { }
725};
726
727U_BOOT_DRIVER(hsdk_cgu_clk) = {
728 .name = "hsdk-cgu-clk",
729 .id = UCLASS_CLK,
730 .of_match = hsdk_cgu_clk_id,
731 .probe = hsdk_cgu_clk_probe,
Eugeniy Paltsevf6d78122018-01-16 20:44:26 +0300732 .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300733 .ops = &hsdk_cgu_ops,
734};