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wdenk12f34242003-09-02 22:48:03 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
29/* ------------------------------------------------------------------------- */
30
31#if 0
32#define FPGA_DEBUG
33#endif
34
35/* fpga configuration data - gzip compressed and generated by bin2c */
36const unsigned char fpgadata[] =
37{
38#include "fpgadata.c"
39};
40
41/*
42 * include common fpga code (for esd boards)
43 */
44#include "../common/fpga.c"
45
46
47/* Prototypes */
48int gunzip(void *, int, unsigned char *, int *);
49
50
51int board_pre_init (void)
52{
53 out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
wdenk42d1f032003-10-15 23:53:47 +000054 out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
wdenk12f34242003-09-02 22:48:03 +000055
56 /*
57 * IRQ 0-15 405GP internally generated; active high; level sensitive
58 * IRQ 16 405GP internally generated; active low; level sensitive
59 * IRQ 17-24 RESERVED
60 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
61 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
62 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
63 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
64 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
65 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
66 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
67 */
68 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
69 mtdcr(uicer, 0x00000000); /* disable all ints */
70 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
71 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
72 mtdcr(uictr, 0x10000000); /* set int trigger levels */
73 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
74 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
75
76 /*
77 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
78 */
79#if 1 /* test-only */
80 mtebc (epcr, 0xa8400000); /* ebc always driven */
81#else
82 mtebc (epcr, 0x28400000); /* ebc in high-z */
83#endif
84
85 return 0;
86}
87
88
89/* ------------------------------------------------------------------------- */
90
91int misc_init_f (void)
92{
93 return 0; /* dummy implementation */
94}
95
96
97int misc_init_r (void)
98{
99#if 0 /* test-only */
100 DECLARE_GLOBAL_DATA_PTR;
101#if 0
102 volatile unsigned short *fpga_mode =
103 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
104 volatile unsigned char *duart0_mcr =
105 (unsigned char *)((ulong)DUART0_BA + 4);
106 volatile unsigned char *duart1_mcr =
107 (unsigned char *)((ulong)DUART1_BA + 4);
108
109 bd_t *bd = gd->bd;
110 char * tmp; /* Temporary char pointer */
111 unsigned char *dst;
112 ulong len = sizeof(fpgadata);
113 int status;
114 int index;
115 int i;
116 unsigned long cntrl0Reg;
117
118 dst = malloc(CFG_FPGA_MAX_SIZE);
119 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
120 printf ("GUNZIP ERROR - must RESET board to recover\n");
121 do_reset (NULL, 0, 0, NULL);
122 }
123
124 status = fpga_boot(dst, len);
125 if (status != 0) {
126 printf("\nFPGA: Booting failed ");
127 switch (status) {
128 case ERROR_FPGA_PRG_INIT_LOW:
129 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
130 break;
131 case ERROR_FPGA_PRG_INIT_HIGH:
132 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
133 break;
134 case ERROR_FPGA_PRG_DONE:
135 printf("(Timeout: DONE not high after programming FPGA)\n ");
136 break;
137 }
138
139 /* display infos on fpgaimage */
140 index = 15;
141 for (i=0; i<4; i++) {
142 len = dst[index];
143 printf("FPGA: %s\n", &(dst[index+1]));
144 index += len+3;
145 }
146 putc ('\n');
147 /* delayed reboot */
148 for (i=20; i>0; i--) {
149 printf("Rebooting in %2d seconds \r",i);
150 for (index=0;index<1000;index++)
151 udelay(1000);
152 }
153 putc ('\n');
154 do_reset(NULL, 0, 0, NULL);
155 }
156
157 puts("FPGA: ");
158
159 /* display infos on fpgaimage */
160 index = 15;
161 for (i=0; i<4; i++) {
162 len = dst[index];
163 printf("%s ", &(dst[index+1]));
164 index += len+3;
165 }
166 putc ('\n');
167
168 free(dst);
169
170 /*
171 * Reset FPGA via FPGA_DATA pin
172 */
173 SET_FPGA(FPGA_PRG | FPGA_CLK);
174 udelay(1000); /* wait 1ms */
175 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
176 udelay(1000); /* wait 1ms */
177
178#endif
179
180#if 0
181 /*
182 * Enable power on PS/2 interface
183 */
184 *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
185
186 /*
187 * Enable interrupts in exar duart mcr[3]
188 */
189 *duart0_mcr = 0x08;
190 *duart1_mcr = 0x08;
191#endif
192#endif
193
194 return (0);
195}
196
197
198/*
199 * Check Board Identity:
200 */
201
202int checkboard (void)
203{
204 unsigned char str[64];
205 int i = getenv_r ("serial#", str, sizeof(str));
206
207 puts ("Board: ");
208
209 if (i == -1) {
210 puts ("### No HW ID - assuming PPChameleonEVB");
211 } else {
212 puts(str);
213 }
214
215 putc ('\n');
216
217 return 0;
218}
219
220/* ------------------------------------------------------------------------- */
221
222long int initdram (int board_type)
223{
224 unsigned long val;
225
226 mtdcr(memcfga, mem_mb0cf);
227 val = mfdcr(memcfgd);
228
229#if 0 /* test-only */
230 for (;;) {
231 NAND_DISABLE_CE(1);
232 udelay(100);
233 NAND_ENABLE_CE(1);
234 udelay(100);
235 }
236#endif
237#if 0
238 printf("\nmb0cf=%x\n", val); /* test-only */
239 printf("strap=%x\n", mfdcr(strap)); /* test-only */
240#endif
241
242 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
243}
244
245/* ------------------------------------------------------------------------- */
246
247int testdram (void)
248{
249 /* TODO: XXX XXX XXX */
250 printf ("test: 16 MB - ok\n");
251
252 return (0);
253}
254
255/* ------------------------------------------------------------------------- */
256
257#if (CONFIG_COMMANDS & CFG_CMD_NAND)
wdenka43278a2003-09-11 19:48:06 +0000258extern ulong
wdenk12f34242003-09-02 22:48:03 +0000259nand_probe(ulong physadr);
260
261void
262nand_init(void)
263{
wdenkfbe4b5c2003-10-06 21:55:32 +0000264 ulong totlen = 0;
wdenka43278a2003-09-11 19:48:06 +0000265
wdenkfbe4b5c2003-10-06 21:55:32 +0000266#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
267 (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
wdenk4d816772003-09-03 14:03:26 +0000268 debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
wdenkfbe4b5c2003-10-06 21:55:32 +0000269 totlen += nand_probe (CFG_NAND0_BASE);
270#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
wdenk4d816772003-09-03 14:03:26 +0000271
272 debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
wdenka43278a2003-09-11 19:48:06 +0000273 totlen += nand_probe (CFG_NAND1_BASE);
274
275 printf ("%4lu MB\n", totlen >>20);
wdenk12f34242003-09-02 22:48:03 +0000276}
277#endif