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Mike Frysinger75ba6d62009-02-23 10:29:47 -05001/*
2 * SMSC LAN9[12]1[567] Network driver
3 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _SMC911X_H_
26#define _SMC911X_H_
27
28#include <linux/types.h>
29
Ben Warren736fead2009-07-20 22:01:11 -070030#define DRIVERNAME "smc911x"
31
32#if defined (CONFIG_SMC911X_32_BIT) && \
33 defined (CONFIG_SMC911X_16_BIT)
34#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
35 CONFIG_SMC911X_16_BIT shall be set"
Mike Frysinger75ba6d62009-02-23 10:29:47 -050036#endif
37
Ben Warren736fead2009-07-20 22:01:11 -070038#if defined (CONFIG_SMC911X_32_BIT)
39static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
Mike Frysinger75ba6d62009-02-23 10:29:47 -050040{
Ben Warren736fead2009-07-20 22:01:11 -070041 return *(volatile u32*)(dev->iobase + offset);
Mike Frysinger75ba6d62009-02-23 10:29:47 -050042}
Ben Warren736fead2009-07-20 22:01:11 -070043u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
44 __attribute__((weak, alias("__smc911x_reg_read")));
Mike Frysinger75ba6d62009-02-23 10:29:47 -050045
Ben Warren736fead2009-07-20 22:01:11 -070046static inline void __smc911x_reg_write(struct eth_device *dev,
47 u32 offset, u32 val)
Mike Frysinger75ba6d62009-02-23 10:29:47 -050048{
Ben Warren736fead2009-07-20 22:01:11 -070049 *(volatile u32*)(dev->iobase + offset) = val;
Mike Frysinger75ba6d62009-02-23 10:29:47 -050050}
Ben Warren736fead2009-07-20 22:01:11 -070051void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
52 __attribute__((weak, alias("__smc911x_reg_write")));
53#elif defined (CONFIG_SMC911X_16_BIT)
54static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
Mike Frysinger75ba6d62009-02-23 10:29:47 -050055{
Ben Warren736fead2009-07-20 22:01:11 -070056 volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
Mike Frysinger75ba6d62009-02-23 10:29:47 -050057 return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
58}
Ben Warren736fead2009-07-20 22:01:11 -070059static inline void smc911x_reg_write(struct eth_device *dev,
60 u32 offset, u32 val)
Mike Frysinger75ba6d62009-02-23 10:29:47 -050061{
Ben Warren736fead2009-07-20 22:01:11 -070062 *(volatile u16 *)(dev->iobase + offset) = (u16)val;
63 *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
Mike Frysinger75ba6d62009-02-23 10:29:47 -050064}
65#else
66#error "SMC911X: undefined bus width"
Ben Warren736fead2009-07-20 22:01:11 -070067#endif /* CONFIG_SMC911X_16_BIT */
Mike Frysinger75ba6d62009-02-23 10:29:47 -050068
69/* Below are the register offsets and bit definitions
70 * of the Lan911x memory space
71 */
Ben Warren736fead2009-07-20 22:01:11 -070072#define RX_DATA_FIFO 0x00
Mike Frysinger75ba6d62009-02-23 10:29:47 -050073
Ben Warren736fead2009-07-20 22:01:11 -070074#define TX_DATA_FIFO 0x20
Mike Frysinger75ba6d62009-02-23 10:29:47 -050075#define TX_CMD_A_INT_ON_COMP 0x80000000
76#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
77#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
78#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
79#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
80#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
81#define TX_CMD_A_INT_FIRST_SEG 0x00002000
82#define TX_CMD_A_INT_LAST_SEG 0x00001000
83#define TX_CMD_A_BUF_SIZE 0x000007FF
84#define TX_CMD_B_PKT_TAG 0xFFFF0000
85#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
86#define TX_CMD_B_DISABLE_PADDING 0x00001000
87#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
88
Ben Warren736fead2009-07-20 22:01:11 -070089#define RX_STATUS_FIFO 0x40
Mike Frysinger75ba6d62009-02-23 10:29:47 -050090#define RX_STS_PKT_LEN 0x3FFF0000
91#define RX_STS_ES 0x00008000
92#define RX_STS_BCST 0x00002000
93#define RX_STS_LEN_ERR 0x00001000
94#define RX_STS_RUNT_ERR 0x00000800
95#define RX_STS_MCAST 0x00000400
96#define RX_STS_TOO_LONG 0x00000080
97#define RX_STS_COLL 0x00000040
98#define RX_STS_ETH_TYPE 0x00000020
99#define RX_STS_WDOG_TMT 0x00000010
100#define RX_STS_MII_ERR 0x00000008
101#define RX_STS_DRIBBLING 0x00000004
102#define RX_STS_CRC_ERR 0x00000002
Ben Warren736fead2009-07-20 22:01:11 -0700103#define RX_STATUS_FIFO_PEEK 0x44
104#define TX_STATUS_FIFO 0x48
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500105#define TX_STS_TAG 0xFFFF0000
106#define TX_STS_ES 0x00008000
107#define TX_STS_LOC 0x00000800
108#define TX_STS_NO_CARR 0x00000400
109#define TX_STS_LATE_COLL 0x00000200
110#define TX_STS_MANY_COLL 0x00000100
111#define TX_STS_COLL_CNT 0x00000078
112#define TX_STS_MANY_DEFER 0x00000004
113#define TX_STS_UNDERRUN 0x00000002
114#define TX_STS_DEFERRED 0x00000001
Ben Warren736fead2009-07-20 22:01:11 -0700115#define TX_STATUS_FIFO_PEEK 0x4C
116#define ID_REV 0x50
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500117#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
118#define ID_REV_REV_ID 0x0000FFFF /* RO */
119
Ben Warren736fead2009-07-20 22:01:11 -0700120#define INT_CFG 0x54
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500121#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
122#define INT_CFG_INT_DEAS_CLR 0x00004000
123#define INT_CFG_INT_DEAS_STS 0x00002000
124#define INT_CFG_IRQ_INT 0x00001000 /* RO */
125#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700126 /* R/W Not Affected by SW Reset */
127#define INT_CFG_IRQ_POL 0x00000010
128 /* R/W Not Affected by SW Reset */
129#define INT_CFG_IRQ_TYPE 0x00000001
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500130
Ben Warren736fead2009-07-20 22:01:11 -0700131#define INT_STS 0x58
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500132#define INT_STS_SW_INT 0x80000000 /* R/WC */
133#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
134#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
135#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
136#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
137#define INT_STS_TX_IOC 0x00200000 /* R/WC */
138#define INT_STS_RXD_INT 0x00100000 /* R/WC */
139#define INT_STS_GPT_INT 0x00080000 /* R/WC */
140#define INT_STS_PHY_INT 0x00040000 /* RO */
141#define INT_STS_PME_INT 0x00020000 /* R/WC */
142#define INT_STS_TXSO 0x00010000 /* R/WC */
143#define INT_STS_RWT 0x00008000 /* R/WC */
144#define INT_STS_RXE 0x00004000 /* R/WC */
145#define INT_STS_TXE 0x00002000 /* R/WC */
146/*#define INT_STS_ERX 0x00001000*/ /* R/WC */
147#define INT_STS_TDFU 0x00000800 /* R/WC */
148#define INT_STS_TDFO 0x00000400 /* R/WC */
149#define INT_STS_TDFA 0x00000200 /* R/WC */
150#define INT_STS_TSFF 0x00000100 /* R/WC */
151#define INT_STS_TSFL 0x00000080 /* R/WC */
152/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
153#define INT_STS_RDFO 0x00000040 /* R/WC */
154#define INT_STS_RDFL 0x00000020 /* R/WC */
155#define INT_STS_RSFF 0x00000010 /* R/WC */
156#define INT_STS_RSFL 0x00000008 /* R/WC */
157#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
158#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
159#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
Ben Warren736fead2009-07-20 22:01:11 -0700160#define INT_EN 0x5C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500161#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
162#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
163#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
164#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
165/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
166#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
167#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
168#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
169#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
170#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
171#define INT_EN_TXSO_EN 0x00010000 /* R/W */
172#define INT_EN_RWT_EN 0x00008000 /* R/W */
173#define INT_EN_RXE_EN 0x00004000 /* R/W */
174#define INT_EN_TXE_EN 0x00002000 /* R/W */
175/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
176#define INT_EN_TDFU_EN 0x00000800 /* R/W */
177#define INT_EN_TDFO_EN 0x00000400 /* R/W */
178#define INT_EN_TDFA_EN 0x00000200 /* R/W */
179#define INT_EN_TSFF_EN 0x00000100 /* R/W */
180#define INT_EN_TSFL_EN 0x00000080 /* R/W */
181/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
182#define INT_EN_RDFO_EN 0x00000040 /* R/W */
183#define INT_EN_RDFL_EN 0x00000020 /* R/W */
184#define INT_EN_RSFF_EN 0x00000010 /* R/W */
185#define INT_EN_RSFL_EN 0x00000008 /* R/W */
186#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
187#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
188#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
189
Ben Warren736fead2009-07-20 22:01:11 -0700190#define BYTE_TEST 0x64
191#define FIFO_INT 0x68
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500192#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
193#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
194#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
195#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
196
Ben Warren736fead2009-07-20 22:01:11 -0700197#define RX_CFG 0x6C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500198#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
199#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
200#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
201#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
202#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
203#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
204#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
205/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
206
Ben Warren736fead2009-07-20 22:01:11 -0700207#define TX_CFG 0x70
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500208/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700209 /* R/W Self Clearing */
210/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500211#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
212#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
213#define TX_CFG_TXSAO 0x00000004 /* R/W */
214#define TX_CFG_TX_ON 0x00000002 /* R/W */
215#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
216
Ben Warren736fead2009-07-20 22:01:11 -0700217#define HW_CFG 0x74
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500218#define HW_CFG_TTM 0x00200000 /* R/W */
219#define HW_CFG_SF 0x00100000 /* R/W */
220#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
221#define HW_CFG_TR 0x00003000 /* R/W */
222#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
223#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
224#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
225#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
226#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
227#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
228#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
229#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
230#define HW_CFG_SRST_TO 0x00000002 /* RO */
231#define HW_CFG_SRST 0x00000001 /* Self Clearing */
232
Ben Warren736fead2009-07-20 22:01:11 -0700233#define RX_DP_CTRL 0x78
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500234#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
235#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
236
Ben Warren736fead2009-07-20 22:01:11 -0700237#define RX_FIFO_INF 0x7C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500238#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
239#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
240
Ben Warren736fead2009-07-20 22:01:11 -0700241#define TX_FIFO_INF 0x80
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500242#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
243#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
244
Ben Warren736fead2009-07-20 22:01:11 -0700245#define PMT_CTRL 0x84
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500246#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
247#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
248#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
249#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700250 /* R/W Not Affected by SW Reset */
251#define PMT_CTRL_PME_TYPE 0x00000040
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500252#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
253#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
254#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
255#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
256#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
257#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
258#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700259 /* R/W Not Affected by SW Reset */
260#define PMT_CTRL_PME_EN 0x00000002
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500261#define PMT_CTRL_READY 0x00000001 /* RO */
262
Ben Warren736fead2009-07-20 22:01:11 -0700263#define GPIO_CFG 0x88
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500264#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
265#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
266#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
267#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
268#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
269#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
270#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
271#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
272#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
273#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
274#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
275#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
276#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
277#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
278#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
279#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
280#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
281#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
282
Ben Warren736fead2009-07-20 22:01:11 -0700283#define GPT_CFG 0x8C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500284#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
285#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
286
Ben Warren736fead2009-07-20 22:01:11 -0700287#define GPT_CNT 0x90
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500288#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
289
Ben Warren736fead2009-07-20 22:01:11 -0700290#define ENDIAN 0x98
291#define FREE_RUN 0x9C
292#define RX_DROP 0xA0
293#define MAC_CSR_CMD 0xA4
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500294#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
295#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
296#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
297
Ben Warren736fead2009-07-20 22:01:11 -0700298#define MAC_CSR_DATA 0xA8
299#define AFC_CFG 0xAC
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500300#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
301#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
302#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
303#define AFC_CFG_FCMULT 0x00000008 /* R/W */
304#define AFC_CFG_FCBRD 0x00000004 /* R/W */
305#define AFC_CFG_FCADD 0x00000002 /* R/W */
306#define AFC_CFG_FCANY 0x00000001 /* R/W */
307
Ben Warren736fead2009-07-20 22:01:11 -0700308#define E2P_CMD 0xB0
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500309#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
310#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
311#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
312#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
313#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
314#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
315#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
316#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
317#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
318#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
319#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
320#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
321#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
322
Ben Warren736fead2009-07-20 22:01:11 -0700323#define E2P_DATA 0xB4
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500324#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
325/* end of LAN register offsets and bit definitions */
326
327/* MAC Control and Status registers */
328#define MAC_CR 0x01 /* R/W */
329
330/* MAC_CR - MAC Control Register */
331#define MAC_CR_RXALL 0x80000000
332/* TODO: delete this bit? It is not described in the data sheet. */
333#define MAC_CR_HBDIS 0x10000000
334#define MAC_CR_RCVOWN 0x00800000
335#define MAC_CR_LOOPBK 0x00200000
336#define MAC_CR_FDPX 0x00100000
337#define MAC_CR_MCPAS 0x00080000
338#define MAC_CR_PRMS 0x00040000
339#define MAC_CR_INVFILT 0x00020000
340#define MAC_CR_PASSBAD 0x00010000
341#define MAC_CR_HFILT 0x00008000
342#define MAC_CR_HPFILT 0x00002000
343#define MAC_CR_LCOLL 0x00001000
344#define MAC_CR_BCAST 0x00000800
345#define MAC_CR_DISRTY 0x00000400
346#define MAC_CR_PADSTR 0x00000100
347#define MAC_CR_BOLMT_MASK 0x000000C0
348#define MAC_CR_DFCHK 0x00000020
349#define MAC_CR_TXEN 0x00000008
350#define MAC_CR_RXEN 0x00000004
351
352#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
353#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
354#define HASHH 0x04 /* R/W */
355#define HASHL 0x05 /* R/W */
356
357#define MII_ACC 0x06 /* R/W */
358#define MII_ACC_PHY_ADDR 0x0000F800
359#define MII_ACC_MIIRINDA 0x000007C0
360#define MII_ACC_MII_WRITE 0x00000002
361#define MII_ACC_MII_BUSY 0x00000001
362
363#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
364
365#define FLOW 0x08 /* R/W */
366#define FLOW_FCPT 0xFFFF0000
367#define FLOW_FCPASS 0x00000004
368#define FLOW_FCEN 0x00000002
369#define FLOW_FCBSY 0x00000001
370
371#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
372#define VLAN1_VTI1 0x0000ffff
373
374#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
375#define VLAN2_VTI2 0x0000ffff
376
377#define WUFF 0x0B /* WO */
378
379#define WUCSR 0x0C /* R/W */
380#define WUCSR_GUE 0x00000200
381#define WUCSR_WUFR 0x00000040
382#define WUCSR_MPR 0x00000020
383#define WUCSR_WAKE_EN 0x00000004
384#define WUCSR_MPEN 0x00000002
385
386/* Chip ID values */
Phil Edworthyaf5de5d2011-05-31 03:53:11 +0000387#define CHIP_89218 0x218a
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500388#define CHIP_9115 0x115
389#define CHIP_9116 0x116
390#define CHIP_9117 0x117
391#define CHIP_9118 0x118
392#define CHIP_9211 0x9211
393#define CHIP_9215 0x115a
394#define CHIP_9216 0x116a
395#define CHIP_9217 0x117a
396#define CHIP_9218 0x118a
Daniel Mackc55096c2009-04-08 13:23:38 +0200397#define CHIP_9220 0x9220
Andreas Pretzsch2ea20ef2009-07-09 21:50:05 +0200398#define CHIP_9221 0x9221
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500399
400struct chip_id {
401 u16 id;
402 char *name;
403};
404
405static const struct chip_id chip_ids[] = {
Phil Edworthyaf5de5d2011-05-31 03:53:11 +0000406 { CHIP_89218, "LAN89218" },
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500407 { CHIP_9115, "LAN9115" },
408 { CHIP_9116, "LAN9116" },
409 { CHIP_9117, "LAN9117" },
410 { CHIP_9118, "LAN9118" },
411 { CHIP_9211, "LAN9211" },
412 { CHIP_9215, "LAN9215" },
413 { CHIP_9216, "LAN9216" },
414 { CHIP_9217, "LAN9217" },
415 { CHIP_9218, "LAN9218" },
Daniel Mackc55096c2009-04-08 13:23:38 +0200416 { CHIP_9220, "LAN9220" },
Andreas Pretzsch2ea20ef2009-07-09 21:50:05 +0200417 { CHIP_9221, "LAN9221" },
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500418 { 0, NULL },
419};
420
Ben Warren736fead2009-07-20 22:01:11 -0700421static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500422{
Ben Warren736fead2009-07-20 22:01:11 -0700423 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500424 ;
Ben Warren736fead2009-07-20 22:01:11 -0700425 smc911x_reg_write(dev, MAC_CSR_CMD,
426 MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
427 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500428 ;
429
Ben Warren736fead2009-07-20 22:01:11 -0700430 return smc911x_reg_read(dev, MAC_CSR_DATA);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500431}
432
Ben Warren736fead2009-07-20 22:01:11 -0700433static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500434{
Ben Warren736fead2009-07-20 22:01:11 -0700435 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500436 ;
Ben Warren736fead2009-07-20 22:01:11 -0700437 smc911x_reg_write(dev, MAC_CSR_DATA, data);
438 smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
439 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500440 ;
441}
442
Ben Warren736fead2009-07-20 22:01:11 -0700443static int smc911x_detect_chip(struct eth_device *dev)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500444{
445 unsigned long val, i;
446
Ben Warren736fead2009-07-20 22:01:11 -0700447 val = smc911x_reg_read(dev, BYTE_TEST);
Olof Johansson2a6cc972009-09-29 10:21:29 -0400448 if (val == 0xffffffff) {
449 /* Special case -- no chip present */
450 return -1;
451 } else if (val != 0x87654321) {
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500452 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
453 return -1;
454 }
455
Ben Warren736fead2009-07-20 22:01:11 -0700456 val = smc911x_reg_read(dev, ID_REV) >> 16;
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500457 for (i = 0; chip_ids[i].id != 0; i++) {
458 if (chip_ids[i].id == val) break;
459 }
460 if (!chip_ids[i].id) {
461 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
462 return -1;
463 }
464
Olof Johansson2a6cc972009-09-29 10:21:29 -0400465 dev->priv = (void *)&chip_ids[i];
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500466
467 return 0;
468}
469
Ben Warren736fead2009-07-20 22:01:11 -0700470static void smc911x_reset(struct eth_device *dev)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500471{
472 int timeout;
473
474 /* Take out of PM setting first */
Ben Warren736fead2009-07-20 22:01:11 -0700475 if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) {
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500476 /* Write to the bytetest will take out of powerdown */
Ben Warren736fead2009-07-20 22:01:11 -0700477 smc911x_reg_write(dev, BYTE_TEST, 0x0);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500478
479 timeout = 10;
480
Ben Warren736fead2009-07-20 22:01:11 -0700481 while (timeout-- &&
482 !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500483 udelay(10);
484 if (!timeout) {
485 printf(DRIVERNAME
486 ": timeout waiting for PM restore\n");
487 return;
488 }
489 }
490
491 /* Disable interrupts */
Ben Warren736fead2009-07-20 22:01:11 -0700492 smc911x_reg_write(dev, INT_EN, 0);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500493
Ben Warren736fead2009-07-20 22:01:11 -0700494 smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500495
496 timeout = 1000;
Ben Warren736fead2009-07-20 22:01:11 -0700497 while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500498 udelay(10);
499
500 if (!timeout) {
501 printf(DRIVERNAME ": reset timeout\n");
502 return;
503 }
504
505 /* Reset the FIFO level and flow control settings */
Ben Warren736fead2009-07-20 22:01:11 -0700506 smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
507 smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500508
509 /* Set to LED outputs */
Ben Warren736fead2009-07-20 22:01:11 -0700510 smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500511}
512
513#endif