blob: 1f52efcf5bdf33ba11d2512d39e9cb32223a94fb [file] [log] [blame]
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0x40000000
27
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020028#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
30#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020031#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020032 /* (it will be used if there is no */
33 /* 'cpuclk' variable with valid value) */
34
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020035#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020036#define CONFIG_SYS_SMC_RXBUFLEN 128
37#define CONFIG_SYS_MAXIDLE 10
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020038#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
39
40#define CONFIG_BOOTCOUNT_LIMIT
41
42#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
43
44#define CONFIG_BOARD_TYPES 1 /* support board types */
45
46#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010047 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020048 "echo"
49
50#undef CONFIG_BOOTARGS
51
52#define CONFIG_EXTRA_ENV_SETTINGS \
53 "netdev=eth0\0" \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
55 "nfsroot=${serverip}:${rootpath}\0" \
56 "ramargs=setenv bootargs root=/dev/ram rw\0" \
57 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \
60 "flash_nfs=run nfsargs addip;" \
61 "bootm ${kernel_addr}\0" \
62 "flash_self=run ramargs addip;" \
63 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
64 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
65 "rootpath=/opt/eldk/ppc_8xx\0" \
Martin Krause11d9eec2007-09-26 17:55:56 +020066 "bootfile=/tftpboot/TQM885D/uImage\0" \
67 "fdt_addr=400C0000\0" \
68 "kernel_addr=40100000\0" \
69 "ramdisk_addr=40280000\0" \
70 "load=tftp 200000 ${u-boot}\0" \
71 "update=protect off 40000000 +${filesize};" \
72 "erase 40000000 +${filesize};" \
73 "cp.b 200000 40000000 ${filesize};" \
74 "protect on 40000000 +${filesize}\0" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020075 ""
76#define CONFIG_BOOTCOMMAND "run flash_self"
77
78#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020080
81#undef CONFIG_WATCHDOG /* watchdog disabled */
82
83#define CONFIG_STATUS_LED 1 /* Status LED enabled */
84
85#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86
87/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010088#define CONFIG_SYS_I2C
89#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
90#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
91#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020092/*
93 * Software (bit-bang) I2C driver configuration
94 */
95#define PB_SCL 0x00000020 /* PB 26 */
96#define PB_SDA 0x00000010 /* PB 27 */
97
98#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
99#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
100#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
101#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
102#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
103 else immr->im_cpm.cp_pbdat &= ~PB_SDA
104#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
105 else immr->im_cpm.cp_pbdat &= ~PB_SCL
106#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
109#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
110#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
111#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200112
113# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200115
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500116/*
117 * BOOTP options
118 */
119#define CONFIG_BOOTP_SUBNETMASK
120#define CONFIG_BOOTP_GATEWAY
121#define CONFIG_BOOTP_HOSTNAME
122#define CONFIG_BOOTP_BOOTPATH
123#define CONFIG_BOOTP_BOOTFILESIZE
124
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200125
126#define CONFIG_MAC_PARTITION
127#define CONFIG_DOS_PARTITION
128
Martin Krause11d9eec2007-09-26 17:55:56 +0200129#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200130
131#define CONFIG_TIMESTAMP /* but print image timestmps */
132
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200133
Jon Loeliger26946902007-07-04 22:30:50 -0500134/*
135 * Command line configuration.
136 */
137#include <config_cmd_default.h>
138
139#define CONFIG_CMD_ASKENV
140#define CONFIG_CMD_DATE
141#define CONFIG_CMD_DHCP
142#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100143#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500144#define CONFIG_CMD_I2C
145#define CONFIG_CMD_IDE
146#define CONFIG_CMD_MII
147#define CONFIG_CMD_NFS
148#define CONFIG_CMD_PING
149
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200150
151/*
152 * Miscellaneous configurable options
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LONGHELP /* undef to save memory */
155#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200156
Wolfgang Denk2751a952006-10-28 02:29:14 +0200157#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200159
Jon Loeliger26946902007-07-04 22:30:50 -0500160#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200162#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200164#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
170#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
171#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200172 memory test.*/
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200177
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200178/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500179 * Enable loopw command.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200180 */
181#define CONFIG_LOOPW
182
183/*
184 * Low Level Configuration Settings
185 * (address mappings, register initial values, etc.)
186 * You should know what you are doing if you make changes here.
187 */
188/*-----------------------------------------------------------------------
189 * Internal Memory Mapped Register
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_IMMR 0xFFF00000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200192
193/*-----------------------------------------------------------------------
194 * Definitions for initial stack pointer and data area (in DPRAM)
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200198#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200200
201/*-----------------------------------------------------------------------
202 * Start addresses for the final memory configuration
203 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_FLASH_BASE 0x40000000
208#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
209#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
210#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200211
212/*
213 * For booting Linux, the board info and command line data
214 * have to be in the first 8 MB of memory, since this is
215 * the maximum mapped by the Linux kernel during initialization.
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200218
219/*-----------------------------------------------------------------------
220 * FLASH organization
221 */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200222
Martin Krausee318d9e2007-09-27 11:10:08 +0200223/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200225#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
227#define CONFIG_SYS_FLASH_EMPTY_INFO
228#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
229#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
230#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200231
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200232#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
234#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
235#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200236
237/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200238#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
239#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200240
241/*-----------------------------------------------------------------------
242 * Hardware Information Block
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
245#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
246#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200247
248/*-----------------------------------------------------------------------
249 * Cache Configuration
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500252#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200254#endif
255
256/*-----------------------------------------------------------------------
257 * SYPCR - System Protection Control 11-9
258 * SYPCR can only be written once after reset!
259 *-----------------------------------------------------------------------
260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
261 */
262#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
265#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200267#endif
268
269/*-----------------------------------------------------------------------
270 * SIUMCR - SIU Module Configuration 11-6
271 *-----------------------------------------------------------------------
272 * PCMCIA config., multi-function pin tri-state
273 */
274#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200276#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200278#endif /* CONFIG_CAN_DRIVER */
279
280/*-----------------------------------------------------------------------
281 * TBSCR - Time Base Status and Control 11-26
282 *-----------------------------------------------------------------------
283 * Clear Reference Interrupt Status, Timebase freezing enabled
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200286
287/*-----------------------------------------------------------------------
288 * PISCR - Periodic Interrupt Status and Control 11-31
289 *-----------------------------------------------------------------------
290 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
291 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200293
294/*-----------------------------------------------------------------------
295 * SCCR - System Clock and reset Control Register 15-27
296 *-----------------------------------------------------------------------
297 * Set clock output, timebase and RTC source and divider,
298 * power management and some other internal clocks
299 */
300#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200302 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
303 SCCR_DFALCD00)
304
305/*-----------------------------------------------------------------------
306 * PCMCIA stuff
307 *-----------------------------------------------------------------------
308 *
309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
311#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
312#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
313#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
314#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
315#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
316#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
317#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200318
319/*-----------------------------------------------------------------------
320 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
321 *-----------------------------------------------------------------------
322 */
323
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000324#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200325#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
326
327#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
328#undef CONFIG_IDE_LED /* LED for ide not supported */
329#undef CONFIG_IDE_RESET /* reset for ide not supported */
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
332#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200337
338/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200340
341/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200343
344/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200346
347/*-----------------------------------------------------------------------
348 *
349 *-----------------------------------------------------------------------
350 *
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_DER 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200353
354/*
355 * Init Memory Controller:
356 *
357 * BR0/1 and OR0/1 (FLASH)
358 */
359
360#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
361#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
362
363/* used to re-map FLASH both when starting from SRAM or FLASH:
364 * restrict access enough to keep SRAM working (if any)
365 * but not too much to meddle with FLASH accesses
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
368#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200369
370/*
371 * FLASH timing: Default value of OR0 after reset
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200374 OR_SCY_6_CLK | OR_TRLX)
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
377#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
378#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
381#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
382#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200383
384/*
385 * BR2/3 and OR2/3 (SDRAM)
386 *
387 */
388#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
389#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
390#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
391
392/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
396#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200397
398#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
400#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200401#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
403#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
404#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
405#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200406 BR_PS_8 | BR_MS_UPMB | BR_V )
407#endif /* CONFIG_CAN_DRIVER */
408
409/*
410 * 4096 Rows from SDRAM example configuration
411 * 1000 factor s -> ms
412 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
413 * 4 Number of refresh cycles per period
414 * 64 Refresh cycle in ms per number of rows
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200417
418/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200419 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
420 *
421 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Jens Gehrlein492c7042007-09-27 14:54:46 +0200423 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
424 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
426 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
427 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
428 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Jens Gehrlein492c7042007-09-27 14:54:46 +0200429 *
430 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
431 * be met also in the default configuration, i.e. if environment variable
432 * 'cpuclk' is not set.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200433 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_MAMR_PTA 128
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200435
436/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200437 * Memory Periodic Timer Prescaler Register (MPTPR) values.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200438 */
Jens Gehrlein492c7042007-09-27 14:54:46 +0200439/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Jens Gehrlein492c7042007-09-27 14:54:46 +0200441/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200443
444/*
445 * MAMR settings for SDRAM
446 */
447
448/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200450 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
452/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200454 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
456/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200458 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
459 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
460
461/*
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200462 * Network configuration
463 */
464#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
465#define CONFIG_FEC_ENET /* enable ethernet on FEC */
466#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
467#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
468
Jon Loeliger26946902007-07-04 22:30:50 -0500469#if defined(CONFIG_CMD_MII)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500471#define CONFIG_MII_INIT 1
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200472#endif
473
474#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
475 switching to another netwok (if the
476 tried network is unreachable) */
477
Heiko Schocher48690d82010-07-20 17:45:02 +0200478#define CONFIG_ETHPRIME "SCC"
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200479
Heiko Schocher7026ead2010-02-09 15:50:27 +0100480/* pass open firmware flat tree */
481#define CONFIG_OF_LIBFDT 1
482#define CONFIG_OF_BOARD_SETUP 1
483#define CONFIG_HWCONFIG 1
484
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200485#endif /* __CONFIG_H */