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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2001
6 * James F. Dougherty (jfd@cs.stanford.edu)
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +00009 */
10
11/*
12 *
13 * Configuration settings for the MOUSSE board.
14 * See also: http://www.vooha.com/
15 *
16 */
17
18/* ------------------------------------------------------------------------- */
19
20/*
21 * board/config.h - configuration options, board specific
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC824X 1
33#define CONFIG_MPC8240 1
34#define CONFIG_MOUSSE 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035
36#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010037#define CONFIG_SYS_LDSCRIPT "board/mousse/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_ADDR_MAP_B 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040
wdenkfe8c2802002-11-03 00:38:21 +000041#define CONFIG_CONS_INDEX 1
42#define CONFIG_BAUDRATE 9600
43#if 1
44#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
45#else
46#define CONFIG_BOOTCOMMAND "bootm ffe10000"
47#endif
48#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
49#define CONFIG_BOOTDELAY 3
Jon Loeliger8353e132007-07-08 14:14:17 -050050
51
52/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050053 * BOOTP options
54 */
55#define CONFIG_BOOTP_BOOTFILESIZE
56#define CONFIG_BOOTP_BOOTPATH
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_HOSTNAME
59
60
61/*
Jon Loeliger8353e132007-07-08 14:14:17 -050062 * Command line configuration.
63 */
64#include <config_cmd_default.h>
65
66#define CONFIG_CMD_ASKENV
67#define CONFIG_CMD_DATE
68
69
wdenkfe8c2802002-11-03 00:38:21 +000070#define CONFIG_ENV_OVERWRITE 1
71#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
72
73#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
Jon Loeliger8353e132007-07-08 14:14:17 -050074
wdenkfe8c2802002-11-03 00:38:21 +000075#include "../board/mousse/mousse.h"
76
77/*
78 * Miscellaneous configurable options
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#undef CONFIG_SYS_LONGHELP /* undef to save memory */
81#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
82#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
83#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
84#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
87#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkfe8c2802002-11-03 00:38:21 +000088
89/*-----------------------------------------------------------------------
90 * Start addresses for the final memory configuration
91 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkfe8c2802002-11-03 00:38:21 +000093 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkfe8c2802002-11-03 00:38:21 +000095
96#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE
wdenkfe8c2802002-11-03 00:38:21 +000098#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000100#endif
101
102#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */
wdenkfe8c2802002-11-03 00:38:21 +0000104#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
wdenkfe8c2802002-11-03 00:38:21 +0000106#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
110#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenkfe8c2802002-11-03 00:38:21 +0000111
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkfe8c2802002-11-03 00:38:21 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_ISA_MEM 0xFD000000
116#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkfe8c2802002-11-03 00:38:21 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_FLASH_BASE 0xFFF00000
119#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024))
120#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkfe8c2802002-11-03 00:38:21 +0000121#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
122#define FLASH_BASE0_SIZE 0x80000 /* 512K */
123#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
124 1MB - 64K FLASH0 SEG =960K
125 (size=0xf0000)*/
126
wdenkfe8c2802002-11-03 00:38:21 +0000127/*
128 * NS16550 Configuration
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_NS16550
131#define CONFIG_SYS_NS16550_SERIAL
wdenkfe8c2802002-11-03 00:38:21 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkfe8c2802002-11-03 00:38:21 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_NS16550_CLK 18432000
wdenkfe8c2802002-11-03 00:38:21 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_NS16550_COM1 0xFFE08080
wdenkfe8c2802002-11-03 00:38:21 +0000138
139/*-----------------------------------------------------------------------
140 * Definitions for initial stack pointer and data area (in DPRAM)
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
Wolfgang Denk553f0982010-10-26 13:32:32 +0200143#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200144#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000146
147/*
148 * Low Level Configuration Settings
149 * (address mappings, register initial values, etc.)
150 * You should know what you are doing if you make changes here.
151 * For the detail description refer to the MPC8240 user's manual.
152 */
153
154#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
155#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_HZ 1000
wdenkfe8c2802002-11-03 00:38:21 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_ETH_DEV_FN 0x00
159#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkfe8c2802002-11-03 00:38:21 +0000160
161
162 /* Bit-field values for MCCR1.
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_ROMNAL 8
165#define CONFIG_SYS_ROMFAL 8
wdenkfe8c2802002-11-03 00:38:21 +0000166
167 /* Bit-field values for MCCR2.
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */
wdenkfe8c2802002-11-03 00:38:21 +0000170
171 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BSTOPRE 0x79
wdenkfe8c2802002-11-03 00:38:21 +0000174
175#ifdef INCLUDE_ECC
176#define USE_ECC 1
177#else /* INCLUDE_ECC */
178#define USE_ECC 0
179#endif /* INCLUDE_ECC */
180
181
182 /* Bit-field values for MCCR3.
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
185#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */
wdenkfe8c2802002-11-03 00:38:21 +0000186
187 /* Bit-field values for MCCR4.
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
190#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
191#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
192#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
193#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
194#define CONFIG_SYS_ACTORW 2
195#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
wdenkfe8c2802002-11-03 00:38:21 +0000196
197/* Memory bank settings.
198 * Only bits 20-29 are actually used from these vales to set the
199 * start/end addresses. The upper two bits will always be 0, and the lower
200 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
201 * address. Refer to the MPC8240 book.
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */
wdenkfe8c2802002-11-03 00:38:21 +0000204
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_BANK0_START 0x00000000
207#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1)
208#define CONFIG_SYS_BANK0_ENABLE 1
209#define CONFIG_SYS_BANK1_START 0x3ff00000
210#define CONFIG_SYS_BANK1_END 0x3fffffff
211#define CONFIG_SYS_BANK1_ENABLE 0
212#define CONFIG_SYS_BANK2_START 0x3ff00000
213#define CONFIG_SYS_BANK2_END 0x3fffffff
214#define CONFIG_SYS_BANK2_ENABLE 0
215#define CONFIG_SYS_BANK3_START 0x3ff00000
216#define CONFIG_SYS_BANK3_END 0x3fffffff
217#define CONFIG_SYS_BANK3_ENABLE 0
218#define CONFIG_SYS_BANK4_START 0x3ff00000
219#define CONFIG_SYS_BANK4_END 0x3fffffff
220#define CONFIG_SYS_BANK4_ENABLE 0
221#define CONFIG_SYS_BANK5_START 0x3ff00000
222#define CONFIG_SYS_BANK5_END 0x3fffffff
223#define CONFIG_SYS_BANK5_ENABLE 0
224#define CONFIG_SYS_BANK6_START 0x3ff00000
225#define CONFIG_SYS_BANK6_END 0x3fffffff
226#define CONFIG_SYS_BANK6_ENABLE 0
227#define CONFIG_SYS_BANK7_START 0x3ff00000
228#define CONFIG_SYS_BANK7_END 0x3fffffff
229#define CONFIG_SYS_BANK7_ENABLE 0
wdenkfe8c2802002-11-03 00:38:21 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_ODCR 0x7f
wdenkfe8c2802002-11-03 00:38:21 +0000232
233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
wdenk8bde7f72003-06-27 21:31:46 +0000235 see 8240 book for details*/
wdenkfe8c2802002-11-03 00:38:21 +0000236#define PCI_MEM_SPACE1_START 0x80000000
237#define PCI_MEM_SPACE2_START 0xfd000000
238
239/* IBAT/DBAT Configuration */
240/* Ram: 64MB, starts at address-0, r/w instruction/data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
242#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
243#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
244#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
wdenkfe8c2802002-11-03 00:38:21 +0000245
246/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
wdenkfe8c2802002-11-03 00:38:21 +0000248#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
wdenkfe8c2802002-11-03 00:38:21 +0000250 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
251#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
wdenkfe8c2802002-11-03 00:38:21 +0000253#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
255#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
wdenkfe8c2802002-11-03 00:38:21 +0000256
257/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
259#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
260#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
261#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
wdenkfe8c2802002-11-03 00:38:21 +0000262
263/* PCI Memory region 2: PCI Devices in 0xFD space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
265#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
266#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
267#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
wdenkfe8c2802002-11-03 00:38:21 +0000268
269
270/*
271 * For booting Linux, the board info and command line data
272 * have to be in the first 8 MB of memory, since this is
273 * the maximum mapped by the Linux kernel during initialization.
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000276
277/*-----------------------------------------------------------------------
278 * FLASH organization
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */
281#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
wdenkfe8c2802002-11-03 00:38:21 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
284#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000285
286#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200287#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200288#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
289#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
wdenkfe8c2802002-11-03 00:38:21 +0000290#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200291#define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200292#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
293#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
294#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
wdenkfe8c2802002-11-03 00:38:21 +0000295#endif
296/*-----------------------------------------------------------------------
297 * Cache Configuration
298 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkfe8c2802002-11-03 00:38:21 +0000300
wdenkfe8c2802002-11-03 00:38:21 +0000301/* Localizations */
302#if 0
303#define CONFIG_ETHADDR 0:0:0:0:1:d
304#define CONFIG_IPADDR 172.16.40.113
305#define CONFIG_SERVERIP 172.16.40.111
306#else
307#define CONFIG_ETHADDR 0:0:0:0:1:d
308#define CONFIG_IPADDR 209.128.93.138
309#define CONFIG_SERVERIP 209.128.93.133
310#endif
311
312/*-----------------------------------------------------------------------
313 * PCI stuff
314 *-----------------------------------------------------------------------
315 */
316#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000317#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkfe8c2802002-11-03 00:38:21 +0000318#undef CONFIG_PCI_PNP
319
wdenkfe8c2802002-11-03 00:38:21 +0000320
321#define CONFIG_TULIP
322
323#endif /* __CONFIG_H */