blob: 6ae31d3a1f336ce32c6f65e972a36ae4c61e02ad [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard246771b2017-09-13 18:00:12 +02002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotard246771b2017-09-13 18:00:12 +02005 */
6
7#include <common.h>
8#include <asm/io.h>
Lokesh Vutlaf2ef2042018-04-26 18:21:30 +05309#include <asm/armv7_mpu.h>
Patrice Chotard246771b2017-09-13 18:00:12 +020010
Patrice Chotard246771b2017-09-13 18:00:12 +020011int arch_cpu_init(void)
12{
13 int i;
14
15 struct mpu_region_config stm32_region_config[] = {
16 /*
Patrice Chotardf5bd13e2018-02-28 17:15:00 +010017 * Make SDRAM area cacheable & executable.
Patrice Chotard246771b2017-09-13 18:00:12 +020018 */
Patrice Chotardf5bd13e2018-02-28 17:15:00 +010019#if defined(CONFIG_STM32F4)
Patrice Chotard246771b2017-09-13 18:00:12 +020020 { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
Patrice Chotardf5bd13e2018-02-28 17:15:00 +010021 O_I_WB_RD_WR_ALLOC, REGION_16MB },
22#endif
Patrice Chotard246771b2017-09-13 18:00:12 +020023
Patrice Chotard16f6cb42019-04-26 10:52:51 +020024 { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
25 SHARED_WRITE_BUFFERED, REGION_256MB },
26
Patrice Chotard362612d2018-10-02 09:03:10 +020027#if defined(CONFIG_STM32F7) || defined(CONFIG_STM32H7)
Patrice Chotardf5bd13e2018-02-28 17:15:00 +010028 { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
Patrice Chotard362612d2018-10-02 09:03:10 +020029 O_I_WB_RD_WR_ALLOC, REGION_512MB },
Patrice Chotardc729fb22017-11-16 08:59:21 +010030#endif
Patrice Chotard246771b2017-09-13 18:00:12 +020031 };
32
33 disable_mpu();
34 for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
35 mpu_config(&stm32_region_config[i]);
36 enable_mpu();
37
38 return 0;
39}