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Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2012 Freescale Semiconductor, Inc.
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05005 */
6
7/*
8 * p2020ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Kumar Galaebf9d522010-05-21 03:02:16 -050014#include "../board/freescale/common/ics307_clk.h"
15
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020016#ifdef CONFIG_36BIT
Kumar Galaa0f9e0e2009-09-10 16:26:37 -050017#define CONFIG_PHYS_64BIT
18#endif
19
Jerry Huang1ac63e42011-01-24 17:09:54 +000020#ifdef CONFIG_SDCARD
21#define CONFIG_SYS_RAMBOOT
22#define CONFIG_SYS_EXTRA_ENV_RELOC
23#define CONFIG_SYS_TEXT_BASE 0xf8f80000
24#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
25#endif
26
Jerry Huang21dd9af2011-01-24 17:09:56 +000027#ifdef CONFIG_SPIFLASH
28#define CONFIG_SYS_RAMBOOT
29#define CONFIG_SYS_EXTRA_ENV_RELOC
30#define CONFIG_SYS_TEXT_BASE 0xf8f80000
31#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
32#endif
33
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050034/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
37#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38#define CONFIG_P2020 1
39#define CONFIG_P2020DS 1
40#define CONFIG_MP 1 /* support multiple processors */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xeff80000
44#endif
45
Kumar Gala7a577fd2011-01-12 02:48:53 -060046#ifndef CONFIG_RESET_VECTOR_ADDRESS
47#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48#endif
49
Li Yang28a096e2010-12-30 11:17:44 -060050#define CONFIG_SYS_SRIO
51#define CONFIG_SRIO1 /* SRIO port 1 */
52#define CONFIG_SRIO2 /* SRIO port 2 */
53
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050054#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
55#define CONFIG_PCI 1 /* Enable PCI/PCIE */
56#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
57#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
58#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
59#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000060#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050061#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
62#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63
64#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zang29c35182009-06-30 13:56:23 +080065#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050066
67#define CONFIG_TSEC_ENET /* tsec ethernet support */
68#define CONFIG_ENV_OVERWRITE
69
Kumar Galaebf9d522010-05-21 03:02:16 -050070#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
71#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050072#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050073
74/*
75 * These can be toggled for performance analysis, otherwise use default.
76 */
77#define CONFIG_L2_CACHE /* toggle L2 cache */
78#define CONFIG_BTB /* toggle branch predition */
79
Jerry Huang9c4d8762011-01-24 17:09:53 +000080#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
81
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050082#define CONFIG_ENABLE_36BIT_PHYS 1
83
84#ifdef CONFIG_PHYS_64BIT
85#define CONFIG_ADDR_MAP 1
86#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
87#endif
88
York Sun84bc0032010-09-28 15:20:37 -070089#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
90#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
91#define CONFIG_SYS_MEMTEST_END 0x00400000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050092#define CONFIG_PANIC_HANG /* do not reset board on panic */
93
94/*
Jerry Huang1ac63e42011-01-24 17:09:54 +000095 * Config the L2 Cache
96 */
97#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
98#ifdef CONFIG_PHYS_64BIT
99#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
100#else
101#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
102#endif
103#define CONFIG_SYS_L2_SIZE (512 << 10)
104#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
105
Timur Tabie46fedf2011-08-04 18:03:41 -0500106#define CONFIG_SYS_CCSRBAR 0xffe00000
107#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500108
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500109/* DDR Setup */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500110#define CONFIG_VERY_BIG_RAM
Wolfgang Denkd24f2d32010-10-04 19:58:00 +0200111#ifdef CONFIG_DDR2
york394c46c2010-07-02 22:25:58 +0000112#define CONFIG_FSL_DDR2
113#else
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500114#define CONFIG_FSL_DDR3 1
york394c46c2010-07-02 22:25:58 +0000115#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500116
Wolfgang Denk8e5e9b92009-07-07 22:35:02 +0200117/* ECC will be enabled based on perf_mode environment variable */
118/* #define CONFIG_DDR_ECC */
119
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500120#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
121#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
122
123#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
125
126#define CONFIG_NUM_DDR_CONTROLLERS 1
127#define CONFIG_DIMM_SLOTS_PER_CTLR 1
128#define CONFIG_CHIP_SELECTS_PER_CTRL 2
129
130/* I2C addresses of SPD EEPROMs */
york394c46c2010-07-02 22:25:58 +0000131#define CONFIG_DDR_SPD
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500132#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
Kumar Galac39f44d2011-01-31 22:18:47 -0600133#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500134
135/* These are used when DDR doesn't use SPD. */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500136#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
137
138/* Default settings for "stable" mode */
139#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
140#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
141#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
142#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
143#define CONFIG_SYS_DDR_TIMING_3 0x00020000
144#define CONFIG_SYS_DDR_TIMING_0 0x00330804
145#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
146#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
147#define CONFIG_SYS_DDR_MODE_1 0x00421422
148#define CONFIG_SYS_DDR_MODE_2 0x00000000
149#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
150#define CONFIG_SYS_DDR_INTERVAL 0x61800100
151#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
152#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
153#define CONFIG_SYS_DDR_TIMING_4 0x00220001
154#define CONFIG_SYS_DDR_TIMING_5 0x03402400
155#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
156#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
157#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
158#define CONFIG_SYS_DDR_CONTROL2 0x24400011
159#define CONFIG_SYS_DDR_CDR1 0x00040000
160#define CONFIG_SYS_DDR_CDR2 0x00000000
161
162#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
163#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
164#define CONFIG_SYS_DDR_SBE 0x00010000
165
166/* Settings that differ for "performance" mode */
167#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
168#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
169#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
170#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
171#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
172#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
173
174/*
175 * The following set of values were tested for DDR2
176 * with a DDR3 to DDR2 interposer
177 *
178#define CONFIG_SYS_DDR_TIMING_3 0x00000000
179#define CONFIG_SYS_DDR_TIMING_0 0x00260802
180#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
181#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
182#define CONFIG_SYS_DDR_MODE_1 0x00480432
183#define CONFIG_SYS_DDR_MODE_2 0x00000000
184#define CONFIG_SYS_DDR_INTERVAL 0x06180100
185#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
186#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
187#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
188#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
189#define CONFIG_SYS_DDR_CONTROL 0xC3008000
190#define CONFIG_SYS_DDR_CONTROL2 0x04400010
191 *
192 */
193
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500194/*
195 * Memory map
196 *
197 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
198 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
199 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
200 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
201 *
202 * Localbus cacheable (TBD)
203 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
204 *
205 * Localbus non-cacheable
206 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
207 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
208 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
209 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
210 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
211 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
212 */
213
214/*
215 * Local Bus Definitions
216 */
217#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
218#ifdef CONFIG_PHYS_64BIT
219#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
220#else
221#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
222#endif
223
Timur Tabi7ee41102012-07-06 07:39:26 +0000224#define CONFIG_FLASH_BR_PRELIM \
225 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500226#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
227
228#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
229#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
230
231#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
232#define CONFIG_SYS_FLASH_QUIET_TEST
233#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
234
235#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
236#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500237#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
239
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200240#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500241
242#define CONFIG_FLASH_CFI_DRIVER
243#define CONFIG_SYS_FLASH_CFI
244#define CONFIG_SYS_FLASH_EMPTY_INFO
245#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
246
247#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
248
york394c46c2010-07-02 22:25:58 +0000249#define CONFIG_HWCONFIG /* enable hwconfig */
Timur Tabi5a469602010-04-01 10:49:42 -0500250#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
251
252#ifdef CONFIG_FSL_NGPIXIS
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500253#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
254#ifdef CONFIG_PHYS_64BIT
255#define PIXIS_BASE_PHYS 0xfffdf0000ull
256#else
257#define PIXIS_BASE_PHYS PIXIS_BASE
258#endif
259
260#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
261#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
262
Timur Tabi5a469602010-04-01 10:49:42 -0500263#define PIXIS_LBMAP_SWITCH 7
264#define PIXIS_LBMAP_MASK 0xf0
265#define PIXIS_LBMAP_SHIFT 4
266#define PIXIS_LBMAP_ALTBANK 0x20
267#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500268
269#define CONFIG_SYS_INIT_RAM_LOCK 1
270#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
yorkd51cc7a2010-07-02 22:26:03 +0000271#ifdef CONFIG_PHYS_64BIT
272#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
273#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
274/* The assembler doesn't like typecast */
275#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
278#else
279#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
280#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
281#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
282#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200283#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500284
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200285#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500286#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
287
288#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
289#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
290
291#define CONFIG_SYS_NAND_BASE 0xffa00000
292#ifdef CONFIG_PHYS_64BIT
293#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
294#else
295#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
296#endif
297#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
298 CONFIG_SYS_NAND_BASE + 0x40000, \
299 CONFIG_SYS_NAND_BASE + 0x80000,\
300 CONFIG_SYS_NAND_BASE + 0xC0000}
301#define CONFIG_SYS_MAX_NAND_DEVICE 4
302#define CONFIG_MTD_NAND_VERIFY_WRITE
303#define CONFIG_CMD_NAND 1
304#define CONFIG_NAND_FSL_ELBC 1
305#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
306
307/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500308#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
312 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500313#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500314 | OR_FCM_PGS /* Large Page*/ \
315 | OR_FCM_CSCT \
316 | OR_FCM_CST \
317 | OR_FCM_CHT \
318 | OR_FCM_SCY_1 \
319 | OR_FCM_TRLX \
320 | OR_FCM_EHTR)
321
322#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
323#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500324#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
325#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500326
Timur Tabi7ee41102012-07-06 07:39:26 +0000327#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500328 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
329 | BR_PS_8 /* Port Size = 8bit */ \
330 | BR_MS_FCM /* MSEL = FCM */ \
331 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500332#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000333#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500334 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
335 | BR_PS_8 /* Port Size = 8bit */ \
336 | BR_MS_FCM /* MSEL = FCM */ \
337 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500338#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500339
Timur Tabi7ee41102012-07-06 07:39:26 +0000340#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500341 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
342 | BR_PS_8 /* Port Size = 8bit */ \
343 | BR_MS_FCM /* MSEL = FCM */ \
344 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500345#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500346
347/* Serial Port - controlled on board with jumper J8
348 * open - index 2
349 * shorted - index 1
350 */
351#define CONFIG_CONS_INDEX 1
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500352#define CONFIG_SYS_NS16550
353#define CONFIG_SYS_NS16550_SERIAL
354#define CONFIG_SYS_NS16550_REG_SIZE 1
355#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
356
357#define CONFIG_SYS_BAUDRATE_TABLE \
Timur Tabifb365a82012-05-04 12:21:27 +0000358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500359
360#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
361#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
362
363/* Use the HUSH parser */
364#define CONFIG_SYS_HUSH_PARSER
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500365
366/*
367 * Pass open firmware flat tree
368 */
369#define CONFIG_OF_LIBFDT 1
370#define CONFIG_OF_BOARD_SETUP 1
371#define CONFIG_OF_STDOUT_VIA_ALIAS 1
372
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500373/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200374#define CONFIG_SYS_I2C
375#define CONFIG_SYS_I2C_FSL
376#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
377#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
378#define CONFIG_SYS_FSL_I2C_SPEED 400000
379#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
380#define CONFIG_SYS_FSL_I2C2_SPEED 400000
381#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500382#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Heiko Schocher00f792e2012-10-24 13:48:22 +0200383#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500384
385/*
386 * I2C2 EEPROM
387 */
388#define CONFIG_ID_EEPROM
389#ifdef CONFIG_ID_EEPROM
390#define CONFIG_SYS_I2C_EEPROM_NXID
391#endif
392#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
393#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
394#define CONFIG_SYS_EEPROM_BUS_NUM 0
395
396/*
Jerry Huang21dd9af2011-01-24 17:09:56 +0000397 * eSPI - Enhanced SPI
398 */
399#define CONFIG_FSL_ESPI
400
401#define CONFIG_SPI_FLASH
402#define CONFIG_SPI_FLASH_SPANSION
403
404#define CONFIG_CMD_SF
405#define CONFIG_SF_DEFAULT_SPEED 10000000
406#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
407
408/*
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500409 * General PCI
410 * Memory space is mapped 1-1, but I/O space must start from 0.
411 */
412
413/* controller 3, Slot 1, tgtid 3, Base address b000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600414#define CONFIG_SYS_PCIE3_NAME "Slot 1"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500415#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
416#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500417#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500418#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
419#else
420#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
421#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
422#endif
423#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
424#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
425#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
428#else
429#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
430#endif
431#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
432
433/* controller 2, direct to uli, tgtid 2, Base address 9000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600434#define CONFIG_SYS_PCIE2_NAME "ULI"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500435#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
436#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500437#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500438#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
439#else
440#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
441#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
442#endif
443#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
444#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
445#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
446#ifdef CONFIG_PHYS_64BIT
447#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
448#else
449#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
450#endif
451#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
452
453/* controller 1, Slot 2, tgtid 1, Base address a000 */
Kumar Gala4d5723d2010-12-17 07:01:00 -0600454#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500455#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
456#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500457#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500458#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
459#else
460#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
461#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
462#endif
463#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
464#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
465#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
466#ifdef CONFIG_PHYS_64BIT
467#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
468#else
469#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
470#endif
471#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
472
473#if defined(CONFIG_PCI)
474
475/*PCIE video card used*/
476#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
477
478/* video */
Andy Flemingd4ed6542013-01-24 01:55:11 -0600479#undef CONFIG_VIDEO
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500480
481#if defined(CONFIG_VIDEO)
482#define CONFIG_BIOSEMU
483#define CONFIG_CFB_CONSOLE
484#define CONFIG_VIDEO_SW_CURSOR
485#define CONFIG_VGA_AS_SINGLE_DEVICE
486#define CONFIG_ATI_RADEON_FB
487#define CONFIG_VIDEO_LOGO
488/*#define CONFIG_CONSOLE_CURSOR*/
489#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
490#endif
491
Li Yang28a096e2010-12-30 11:17:44 -0600492/* SRIO1 uses the same window as PCIE2 mem window */
493#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
494#ifdef CONFIG_PHYS_64BIT
495#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
496#else
497#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
498#endif
499#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
500
501/* SRIO2 uses the same window as PCIE1 mem window */
502#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
503#ifdef CONFIG_PHYS_64BIT
504#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
505#else
506#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
507#endif
508#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
509
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500510#define CONFIG_PCI_PNP /* do pci plug-and-play */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500511#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
512#define CONFIG_DOS_PARTITION
513#define CONFIG_SCSI_AHCI
514
515#ifdef CONFIG_SCSI_AHCI
516#define CONFIG_SATA_ULI5288
517#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
518#define CONFIG_SYS_SCSI_MAX_LUN 1
519#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
520#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
521#endif /* SCSI */
522
523#endif /* CONFIG_PCI */
524
525
526#if defined(CONFIG_TSEC_ENET)
527
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500528#define CONFIG_MII 1 /* MII PHY management */
529#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
530#define CONFIG_TSEC1 1
531#define CONFIG_TSEC1_NAME "eTSEC1"
532#define CONFIG_TSEC2 1
533#define CONFIG_TSEC2_NAME "eTSEC2"
534#define CONFIG_TSEC3 1
535#define CONFIG_TSEC3_NAME "eTSEC3"
536
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500537#define CONFIG_FSL_SGMII_RISER 1
538#define SGMII_RISER_PHY_OFFSET 0x1b
539
540#ifdef CONFIG_FSL_SGMII_RISER
541#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
542#endif
543
544#define TSEC1_PHY_ADDR 0
545#define TSEC2_PHY_ADDR 1
546#define TSEC3_PHY_ADDR 2
547
548#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
549#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
550#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
551
552#define TSEC1_PHYIDX 0
553#define TSEC2_PHYIDX 0
554#define TSEC3_PHYIDX 0
555
556#define CONFIG_ETHPRIME "eTSEC1"
557
558#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
559#endif /* CONFIG_TSEC_ENET */
560
561/*
562 * Environment
563 */
Jerry Huang1ac63e42011-01-24 17:09:54 +0000564#if defined(CONFIG_SDCARD)
565#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000566#define CONFIG_FSL_FIXED_MMC_LOCATION
Jerry Huang1ac63e42011-01-24 17:09:54 +0000567#define CONFIG_ENV_SIZE 0x2000
568#define CONFIG_SYS_MMC_ENV_DEV 0
Jerry Huang21dd9af2011-01-24 17:09:56 +0000569#elif defined(CONFIG_SPIFLASH)
570#define CONFIG_ENV_IS_IN_SPI_FLASH
571#define CONFIG_ENV_SPI_BUS 0
572#define CONFIG_ENV_SPI_CS 0
573#define CONFIG_ENV_SPI_MAX_HZ 10000000
574#define CONFIG_ENV_SPI_MODE 0
575#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
576#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
577#define CONFIG_ENV_SECT_SIZE 0x10000
Jerry Huang1ac63e42011-01-24 17:09:54 +0000578#else
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500579#define CONFIG_ENV_IS_IN_FLASH 1
580#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
581#define CONFIG_ENV_ADDR 0xfff80000
582#else
583#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
584#endif
585#define CONFIG_ENV_SIZE 0x2000
586#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Jerry Huang1ac63e42011-01-24 17:09:54 +0000587#endif
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500588
589#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
590#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
591
592/*
593 * Command line configuration.
594 */
595#include <config_cmd_default.h>
596
597#define CONFIG_CMD_IRQ
598#define CONFIG_CMD_PING
599#define CONFIG_CMD_I2C
600#define CONFIG_CMD_MII
601#define CONFIG_CMD_ELF
602#define CONFIG_CMD_IRQ
603#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500604#define CONFIG_CMD_REGINFO
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500605
606#if defined(CONFIG_PCI)
607#define CONFIG_CMD_PCI
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500608#define CONFIG_CMD_NET
609#define CONFIG_CMD_SCSI
610#define CONFIG_CMD_EXT2
611#endif
612
Roy Zang0ead6f22009-09-10 14:44:48 +0800613/*
614 * USB
615 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000616#define CONFIG_HAS_FSL_DR_USB
617#ifdef CONFIG_HAS_FSL_DR_USB
Jerry Huang9c4d8762011-01-24 17:09:53 +0000618#define CONFIG_USB_EHCI
619
620#ifdef CONFIG_USB_EHCI
Roy Zang0ead6f22009-09-10 14:44:48 +0800621#define CONFIG_CMD_USB
622#define CONFIG_USB_STORAGE
Roy Zang0ead6f22009-09-10 14:44:48 +0800623#define CONFIG_USB_EHCI_FSL
624#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Jerry Huang9c4d8762011-01-24 17:09:53 +0000625#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000626#endif
Roy Zang0ead6f22009-09-10 14:44:48 +0800627
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500628/*
Jerry Huang9c4d8762011-01-24 17:09:53 +0000629 * SDHC/MMC
630 */
631#define CONFIG_MMC
632
633#ifdef CONFIG_MMC
634#define CONFIG_FSL_ESDHC
635#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
636#define CONFIG_CMD_MMC
637#define CONFIG_GENERIC_MMC
638#endif
639
640#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
641#define CONFIG_CMD_EXT2
642#define CONFIG_CMD_FAT
643#define CONFIG_DOS_PARTITION
644#endif
645
646/*
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500647 * Miscellaneous configurable options
648 */
649#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500650#define CONFIG_CMDLINE_EDITING /* Command-line editing */
651#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500652#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
653#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
654#if defined(CONFIG_CMD_KGDB)
655#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
656#else
657#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
658#endif
659#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
660#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
661#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
662#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
663
664/*
665 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500666 * have to be in the first 64 MB of memory, since this is
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500667 * the maximum mapped by the Linux kernel during initialization.
668 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500669#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
670#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500671
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500672#if defined(CONFIG_CMD_KGDB)
673#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
674#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
675#endif
676
677/*
678 * Environment Configuration
679 */
680
681/* The mac addresses for all ethernet interface */
682#if defined(CONFIG_TSEC_ENET)
683#define CONFIG_HAS_ETH0
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500684#define CONFIG_HAS_ETH1
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500685#define CONFIG_HAS_ETH2
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500686#endif
687
688#define CONFIG_IPADDR 192.168.1.254
689
690#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000691#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000692#define CONFIG_BOOTFILE "uImage"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500693#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
694
695#define CONFIG_SERVERIP 192.168.1.1
696#define CONFIG_GATEWAYIP 192.168.1.1
697#define CONFIG_NETMASK 255.255.255.0
698
699/* default location for tftp and bootm */
700#define CONFIG_LOADADDR 1000000
701
702#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500703
704#define CONFIG_BAUDRATE 115200
705
706#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200707"perf_mode=performance\0" \
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000708 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
709 "usb1:dr_mode=host,phy_type=ulpi\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200710"netdev=eth0\0" \
711"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
712"tftpflash=tftpboot $loadaddr $uboot; " \
713 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
714 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
715 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
716 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
717 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
718"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
Li Yangccc4a8d2011-01-24 17:09:52 +0000719 "console=$consoledev,$baudrate $othbootargs;" \
720 "tftp $loadaddr $bootfile;" \
721 "tftp $fdtaddr $fdtfile;" \
722 "bootm $loadaddr - $fdtaddr" \
Marek Vasut5368c552012-09-23 17:41:24 +0200723"consoledev=ttyS0\0" \
724"ramdiskaddr=2000000\0" \
725"ramdiskfile=p2020ds/ramdisk.uboot\0" \
726"fdtaddr=c00000\0" \
727"othbootargs=cache-sram-size=0x10000\0" \
728"fdtfile=p2020ds/p2020ds.dtb\0" \
729"bdev=sda3\0" \
730"partition=scsi 0:0\0"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500731
732#define CONFIG_HDBOOT \
733 "setenv bootargs root=/dev/$bdev rw " \
734 "console=$consoledev,$baudrate $othbootargs;" \
Li Yangccc4a8d2011-01-24 17:09:52 +0000735 "ext2load $partition $loadaddr $bootfile;" \
736 "ext2load $partition $fdtaddr $fdtfile;" \
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500737 "bootm $loadaddr - $fdtaddr"
738
739#define CONFIG_NFSBOOTCOMMAND \
740 "setenv bootargs root=/dev/nfs rw " \
741 "nfsroot=$serverip:$rootpath " \
742 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
743 "console=$consoledev,$baudrate $othbootargs;" \
744 "tftp $loadaddr $bootfile;" \
745 "tftp $fdtaddr $fdtfile;" \
746 "bootm $loadaddr - $fdtaddr"
747
748#define CONFIG_RAMBOOTCOMMAND \
749 "setenv bootargs root=/dev/ram rw " \
750 "console=$consoledev,$baudrate $othbootargs;" \
751 "tftp $ramdiskaddr $ramdiskfile;" \
752 "tftp $loadaddr $bootfile;" \
753 "tftp $fdtaddr $fdtfile;" \
754 "bootm $loadaddr $ramdiskaddr $fdtaddr"
755
756#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
757
758#endif /* __CONFIG_H */