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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang2c62c562015-11-04 14:25:13 +08002/*
3 * Atmel PIO4 device driver
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang2c62c562015-11-04 14:25:13 +08007 */
8#include <common.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +08009#include <clk.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080010#include <dm.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080011#include <fdtdec.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080012#include <asm/arch/hardware.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080013#include <asm/gpio.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080014#include <mach/gpio.h>
15#include <mach/atmel_pio4.h>
16
Wenyou Yangee3311d2016-07-20 17:16:26 +080017DECLARE_GLOBAL_DATA_PTR;
18
Wenyou Yang2c62c562015-11-04 14:25:13 +080019static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
20{
21 struct atmel_pio4_port *base = NULL;
22
23 switch (port) {
24 case AT91_PIO_PORTA:
25 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
26 break;
27 case AT91_PIO_PORTB:
28 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
29 break;
30 case AT91_PIO_PORTC:
31 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
32 break;
33 case AT91_PIO_PORTD:
34 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
35 break;
36 default:
37 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
38 port);
39 break;
40 }
41
42 return base;
43}
44
45static int atmel_pio4_config_io_func(u32 port, u32 pin,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030046 u32 func, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080047{
48 struct atmel_pio4_port *port_base;
49 u32 reg, mask;
50
Wenyou Yang46ed9382016-07-20 17:16:25 +080051 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -060052 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080053
54 port_base = atmel_pio4_port_base(port);
55 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -060056 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080057
58 mask = 1 << pin;
59 reg = func;
Ludovic Desroches8ee54672018-04-24 10:16:01 +030060 reg |= config;
Wenyou Yang2c62c562015-11-04 14:25:13 +080061
62 writel(mask, &port_base->mskr);
63 writel(reg, &port_base->cfgr);
64
65 return 0;
66}
67
Ludovic Desroches8ee54672018-04-24 10:16:01 +030068int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080069{
70 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080071 ATMEL_PIO_CFGR_FUNC_GPIO,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030072 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080073}
74
Ludovic Desroches8ee54672018-04-24 10:16:01 +030075int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080076{
77 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080078 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030079 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080080}
81
Ludovic Desroches8ee54672018-04-24 10:16:01 +030082int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080083{
84 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080085 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030086 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080087}
88
Ludovic Desroches8ee54672018-04-24 10:16:01 +030089int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080090{
91 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080092 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030093 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080094}
95
Ludovic Desroches8ee54672018-04-24 10:16:01 +030096int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080097{
98 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080099 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300100 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800101}
102
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300103int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800104{
105 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800106 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300107 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800108}
109
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300110int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800111{
112 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800113 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300114 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800115}
116
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300117int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800118{
119 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800120 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300121 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800122}
123
124int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
125{
126 struct atmel_pio4_port *port_base;
127 u32 reg, mask;
128
Wenyou Yang46ed9382016-07-20 17:16:25 +0800129 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600130 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800131
132 port_base = atmel_pio4_port_base(port);
133 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600134 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800135
136 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800137 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800138
139 writel(mask, &port_base->mskr);
140 writel(reg, &port_base->cfgr);
141
142 if (value)
143 writel(mask, &port_base->sodr);
144 else
145 writel(mask, &port_base->codr);
146
147 return 0;
148}
149
150int atmel_pio4_get_pio_input(u32 port, u32 pin)
151{
152 struct atmel_pio4_port *port_base;
153 u32 reg, mask;
154
Wenyou Yang46ed9382016-07-20 17:16:25 +0800155 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600156 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800157
158 port_base = atmel_pio4_port_base(port);
159 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600160 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800161
162 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800163 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800164
165 writel(mask, &port_base->mskr);
166 writel(reg, &port_base->cfgr);
167
168 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
169}
170
Simon Glassbcee8d62019-12-06 21:41:35 -0700171#if CONFIG_IS_ENABLED(DM_GPIO)
Wenyou Yangee3311d2016-07-20 17:16:26 +0800172
173struct atmel_pioctrl_data {
174 u32 nbanks;
175};
176
177struct atmel_pio4_platdata {
178 struct atmel_pio4_port *reg_base;
179};
180
181static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
182 u32 bank)
183{
184 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
185 struct atmel_pio4_port *port_base =
186 (struct atmel_pio4_port *)((u32)plat->reg_base +
187 ATMEL_PIO_BANK_OFFSET * bank);
188
189 return port_base;
190}
191
Wenyou Yang2c62c562015-11-04 14:25:13 +0800192static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
193{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800194 u32 bank = ATMEL_PIO_BANK(offset);
195 u32 line = ATMEL_PIO_LINE(offset);
196 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
197 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800198
199 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800200
201 clrbits_le32(&port_base->cfgr,
202 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800203
204 return 0;
205}
206
207static int atmel_pio4_direction_output(struct udevice *dev,
208 unsigned offset, int value)
209{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800210 u32 bank = ATMEL_PIO_BANK(offset);
211 u32 line = ATMEL_PIO_LINE(offset);
212 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
213 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800214
215 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800216
217 clrsetbits_le32(&port_base->cfgr,
218 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800219
220 if (value)
221 writel(mask, &port_base->sodr);
222 else
223 writel(mask, &port_base->codr);
224
225 return 0;
226}
227
228static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
229{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800230 u32 bank = ATMEL_PIO_BANK(offset);
231 u32 line = ATMEL_PIO_LINE(offset);
232 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
233 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800234
235 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
236}
237
238static int atmel_pio4_set_value(struct udevice *dev,
239 unsigned offset, int value)
240{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800241 u32 bank = ATMEL_PIO_BANK(offset);
242 u32 line = ATMEL_PIO_LINE(offset);
243 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
244 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800245
246 if (value)
247 writel(mask, &port_base->sodr);
248 else
249 writel(mask, &port_base->codr);
250
251 return 0;
252}
253
254static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
255{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800256 u32 bank = ATMEL_PIO_BANK(offset);
257 u32 line = ATMEL_PIO_LINE(offset);
258 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
259 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800260
261 writel(mask, &port_base->mskr);
262
263 return (readl(&port_base->cfgr) &
Wenyou Yang46ed9382016-07-20 17:16:25 +0800264 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800265}
266
267static const struct dm_gpio_ops atmel_pio4_ops = {
268 .direction_input = atmel_pio4_direction_input,
269 .direction_output = atmel_pio4_direction_output,
270 .get_value = atmel_pio4_get_value,
271 .set_value = atmel_pio4_set_value,
272 .get_function = atmel_pio4_get_function,
273};
274
Wenyou Yangee3311d2016-07-20 17:16:26 +0800275static int atmel_pio4_bind(struct udevice *dev)
276{
Simon Glass79fc0c72017-05-17 17:18:06 -0600277 return dm_scan_fdt_dev(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800278}
279
Wenyou Yang2c62c562015-11-04 14:25:13 +0800280static int atmel_pio4_probe(struct udevice *dev)
281{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800282 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800283 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800284 struct atmel_pioctrl_data *pioctrl_data;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800285 struct clk clk;
286 fdt_addr_t addr_base;
287 u32 nbanks;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800288 int ret;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800289
Wenyou Yangee3311d2016-07-20 17:16:26 +0800290 ret = clk_get_by_index(dev, 0, &clk);
291 if (ret)
292 return ret;
293
Wenyou Yangee3311d2016-07-20 17:16:26 +0800294 ret = clk_enable(&clk);
295 if (ret)
296 return ret;
297
298 clk_free(&clk);
299
Simon Glassa821c4a2017-05-17 17:18:05 -0600300 addr_base = devfdt_get_addr(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800301 if (addr_base == FDT_ADDR_T_NONE)
302 return -EINVAL;
303
304 plat->reg_base = (struct atmel_pio4_port *)addr_base;
305
306 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
307 nbanks = pioctrl_data->nbanks;
308
Simon Glasse160f7d2017-01-17 16:52:55 -0700309 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
310 NULL);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800311 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800312
313 return 0;
314}
315
Wenyou Yangee3311d2016-07-20 17:16:26 +0800316/*
317 * The number of banks can be different from a SoC to another one.
318 * We can have up to 16 banks.
319 */
320static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
321 .nbanks = 4,
322};
323
324static const struct udevice_id atmel_pio4_ids[] = {
325 {
326 .compatible = "atmel,sama5d2-gpio",
327 .data = (ulong)&atmel_sama5d2_pioctrl_data,
328 },
329 {}
330};
331
Wenyou Yang2c62c562015-11-04 14:25:13 +0800332U_BOOT_DRIVER(gpio_atmel_pio4) = {
333 .name = "gpio_atmel_pio4",
334 .id = UCLASS_GPIO,
335 .ops = &atmel_pio4_ops,
336 .probe = atmel_pio4_probe,
Wenyou Yangee3311d2016-07-20 17:16:26 +0800337 .bind = atmel_pio4_bind,
338 .of_match = atmel_pio4_ids,
339 .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
Wenyou Yang2c62c562015-11-04 14:25:13 +0800340};
Wenyou Yangee3311d2016-07-20 17:16:26 +0800341
Wenyou Yang2c62c562015-11-04 14:25:13 +0800342#endif